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WO2011066863A1 - Semiconductor chip with backside metallization and arrangement of said chip on a carrier - Google Patents

Semiconductor chip with backside metallization and arrangement of said chip on a carrier Download PDF

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Publication number
WO2011066863A1
WO2011066863A1 PCT/EP2009/066367 EP2009066367W WO2011066863A1 WO 2011066863 A1 WO2011066863 A1 WO 2011066863A1 EP 2009066367 W EP2009066367 W EP 2009066367W WO 2011066863 A1 WO2011066863 A1 WO 2011066863A1
Authority
WO
WIPO (PCT)
Prior art keywords
backside metallization
carrier
interconnect
semiconductor chip
terminals
Prior art date
Application number
PCT/EP2009/066367
Other languages
French (fr)
Inventor
Tomas Fric
Jeroen Bouwman
Léon C. M. van den Oever
Original Assignee
Epcos Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos Ag filed Critical Epcos Ag
Priority to PCT/EP2009/066367 priority Critical patent/WO2011066863A1/en
Publication of WO2011066863A1 publication Critical patent/WO2011066863A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the invention relates to electric signal connections between a semiconductor chip and a carrier.
  • a semiconductor chip especially a GaAs die, is conventional ⁇ ly mounted on a carrier by means of a glue layer or by
  • soldering The electric connections are realized by bond wires or by bumps, solder balls or studs in conjunction with a flip-chip mounting.
  • the backside contact pad is a coplanar waveguide section. It is an object of the invention to present a semiconductor chip suitable for mounting on a carrier. It is a further object to disclose a new arrangement of a semiconductor chip on a carrier.
  • the invention is based on a combination of interconnects through the semiconductor chip and a structured backside metallization. It offers new applications and possibilities for power amplifiers or switches, for example.
  • semiconductor chip comprises an electronic device or circuit at the front side and a structured backside metallization on the opposite rear side. Terminals of the electronic device or circuit are electrically connected with a wiring including the backside metallization and at least one interconnect through the substrate, the interconnect being electrically connected with the backside metallization.
  • an inductor formed by a spiral or an RF transmission line formed by a conductor track is structured in the backside metallization.
  • the semiconductor chip comprises a substrate of GaAs .
  • the semiconductor chip with backside metallization can be arranged on a carrier having contact areas .
  • the chip can be arranged on the carrier with the front side of the chip facing the carrier, and at least one of the terminals of the electronic device or circuit of the chip can be electrically conductively connected to one of the contact areas of the carrier.
  • the semiconductor chip can be arranged on the carrier with the rear side facing the carrier, at least one of the contact areas of the carrier being electrically conductively connected to the backside metallization of the semiconductor chip, and at least one of the contact areas of the carrier is electrically conductively connected to one of the terminals on the chip by means of a bond wire.
  • the semiconductor chip is arranged on the carrier with the front side facing the carrier and a bond wire connects the backside metalliza ⁇ tion with one of the contact areas of the carrier.
  • the semiconductor chip is arranged on the carrier with the rear side facing the carrier, a contact area of the carrier that is electrically conductively connected to the backside metallization is provided for the transmission of an RF signal, and a contact area that is electrically conductively connected by means of a bond wire is provided for a DC connection.
  • the interconnect of the semiconductor chip and a further interconnect of the semiconductor chip electrically connect terminals of the electronic device or circuit via the backside metallization.
  • the chip comprises an inductor formed by a spiral or an RF transmission line formed by a conductor track in the backside metallization.
  • an electrically conductive bump is arranged on a contact area of the carrier and a conductor track of the wiring connects the bump with an interconnect .
  • an electrically conductive bump is arranged between an interconnect of the chip and a contact area of the carrier.
  • the interconnect can be formed by a through-wafer contact or backvia, which is available in a standard GaAs technology, for example.
  • An interconnect through the substrate of the semiconductor chip provides a low-ohmic and low-inductance connection between a front side metallization and a backside metallization belonging to a wiring of the chip.
  • a backside metallization has a typical thickness of about 4.5 ⁇ and can be gold, for example.
  • the backside metallization usually forms an electric grounding and may also be used as a heat sink. To prolong the lifetime of the dicing saw, the backside metallization is not present in a dicing street provided for the separation of individual chips from the wafer.
  • the backside metallization is structured to form part of the wiring of the chip.
  • the backside metallization is structured to form part of the wiring of the chip.
  • FIG. 1 shows a perspective view of an arrangement of a
  • FIG. 2 shows the structure of the backside metallization of the chip of the embodiment according to FIG. 1.
  • FIG. 3 shows a perspective view of an arrangement of a
  • FIG. 4 shows a perspective view of an arrangement of a
  • semiconductor chip having a backside metallization mounted in flip-chip technology on a carrier.
  • FIG. 5 shows a perspective view of an arrangement of a
  • FIG. 6 shows a perspective view of a further embodiment of an arrangement according to FIG. 5.
  • FIG. 1 shows a perspective view of an embodiment of an arrangement of a semiconductor chip having a structured backside metallization, which forms part of a wiring, on a carrier.
  • the carrier 10 can be any substrate or PCB (printed circuit board) , which is used for standard surface mounted devices.
  • the semiconductor chip 11 comprises a substrate 1 of semiconductor material having a front side 2 and a rear side 3.
  • An electronic device or circuit 4 not shown in detail in FIG. 1, is arranged at the front side 2.
  • the electronic de ⁇ vice or circuit 4 is provided with terminals 5, which can be formed by contact pads or the like.
  • a wiring is electrically connected with the terminals and can comprise conventional metallization layers and intermetal dielectric, for example.
  • the invention further comprises an interconnect 8 through the substrate 1 and a structured backside metallization 7.
  • the carrier 10 is provided with contact areas 15.
  • Contact areas provided in the backside metallization 7 of the semiconductor chip 11 are arranged on the contact areas 15 of the carrier 10 and fastened to the contact areas 15 by means of an electrically conductive glue or a solder material.
  • the corresponding portions of the backside metallization 7 can be provided for a grounding, a heat sink or other conventional passive components formed in a metal layer, and can comprise conductor tracks connecting the interconnects 8, 9 to one another or to the contact areas.
  • the backside metallization 7 and the contact areas 15 can also be used for signals, especially DC signals or RF signals, for example.
  • the backside metallization 7 may comprise conducting spirals 12 used as inductors and/or conductor tracks 13 which can be used as re-routing or redirection on the rear side or as RF transmission lines, for example.
  • the areas of the backside metallization 7 that are contacted with the contact areas 15 of the carrier 10 can be terminals of emitter, base and collector of a heterobipolar transistor, for example.
  • any circuit components of an electronic device or circuit 4 integrated in the substrate 1 can be connected via the structured backside metallization 7.
  • a structured backside metallization 7 it is especially possible in RF devices to separate backside connections for different RF stages in order to eliminate ground coupling. Grounding and ground coupling are important with respect to the performance and stability of RF devices, in order to avoid oscillations.
  • FIG. 2 shows an example of the structured backside metalliza ⁇ tion 7 forming part of a wiring 6, which encompasses the backside metallization 7, interconnects 8, terminals 5 of the electronic device or circuit 4, and possibly further metal ⁇ lizations and interconnects of a conventional wiring formed by metal layers and vias that are arranged in an intermetal dielectric.
  • FIG. 2 also shows spirals 12 of conductor tracks used as inductors. Contact pads of the backside metallization 7 are in contact with the interconnects 8, which are indi ⁇ cated with broken lines as hidden contours.
  • the conductor track 13 can be provided to serve as a connection between the interconnect 8 and the further interconnect 9 and thus to provide a re-routing or redistribution on the backside of the semiconductor chip 11.
  • the larger areas of the backside metallization 7 shown on the left side of FIG. 2 can be contact areas that are provided to connect terminals of the integrated electronic device or circuit 4 with corresponding contact areas 15 of the carrier 10.
  • the three contact areas shown in FIG. 2 can be terminals of an emitter, a base and a collector of a heterobipolar transistor, for example.
  • the relatively thick backside metallization 7 is especially favorable to realize inductors in the form of spirals 12 such as shown in FIG. 2.
  • the thick metal layer of the backside metallization 7 gives a high quality factor of the inductor.
  • FIG. 3 shows a perspective view of an arrangement of a semiconductor chip 11 having a structured backside metallization 7, in which the rear side 3 of the semiconductor chip 11 faces the carrier 10 and the front side 2 of the semiconductor chip 11 carries terminals 5 which are electrically connected to contact areas 15 of the carrier 10 by means of bond wires 14.
  • the terminals 5 on the front side 2 can thus be connected to the backside metallization 7 via the interconnects 8 or can be connected to contact areas 15 of the carrier 10 via the bond wires 14. This offers the possibility of realizing critical RF
  • FIG. 3 also shows that the connection of a terminal 5 to one contact area or contact pad formed in the structured backside metallization 7 can be realized by more than one interconnect 8.
  • FIG. 3 shows the connection of terminals 5 via three interconnects 8 to the corresponding portion of the backside metallization 7. This may be desired in view of an increased current capability.
  • FIG. 4 shows a perspective view of an arrangement in which the semiconductor chip 11 is mounted on the carrier 10 with the front side 2 of the substrate 1 facing the carrier 10.
  • This arrangement can be manufactured by flip-chip technology.
  • the electric connection between the terminals 5 on the front side 2 of the substrate 1 and the contact areas 15 of the carrier 10 can be formed by bumps 16 of electrically
  • the bumps 16 can be formed from a solder, for example. Flip-chip technology is known per se.
  • the backside metallization 7 on the rear side 3 facing away from the carrier 10 can be structured into conductor tracks and contact areas including, for instance, inductors, routing tracks 13, a ground plane, a heat spreader or the like. These components of the backside metallization 7 are connected by interconnects 8 through the substrate 1.
  • FIG. 5 shows an example of the arrangement, in which the rear side 3 of the semiconductor chip 11 faces the carrier 10.
  • the backside metallization 7 comprises contact areas which are electrically connected to the contact areas 15 of the carrier 10 by means of electrically conductive bumps 16.
  • the substrate 1 is arranged with the rear side 3 facing the carrier 10.
  • the contact areas are connected via electrically conductive bumps 16 on the rear side 3 of the semiconductor chip 11. It is an advantage of the arrangement shown in FIG. 5 that the area that may be occupied by the contact areas is larger on the rear side 3 than on the front side 2 of the semiconductor chip 11.
  • the contact pads on the rear side 3 may have typically twice the dimensions of the contact areas on the front side 2, and hence the area of the backside contact pads is typically four times as large. It is therefore favorable to use the larger contact areas in the structured backside metallization 7 for the bumps 16 instead of the small contact pads on the front side 2. This also saves chip area on the front side 2, which can be used for the integration of electronic devices and circuit components.
  • the interconnects 8 can directly connect the terminals 5 of the electronic device or circuit 4 integrated on the front side 2 with the corresponding contact areas of the backside metallization 7. Instead, the terminals 5 and the contact areas of the backside metallization 7 that are to be
  • FIG. 6 shows an arrangement according to the embodiment of FIG. 5 with the contact areas of the backside metallization 7 provided with the bumps 16 being shifted laterally with respect to the terminals 5.
  • conductor tracks 17 are provided in the structured backside metallization 7.
  • the arrangement of the terminals 5 on the front side 2 of the substrate 1 can thus be chosen essentially independently of the arrangement of the bumps 16 on the rear side 3. This also enables the use of bumps 16 that are smaller than the diameter of the interconnects 8.
  • the features of the different embodiments using bumps can also be combined and the backside metallization 7 may
  • the semiconductor chip offers new possibilities for the wiring of the semiconductor chip and for the mounting of the semiconductor chip on a carrier like a PCB .
  • the semiconductor chip
  • the invention enables to use backside connections as add-on or as a replacement for bond wires in order to save assembly costs and assembly time for bond wiring.
  • interconnect it is sufficient to have a first metallization layer on the front side, so that the upper metal layers of the wiring are available to design interconnects, inductors and the like above the interconnect through the substrate.
  • the interconnects forming the electric connection to the backside metallization do therefore not inhibit the
  • the structured backside metallization and the interconnects through the substrate can be manufactured in a standard process requiring only slight modifications.
  • the patterning of the backside metallization can be made using masks that are used for opening dicing streets in the conventional whole-area metallization.
  • the masks need only be modified to be appropriate for structuring the backside metallization into conductor tracks and other passive components according to the invention.
  • the invention permits the production of better, smaller and cheaper modules, particularly in GaAs- technology. It enables an elimination of bond wiring or conventional flip-chip technology and allows a combination of these conventional technologies with the production of additional electric connections.
  • the structured backside metallization of the semiconductor chip allows a versatile arrangement of the chip when mounted on a carrier.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electronic device or circuit (4) at the front side (2) of a substrate (1) of semiconductor material with terminals (5) and a wiring electrically connected with the terminals is connected with a structured backside metallization (7) on the rear side. An interconnect (8) through the substrate is electrically connected with the backside metallization, and the interconnect and the backside metallization form part of the wiring. The chip (11) can be arranged on a carrier (10) comprising contact areas (15), which can be connected with the backside metallization or the terminals directly or via bond wires.

Description

Description
SEMICONDUCTOR CHIP WITH BACKSIDE METALLIZATION AND ARRANGEMENT OF SAID CHIP ON A CARRIER
The invention relates to electric signal connections between a semiconductor chip and a carrier.
A semiconductor chip, especially a GaAs die, is conventional¬ ly mounted on a carrier by means of a glue layer or by
soldering. The electric connections are realized by bond wires or by bumps, solder balls or studs in conjunction with a flip-chip mounting.
The paper of J. Fender et al . , "Development of Backside
Process for Alternative Die Attach on HBT " , CS MANTECH
Conference, May 14-17, 2007, Austin, Texas, USA, pages 159 to 162, describes a backside die attach on a carrier. Solderable contacts are formed on the backside of the die, and the contacts are connected to contact pads on a carrier. Through- wafer vias are used to connect the devices on the front side of the die with the backside contacts.
The paper of A. Bessemoulin, "Design Data for Hot-via
Interconnects in Chip Scale Packaged MMICs up to 110 GHz", 12th GAAS Symposium, Amsterdam 2004, pages 495 to 498,
describes an arrangement of a broadband millimeter-wave PHEMT amplifier MMIC using through-wafer contacts to connect
opposite sides of the IC chip electrically. The backside contact pad is a coplanar waveguide section. It is an object of the invention to present a semiconductor chip suitable for mounting on a carrier. It is a further object to disclose a new arrangement of a semiconductor chip on a carrier.
These objects are achieved with the semiconductor chip with backside metallization according to claim 1 and the
arrangement of a semiconductor chip with backside
metallization according to claim 6 or claim 8. Further objects are achieved with embodiments according to the dependent claims.
The invention is based on a combination of interconnects through the semiconductor chip and a structured backside metallization. It offers new applications and possibilities for power amplifiers or switches, for example. The
semiconductor chip comprises an electronic device or circuit at the front side and a structured backside metallization on the opposite rear side. Terminals of the electronic device or circuit are electrically connected with a wiring including the backside metallization and at least one interconnect through the substrate, the interconnect being electrically connected with the backside metallization.
In a further embodiment of the semiconductor chip, it
possesses a further interconnect through the substrate, the interconnect and the further interconnect electrically connecting terminals of the electronic device or circuit via the backside metallization.
In further embodiments of the semiconductor chip, an inductor formed by a spiral or an RF transmission line formed by a conductor track is structured in the backside metallization. In a further embodiment, the semiconductor chip comprises a substrate of GaAs .
The semiconductor chip with backside metallization can be arranged on a carrier having contact areas . The chip can be arranged on the carrier with the front side of the chip facing the carrier, and at least one of the terminals of the electronic device or circuit of the chip can be electrically conductively connected to one of the contact areas of the carrier. Instead, the semiconductor chip can be arranged on the carrier with the rear side facing the carrier, at least one of the contact areas of the carrier being electrically conductively connected to the backside metallization of the semiconductor chip, and at least one of the contact areas of the carrier is electrically conductively connected to one of the terminals on the chip by means of a bond wire.
In a further embodiment of the arrangement, the semiconductor chip is arranged on the carrier with the front side facing the carrier and a bond wire connects the backside metalliza¬ tion with one of the contact areas of the carrier.
In a further embodiment, the semiconductor chip is arranged on the carrier with the rear side facing the carrier, a contact area of the carrier that is electrically conductively connected to the backside metallization is provided for the transmission of an RF signal, and a contact area that is electrically conductively connected by means of a bond wire is provided for a DC connection.
In a further embodiment of the arrangement, the interconnect of the semiconductor chip and a further interconnect of the semiconductor chip electrically connect terminals of the electronic device or circuit via the backside metallization.
In further embodiments of the arrangement, the chip comprises an inductor formed by a spiral or an RF transmission line formed by a conductor track in the backside metallization.
In a further embodiment of the arrangement, the chip
comprises a substrate of GaAs .
In a further embodiment of the arrangement, an electrically conductive bump is arranged on a contact area of the carrier and a conductor track of the wiring connects the bump with an interconnect .
In a further embodiment of the arrangement, an electrically conductive bump is arranged between an interconnect of the chip and a contact area of the carrier.
The interconnect can be formed by a through-wafer contact or backvia, which is available in a standard GaAs technology, for example. An interconnect through the substrate of the semiconductor chip provides a low-ohmic and low-inductance connection between a front side metallization and a backside metallization belonging to a wiring of the chip. A backside metallization has a typical thickness of about 4.5 μιη and can be gold, for example. The backside metallization usually forms an electric grounding and may also be used as a heat sink. To prolong the lifetime of the dicing saw, the backside metallization is not present in a dicing street provided for the separation of individual chips from the wafer. According to the present invention, the backside metallization is structured to form part of the wiring of the chip. Thus, there is not only a continuous layer of the metallization, which is only interrupted by the dicing street, but a pattern of conductor tracks or the like is formed in the backside metallization.
The following is a more detailed description of examples of the invention in conjunction with the appended figures.
FIG. 1 shows a perspective view of an arrangement of a
semiconductor chip on a carrier.
FIG. 2 shows the structure of the backside metallization of the chip of the embodiment according to FIG. 1.
FIG. 3 shows a perspective view of an arrangement of a
semiconductor chip on a carrier, which comprises additional bond wires.
FIG. 4 shows a perspective view of an arrangement of a
semiconductor chip having a backside metallization mounted in flip-chip technology on a carrier.
FIG. 5 shows a perspective view of an arrangement of a
semiconductor chip with the backside metallization facing the carrier and mounted by means of bumps.
FIG. 6 shows a perspective view of a further embodiment of an arrangement according to FIG. 5.
FIG. 1 shows a perspective view of an embodiment of an arrangement of a semiconductor chip having a structured backside metallization, which forms part of a wiring, on a carrier. The carrier 10 can be any substrate or PCB (printed circuit board) , which is used for standard surface mounted devices. The semiconductor chip 11 comprises a substrate 1 of semiconductor material having a front side 2 and a rear side 3. An electronic device or circuit 4, not shown in detail in FIG. 1, is arranged at the front side 2. The electronic de¬ vice or circuit 4 is provided with terminals 5, which can be formed by contact pads or the like. A wiring is electrically connected with the terminals and can comprise conventional metallization layers and intermetal dielectric, for example.
The wiring of the semiconductor chip according to the
invention further comprises an interconnect 8 through the substrate 1 and a structured backside metallization 7. The carrier 10 is provided with contact areas 15. Contact areas provided in the backside metallization 7 of the semiconductor chip 11 are arranged on the contact areas 15 of the carrier 10 and fastened to the contact areas 15 by means of an electrically conductive glue or a solder material. The corresponding portions of the backside metallization 7 can be provided for a grounding, a heat sink or other conventional passive components formed in a metal layer, and can comprise conductor tracks connecting the interconnects 8, 9 to one another or to the contact areas. The backside metallization 7 and the contact areas 15 can also be used for signals, especially DC signals or RF signals, for example.
The backside metallization 7 may comprise conducting spirals 12 used as inductors and/or conductor tracks 13 which can be used as re-routing or redirection on the rear side or as RF transmission lines, for example. The areas of the backside metallization 7 that are contacted with the contact areas 15 of the carrier 10 can be terminals of emitter, base and collector of a heterobipolar transistor, for example. Instead of a heterobipolar transistor, any circuit components of an electronic device or circuit 4 integrated in the substrate 1 can be connected via the structured backside metallization 7. By means of a structured backside metallization 7, it is especially possible in RF devices to separate backside connections for different RF stages in order to eliminate ground coupling. Grounding and ground coupling are important with respect to the performance and stability of RF devices, in order to avoid oscillations.
FIG. 2 shows an example of the structured backside metalliza¬ tion 7 forming part of a wiring 6, which encompasses the backside metallization 7, interconnects 8, terminals 5 of the electronic device or circuit 4, and possibly further metal¬ lizations and interconnects of a conventional wiring formed by metal layers and vias that are arranged in an intermetal dielectric. FIG. 2 also shows spirals 12 of conductor tracks used as inductors. Contact pads of the backside metallization 7 are in contact with the interconnects 8, which are indi¬ cated with broken lines as hidden contours. The conductor track 13 can be provided to serve as a connection between the interconnect 8 and the further interconnect 9 and thus to provide a re-routing or redistribution on the backside of the semiconductor chip 11. The larger areas of the backside metallization 7 shown on the left side of FIG. 2 can be contact areas that are provided to connect terminals of the integrated electronic device or circuit 4 with corresponding contact areas 15 of the carrier 10. The three contact areas shown in FIG. 2 can be terminals of an emitter, a base and a collector of a heterobipolar transistor, for example. The relatively thick backside metallization 7 is especially favorable to realize inductors in the form of spirals 12 such as shown in FIG. 2. The thick metal layer of the backside metallization 7 gives a high quality factor of the inductor. Furthermore, using planar spirals 12 as inductors and
connecting their terminals by means of the interconnects 8 through the substrate 1 avoids an application of conductor bridges and thus prevents the occurrence of parasitic
capacitances and resistances.
Connections between the contact areas 15 of the carrier 10 and terminals 5 of the electronic device or circuit 4
integrated in the semiconductor chip 11 can be made by a direct connection of the contact areas of the backside metallization 7 on the contact areas 15 of the carrier 10 and, additionally, by means of bond wires connecting contact areas on the front side 2 of the semiconductor chip 11 to further contact areas 15 of the carrier 10. FIG. 3 shows a perspective view of an arrangement of a semiconductor chip 11 having a structured backside metallization 7, in which the rear side 3 of the semiconductor chip 11 faces the carrier 10 and the front side 2 of the semiconductor chip 11 carries terminals 5 which are electrically connected to contact areas 15 of the carrier 10 by means of bond wires 14. The terminals 5 on the front side 2 can thus be connected to the backside metallization 7 via the interconnects 8 or can be connected to contact areas 15 of the carrier 10 via the bond wires 14. This offers the possibility of realizing critical RF
connections via the backside metallization 7 directly to the corresponding contact areas 15 and less critical DC
connections via bond wires 14. RF structures like inductors or transmission lines can thus be restricted to the
structured backside metallization 7 while DC input/output interconnects can be formed on the front side 2 by means of the bond wires 14. FIG. 3 also shows that the connection of a terminal 5 to one contact area or contact pad formed in the structured backside metallization 7 can be realized by more than one interconnect 8. FIG. 3 shows the connection of terminals 5 via three interconnects 8 to the corresponding portion of the backside metallization 7. This may be desired in view of an increased current capability. Features of the embodiment according to FIG. 1 and FIG. 3 can be combined to have inductors or re-routing tracks and bond wires or
multiple interconnects in the same arrangement.
FIG. 4 shows a perspective view of an arrangement in which the semiconductor chip 11 is mounted on the carrier 10 with the front side 2 of the substrate 1 facing the carrier 10. This arrangement can be manufactured by flip-chip technology. The electric connection between the terminals 5 on the front side 2 of the substrate 1 and the contact areas 15 of the carrier 10 can be formed by bumps 16 of electrically
conductive material. The bumps 16 can be formed from a solder, for example. Flip-chip technology is known per se. The backside metallization 7 on the rear side 3 facing away from the carrier 10 can be structured into conductor tracks and contact areas including, for instance, inductors, routing tracks 13, a ground plane, a heat spreader or the like. These components of the backside metallization 7 are connected by interconnects 8 through the substrate 1.
FIG. 5 shows an example of the arrangement, in which the rear side 3 of the semiconductor chip 11 faces the carrier 10. The backside metallization 7 comprises contact areas which are electrically connected to the contact areas 15 of the carrier 10 by means of electrically conductive bumps 16. This
arrangement can be manufactured using a technology similar to flip-chip technology. Contrary to conventional flip-chip technology, the substrate 1 is arranged with the rear side 3 facing the carrier 10. The contact areas are connected via electrically conductive bumps 16 on the rear side 3 of the semiconductor chip 11. It is an advantage of the arrangement shown in FIG. 5 that the area that may be occupied by the contact areas is larger on the rear side 3 than on the front side 2 of the semiconductor chip 11. The contact pads on the rear side 3 may have typically twice the dimensions of the contact areas on the front side 2, and hence the area of the backside contact pads is typically four times as large. It is therefore favorable to use the larger contact areas in the structured backside metallization 7 for the bumps 16 instead of the small contact pads on the front side 2. This also saves chip area on the front side 2, which can be used for the integration of electronic devices and circuit components.
The interconnects 8 can directly connect the terminals 5 of the electronic device or circuit 4 integrated on the front side 2 with the corresponding contact areas of the backside metallization 7. Instead, the terminals 5 and the contact areas of the backside metallization 7 that are to be
connected with the contact areas 15 of the carrier 10 can be laterally shifted with respect to one another.
FIG. 6 shows an arrangement according to the embodiment of FIG. 5 with the contact areas of the backside metallization 7 provided with the bumps 16 being shifted laterally with respect to the terminals 5. In order to provide the necessary electric connection between the interconnects 8 and the bumps 16, conductor tracks 17 are provided in the structured backside metallization 7. The arrangement of the terminals 5 on the front side 2 of the substrate 1 can thus be chosen essentially independently of the arrangement of the bumps 16 on the rear side 3. This also enables the use of bumps 16 that are smaller than the diameter of the interconnects 8. The features of the different embodiments using bumps can also be combined and the backside metallization 7 may
particularly comprise the structure components of the
previously described embodiments like inductors or re-routing tracks, for example.
The use of a structured backside metallization and
interconnects through the substrate connecting terminals of the integrated devices with the structured backside
metallization offers new possibilities for the wiring of the semiconductor chip and for the mounting of the semiconductor chip on a carrier like a PCB . The semiconductor chip
according to the invention and the arrangement on the carrier have several advantages in comparison with conventional devices and mountings.
The invention enables to use backside connections as add-on or as a replacement for bond wires in order to save assembly costs and assembly time for bond wiring. Mounting and
connecting the semiconductor chip to the contact areas of the carrier by means of bumps or an electrically conductive interlayer is supposed to be less susceptible to spread than bond wiring or conventional flip-chip technology. This results in less variation in performance and a reduction of parasitic inductances. The elimination of bond wires can also save space and hence reduce substrate size and cost. It thus enables further miniaturization. An arrangement of the semiconductor chip with its rear side facing the carrier is advantageous in view of an easier laser tuning during
evaluation. This is a big advantage during product
development and for laser trimming in production. For the interconnect, it is sufficient to have a first metallization layer on the front side, so that the upper metal layers of the wiring are available to design interconnects, inductors and the like above the interconnect through the substrate. The interconnects forming the electric connection to the backside metallization do therefore not inhibit the
arrangement of metal patterns in the front side wiring. The structured backside metallization and the interconnects through the substrate can be manufactured in a standard process requiring only slight modifications. The patterning of the backside metallization can be made using masks that are used for opening dicing streets in the conventional whole-area metallization. The masks need only be modified to be appropriate for structuring the backside metallization into conductor tracks and other passive components according to the invention. The invention permits the production of better, smaller and cheaper modules, particularly in GaAs- technology. It enables an elimination of bond wiring or conventional flip-chip technology and allows a combination of these conventional technologies with the production of additional electric connections. The structured backside metallization of the semiconductor chip allows a versatile arrangement of the chip when mounted on a carrier.
List of reference numerals
1 substrate
2 front side
3 rear side
4 electronic device or circuit
5 terminal
6 wiring
7 backside metallization
8 interconnect
9 further interconnect
10 carrier
11 chip
12 spiral
13 conductor track
14 bond wire
15 contact area
16 bump
17 conductor track

Claims

Claims
1. Semiconductor chip with backside metallization,
comprising :
- a substrate (1) of semiconductor material having a front side (2) and a rear side (3) opposite to the front side,
- an electronic device or circuit (4) at the front side,
- terminals (5) of the electronic device or circuit,
- a wiring (6) electrically connected with the terminals,
- a structured backside metallization (7) on the rear side,
- an interconnect (8) through the substrate, the inter¬ connect being electrically connected with the backside metallization, and
- the interconnect and the backside metallization forming part of the wiring.
2. The semiconductor chip according to claim 1, further
comprising :
a further interconnect (9) through the substrate (1), the interconnect (8) and the further interconnect (9) electrically connecting terminals (5) of the electronic device or circuit (4) via the backside metallization (7) .
3. The semiconductor chip according to claim 1 or 2, further comprising :
an inductor formed by a spiral (12) in the backside metallization (7) .
4. The semiconductor chip according to one of claims 1 to 3, further comprising:
an RF transmission line formed by a conductor track (13) in the backside metallization (7) .
5. The semiconductor chip according to one of claims 1 to 4, wherein the substrate (1) is GaAs .
6. Arrangement of a semiconductor chip with backside
metallization, comprising:
- a carrier (10) having contact areas (15),
- a chip (11) having a substrate (1) of semiconductor
material with a front side (2) and a rear side (3) opposite to the front side,
- an electronic device or circuit (4) at the front side,
- terminals (5) of the electronic device or circuit,
- a wiring (6) electrically connected with the terminals,
- a structured backside metallization (7) on the rear side,
- an interconnect (8) through the substrate, the inter¬ connect being electrically connected with the backside metallization,
- the interconnect and the backside metallization forming part of the wiring,
- the chip being arranged on the carrier with the front
side facing the carrier, and
- at least one of the terminals being electrically
conductively connected to one of the contact areas.
7. The arrangement according to claim 6, further comprising: a bond wire (14) connecting the backside metallization (7) with one of the contact areas (15) .
8. Arrangement of a semiconductor chip with backside
metallization, comprising
- a carrier (10) having contact areas (15), - a chip (11) having a substrate (1) of semiconductor material with a front side (2) and a rear side (3) opposite to the front side,
- an electronic device or circuit (4) at the front side,
- terminals (5) of the electronic device or circuit,
- a wiring (6) electrically connected with the terminals,
- a structured backside metallization (7) on the rear side,
- an interconnect (8) through the substrate, the inter¬ connect being electrically connected with the backside metallization,
- the interconnect and the backside metallization forming part of the wiring,
- the chip being arranged on the carrier with the rear side facing the carrier,
- at least one of the contact areas being electrically
conductively connected to the backside metallization, and
- at least one of the contact areas being electrically
conductively connected to one of the terminals by means of a bond wire (14) .
9. The arrangement according to claim 8, wherein
a contact area (15) that is electrically conductively connected to the backside metallization (7) is provided for a transmission of an RF signal, and
a contact area (15) that is electrically conductively connected by means of a bond wire (14) is provided for a DC connection.
10. The arrangement according to one of claims 6 to 9,
further comprising:
a further interconnect (9) through the substrate (1), the interconnect (8) and the further interconnect electrically connecting terminals (5) of the electronic device or circuit (4) via the backside metallization (7) .
11. The arrangement according to one of claims 6 to 10,
further comprising:
an inductor formed by a spiral (12) in the backside metallization (7) .
12. The arrangement according to one of claims 6 to 11,
further comprising:
an RF transmission line formed by a conductor track (13) in the backside metallization (7) .
13. The arrangement according to one of claims 6 to 12,
wherein the substrate (1) is GaAs .
14. The arrangement according to one of claims 6 to 13,
further comprising:
- an electrically conductive bump (16) on a contact area (15) of the carrier (10), and
- a conductor track (17) of the wiring (6), the conductor track connecting the bump with an interconnect (8) .
15. The arrangement according to one of claims 6 to 14,
further comprising:
an electrically conductive bump (16) arranged between an interconnect (8) and a contact area (15) of the carrier (10) .
PCT/EP2009/066367 2009-12-03 2009-12-03 Semiconductor chip with backside metallization and arrangement of said chip on a carrier WO2011066863A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2009/066367 WO2011066863A1 (en) 2009-12-03 2009-12-03 Semiconductor chip with backside metallization and arrangement of said chip on a carrier

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014099675A1 (en) * 2012-12-20 2014-06-26 Applied Materials, Inc. Wafer dicing from wafer backside

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5635762A (en) * 1993-05-18 1997-06-03 U.S. Philips Corporation Flip chip semiconductor device with dual purpose metallized ground conductor
US20020030267A1 (en) * 2000-09-08 2002-03-14 Fujitsu Quantum Devices Limited Compound semiconductor device
US20080296735A1 (en) * 2007-06-01 2008-12-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5635762A (en) * 1993-05-18 1997-06-03 U.S. Philips Corporation Flip chip semiconductor device with dual purpose metallized ground conductor
US20020030267A1 (en) * 2000-09-08 2002-03-14 Fujitsu Quantum Devices Limited Compound semiconductor device
US20080296735A1 (en) * 2007-06-01 2008-12-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014099675A1 (en) * 2012-12-20 2014-06-26 Applied Materials, Inc. Wafer dicing from wafer backside
US8975162B2 (en) 2012-12-20 2015-03-10 Applied Materials, Inc. Wafer dicing from wafer backside

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