WO2011046530A1

WO2011046530A1 - Selectable latency maximum a posteriori (map) decoder

Info

Publication number: WO2011046530A1
Application number: PCT/US2009/005578
Authority: WO
Inventors: Ivonete Markman
Original assignee: Thomson Licensing
Priority date: 2009-10-13
Filing date: 2009-10-13
Publication date: 2011-04-21

Abstract

A variable latency maximum a posteriori (MAP) decoder inputs an encoded stream of M interleaved trellis encodings. The MAP decoder includes a metric generator unit, an alpha unit, a beta unit, and a log likelihood ratio unit that computes output values corresponding to the digital data using the accumulated alpha state metrics and accumulated beta state metrics. The processing block size per decoder, expressed in symbols, L_pb, is selectable to provide either a low latency processing time or a high latency processing time in computing the output values. The decoder operates under the conditions that N*S is a multiple of D*M*L_pb where M, N, and D are integer numbers greater than or equal to 1 and the input data stream is organized in digital symbols of size S.

Description

SELECTABLE LATENCY MAXIMUM A POSTERIORI (MAP) DECODER

FIELD

[0001] The present invention relates to digital signal decoding and more specifically to an architecture for a selectable latency maximum a posteriori (MAP) decoder for a digital television (DTV) trellis coded television signal.

BACKGROUND

[0002] The Advanced Television Systems Committee (ATSC) standard for Digital

Television (DTV) in the United States requires an 8-Vestigial SideBand (VSB) transmission system which includes Forward Error Correction (FEC) as a means of improving the ί,/stem performance. The FEC system consists of a Reed-Solomon encoder, followed by a byte interleaver, and a trellis encoder on the transmitter side. At the receiver end, there is a corresponding trellis decoder, byte deinterleaver and Reed-Solomon decoder. The ATSC- DTV standard is document A53.doc, dated September 16, 1995 produced by the United States Advanced Television Systems Committee. Figure 1 shows a simplified block diagram of the DTV transmitter and receiver, emphasizing the FEC system.

[0003] The ATSC DTV transmission scheme is not robust enough against Doppler shift and multipath radio interference, and is designed for highly directional fixed antennas, hindering the provision of expanded services to customers utilizing mobile and handheld devices. To overcome these issues, and create a more robust and more flexible system, among other things, it is possible to add a new layer of FEC coding, and more powerful decoding algorithms to decrease the Threshold of Visibility (TOV).

[0004] The added layer of FEC coding can require decoding techniques such as turbo decoding discussed in an article by C. Berrou, A. Glavieux and P. Thitimajshima, entitled "Near Shannon Limit Error - Correcting Coding and Decoding: Turbo-Codes", found in Proceedings of the ΓΕΕΕ International Conference on Communications - ICC 93, May 23- 26, 1993, Geneva, Switzerland, pp. 1064-1070. Another turbo code discussion can be found in the article by M. R. Soleymani, Y. Gao and U. Vilaipomsawai, entitled "Turbo Coding for Satellite and Wireless Communications", Kluwer Academic Publishers, USA, 2002.

[0005] Hence, decoding of signals encoded for ATSC-DTV with an added FEC layer can involve trellis decoding algorithms like maximum a posteriori (MAP) decoders as described by L.R. Bahl, J. Cocke, F. Jelinek and J. Raviv, in an article entitled "Optimal Decoding of Liner Codes for Minimizing Symbol Error Rate", found in ΓΕΕΕ Transactions on

Information Theory, Vol. IT-20, No. 2, March 1974, pp. 284-287. Another discussion of trellis codes and a MAP decoder is found in an article written by A.J. Viterbi, entitled "An Intuitive Justification and a Simplified Implementation of the MAP Decoder for

Convolutional Codes", found in IEEE Journal on Selected Areas in Communications, Vol. 16, No. 2, February 1998, pp. 260-264.

[0006] The trellis code employed in the ATSC-DTV standard is a rate 2/3 trellis coded modulation (TCM) code. This code is implemented by coding one bit using a rate ½, 4-state convolutional encoder, and adding an FEC uncoded bit which is differentially precoded. Each set of three coded bits out of the encoder is mapped to an 8-VSB modulator symbol.

[0007] Figure 2 shows a block diagram of the differential precoder, trellis encoder and corresponding 8-VSB symbol mapper. Furthermore, a twelve intrasegment interleaving is employed whereby 12 identical encoders and precoders are sequentially used, processing each a byte at a time, and transmitting each a symbol at a time. In addition, a skip of four encoders/precoders is performed every segment sync.

[0008] Figures 3 and 4 show the 12-encoder interleaving and corresponding 12-decoder deinterleaving, respectively. The reason for the 12-encoder interleaving came from the need to eliminate possible National Television Standard Committee (NTSC) co-channel interference, which coexisted with HDTV for a number of years.

[0009] In the instance of the ATSC trellis code depicted in Figures 2 and 3, the MAP decoder can be used to obtain the soft output of the decision bit-pair (two bits per trellis branch), which is the a posteriori probability (APP) of the decision bit-pair, or equivalently, of the TCM code output symbols. Since the ATSC-DTV trellis code is a composite of 12 interleaved trellis codes, as shown in Figure 3, a straightforward MAP decoder design would replicate the MAP decoder twelve times, as shown in Figure 4. In addition the trellis deinterleaving operation must take into account the skipping of 4 decoders every segment sync, according to the ATSC-DTV standard.

[0010] Latency in MAP decoders is directly related to the processing block size and affects the reliability of the output. Normally, a latency determination is fixed upon the fixed design and construction of the MAP decoder. However, it is envisioned that a more flexible approach, a selectable latency MAP decoder would be desirable in order to provide either quicker estimated output with a low latency or higher reliability with a high latency. The present invention addresses the need for a dual latency mode MAP decoder. SUMMARY

[0011] The ATSC-DTV standard employs a trellis code with twelve intrasegment interleaving whereby twelve identical encoders and corresponding decoders are sequentially used. According to one aspect of the invention, a maximum a posteriori (MAP) decoder is realized that has a variable latency selection. The variable latency (MAP) decoder inputs an encoded stream of M interleaved trellis encodings. The variable latency MAP decoder can be used to select operation to be either a low latency decoder or a high latency decoder for a particular trellis encoding data stream. The selection is dependent on input or selection of a processing block size value, L_pb, expressed in symbols. The decoder operates under the conditions that N*S is a multiple of D*M*Lp_b where M, N, and D are integer numbers greater than or equal to 1 and S is the number of symbols in an ATSC data segment or data field.

[0012] In one embodiment, selecting a processing block size can affect the initialization and synchronization of various functional metric computing blocks within the MAP decoder such that variable latencies can be achieved from a single MAP decoder design.

[0013] Additional features and advantages of the invention are apparent from the following detailed description of illustrative embodiments which proceeds with reference to the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 depicts an example block diagram of a digital television transmitter and receiver system;

Figure 2 depicts an example trellis encoder, differential precoder, and symbol mapper for a transmitter in a digital television system;

Figure 3 depicts an example twelve stage trellis encoder and interleaver for a digital television transmitter;

Figure 4 depicts an example twelve stage trellis decoder and deinterleaver for a digital television receiver;

Figure 5 depicts an example digital television data frame;

Figure 6 depicts an example digital television field synchronization structure;

Figure 7 depicts an example architecture for a MAP decoder in a digital television receiver according to aspects of the invention; Figure 8 is a table depicting the data processing blocks in time as processed by MAP decoder units according to aspects of the invention;

Figure 9 depicts the data block relationship between processing units in an example MAP decoder according to aspects of the invention;

Figure 10 depicts data processing block in processing units of a MAP decoder according to aspects of the invention;

Figure 11 depicts an example MAP decoder architecture having control aspects according to the invention; and

Figure 12 depicts a timing relationship between the inputs and metric calculator block outputs according to aspects of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] As discussed above, Figure 1 shows one prior art architecture for a DTV system which incorporates forward error correction. Here, input digital data, which may be considered any of video, audio, textual, or other information data, is encoded using a DTV standard and transmitted to a receiver which decodes the digital data. Of particular interest is the decoding system which includes a trellis decoding function in the receiver chain. Figure 2 depicts the precoder, trellis encoding, and symbol mapper of a DTV transmitter. Figure 3 depicts an existing system used on the transmission side showing the 12 interleaved stages of the Figure 2 precoder and trellis encoder function followed by a mapper which accepts the trellis encoded output symbols. A straightforward decoder for such a system is depicted in Figure 4 which shows the need for 12 deinterleaved trellis decoders in order to decode the transmission stream produced by the encoder of Figure 3.

[0016] Considering the ATSC-DTV standard, Figure 5 shows how the DTV data are organized for transmission. Each data frame consists of two data fields, each containing 313 data segments. The first data segment of each data field is a unique synchronizing signal (data field sync) as shown in Figure 6, including several pseudo random (PN) sequences. The remaining 312 data segments each carry the equivalent of the data from one 188-byte transport packet plus its associated FEC overhead. Each data segment consists of 832 8-VSB symbols. The first 4 symbols are transmitted in binary form and provide segment synchronization, as also shown in Figure 6 (values of: +5, -5, -5, +5). This data segment sync signal also represents the sync byte of the 188-byte MPEG-compatible transport packet. The remaining 828 symbols of each data segment carry data equivalent to the remaining 187 bytes of a transport packet and its associated FEC overhead. [0017] The maximum a posteriori (MAP) decoding algorithm for convolutional codes was proposed over three decades ago by Bahl et al., but only got increased attention over a decade ago as an iterative soft-output decoder for the class of turbo codes discovered by Berrou et al. Although more complex than the maximum likelihood decoder algorithm proposed by Viterbi, the MAP decoder proposed by Bahl et al. minimizes the probability of symbol error, therefore accomplishing acceptable performance within Signal-to-Noise (SNR) levels of ldB of the Shannon capacity values in iterative decoding systems. In particular, sub-optimum versions of the MAP algorithm, like the max-log-MAP algorithm with a correction factor for the max operation (also called log-MAP algorithm), represent a drastic reduction in computational complexity for a small degradation in the order of tenths of a dB, hence being favored for practical implementations. This is discussed in an article by M. R. Soleymani, Y. Gao and U. Vilaipomsawai, entitled "Turbo Coding for Satellite and Wireless Communications", luwer Academic Publishers, USA, 2002. Sub-optimal decoding is presented by Robertson, E. Villebrun and P. Hoeher, in an article entitled "A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain", found in the Proceedings of the IEEE International Conference on Communications - ICC '95, Seattle, WA, 1995, pp. 1009-1013.

[0018] The most basic implementation of the MAP decoder sees the algorithm as a dual- maxima computation combined with forward (alpha) and backward (beta) recursions of the Viterbi algorithm computations. Figure 7 shows a simplified block diagram of the MAP decoder. In the case of the ATSC trellis code, the MAP decoder can be used to obtain the soft output of the decision bit-pair (two bits per trellis branch), which is the a posteriori probability (APP) of the decision bit-pair, or equivalently, of the TCM code output symbols. Thus, the functional blocks of Figure 7 are normally duplicated 12 times in order to achieve the DTV trellis decoder depicted in Figure 4.

[0019] Referring to Figure 7, the metric generator unit consists of the channel metric (rri_c) computation for each 8-VSB input symbol (r), which may be given by: m _c (k, i) = - C ; ) /(2σ² ) (1) where k > 1 is the symbol period; σ² is the noise variance and , for i = 0, 1 ... 7, are the 8 possible TCM symbols. The channel metrics (i¾) are then stored for a size of two processing blocks. This processing block, Lp_b, is equivalent to the traceback latency of a Viterbi decoder, in symbols. [0020] The metric generator unit also stores the apriori metric (m_apr) received from a previous iteration for a size of two processing blocks. The apriori metrics m_apr(k, j) is given by: m _apr (k, j) = -log (p ^_k = jjj (2)

where k > 1 is the symbol period; log(.) is the logarithm function; P(.) is the probability; I_k is the bit-pair at time k and j= 0, 1, 2, 3, represents the four bit-pair values.

[0021] The metric generator must then send the mc and m_apr stored values to the

corresponding alpha (forward processing) and beta (backward processing) units. The alpha values (airi_c and am_apr) are sent in a first in first out (FIFO) mode, while the beta (bnic and bniapr) values are sent in a last in first out (LIFO) mode.

[0022] Figure 8 presents a table depicting the ordering of received data processing blocks (L_pb) numbered in time (p_w), and the respective alpha and beta metrics and accumulated metrics, as well as the LLR calculations. The arrows indicate the latency of processing the first data processing block within the decoder. Observe that the alpha and beta metrics calculated inside the metric generator unit have a latency of 2xL_pb symbols with respect to the MAP decoder input.

[0023] The alpha unit is a modified forward Viterbi decoder which computes the forward state metrics as follows:

[0024]

A{k) = mm* (Aik - ^ + am^S^→ S_k ) + am_apr {k, S_k__x→S_k )) (3) where k > 1 is the symbol period; min*(.) is the min_star_sum operation, which is performed for all states S_k__l that transit to a given state S_k ; A(k-l) is the alpha accumulated metric at time period k-1, which initial value A(0) = 0; am_c(k, S_k__l→S_k ) is the alpha channel metric associated with the particular state transition in the TCM trellis, chosen to be a particular am_c(k,i) value, when i is the 8-VSB symbol index associated with the trellis state transition (5_W→5₍ ) and am_apr(k, S_k_₁→S_k ) is the alpha apriori metric associated with the particular state transition in the TCM trellis, chosen to be a particular am_c(k,j) value, where j is the dual-bit index associated with the trellis state transition ( 5_t_,→ S_k ).

[0025] A min_star_sum operation is defined as follows:

mm (x₁ ,x₂ ,..., x_N ) = -log(e^'Xl + e^'X2 + ... + e^'x" ) (4) For N=2, we have the following simple formula:

mm (x_l,x₂) = -\og(e^~x> + e^"Jt2 ) = min( ₁, ₂) - log(l + e^{"|jt| ~JC21}) (5) Note that this function can be reduced to finding the minimum of two numbers and adding a (log) correction factor, which can be implemented using a very small look-up table. In addition, equation 5 may be recursively calculated to compute equation 4.

[0026] In Figure 8, observe that the alpha metrics (arri_c and am_apr) are sent to the alpha unit with a latency of 2xL_pb symbols and are always processed in forward order. The accumulated alpha metrics, A(k), are then stored while being processed and will be sent to the LLR unit in reverse (LIFO) order of storage, during the following data processing block period, p_w. Therefore, during each p_w, a new data processing block is being processed, while the previously processed accumulated metrics are being sent to the LLR unit. For example, the arrows show that when p_w = 2, the data processing block 0 is being processed by the alpha unit and the accumulated metrics A(k) will be sent to the LLR unit during p_w= 3, while the data processing block 1 is being processed.

[0027] The beta unit is composed of two modified backward Viterbi decoders which compute the backward state metrics as follows:

B_w{k) = min* (B_w(k + l) + bm_c {k + 1, S_M→S_k ) + bm_apr {k + 1, S_k+l→ S_k )) (6) where w = 0 or 1, representing the two beta sub-units; k > 1 is the symbol period; min*(.) is the min_star_sum operation, which is performed for all states S_t+1 that transit to a given state

S_k ; B_w(k+1) is the beta sub-unit w accumulated metric at time period k+1, with initial value

Bw(P_wXL_pb) = 0, L_pb is the data processing block size and p_w > 0 is the set of even numbers when w = 0 and odd integers when w = 1; bm_c(k+l, S_k+l→S_k ) is the beta channel metric associated with the particular state transition in the TCM trellis, chosen to be a particular bm_c(k+l,i) value, when i is the 8-VSB symbol index associated with the trellis state transition ( S_k+l ^→S_k ) and bm_apr(k+l, S_k+i→ S_k ) is the beta apriori metric associated with the particular state transition in the TCM trellis, chosen to be a particular bm_c(k+l,j) value, where j is the dual-bit index associated with the trellis state transition ( S_k+l→ S_k ).

[0028] In Figure 8, observe that the beta sub-units compute their accumulated metrics backwards in time for a period of 2xL_p symbols each, and they are staggered in time by L_pb symbols. The beta 0 sub-unit resets its accumulated metric to 0 at the beginning of the even p_w values, while processing the odd numbered data processing blocks. The beta 1 sub-unit resets its accumulated metric to 0 at the beginning of the odd numbered p_w values, while processing the even numbered data processing blocks. For each p_w, the accumulated beta metrics of one of the beta units will be sent to the LLR unit as soon as they are processed: B₀(k) for odd numbered p_w values and Bi(k) for even numbered p_w values. For example, the arrows show that when p_w = 2, the data processing block 0 is being processed by the beta unit 0 and the accumulated metrics B₀(k) are being concurrently sent to the LLR unit, while the beta unit 1 is processing the data processing block 2.

[0029] The LLR (log likelihood ratio) unit computes the extrinsic information for the input bit-pairs I_k as follows:

LLR{k, j) = min* (A{k - l)+ B{k)+ bm_c {k, S_k→S_{k l} )) (7)

Sk→S_k-i

where k > 1 is the symbol period; min*(.) is the min_star_sum operation, which is performed for all states S_k that transit to a given state 5 and for each particular value of I_k = j and j = 0, 1, 2,3; A(k-l) is the alpha accumulated metric at time period k-1; B(k) is the beta accumulated metric at time period k and bni_c(k, S_k→ 5_t_, ) is the beta channel metric associated with the particular state transition in the TCM trellis, chosen to be a particular bm_c(k,i) value, when i is the 8-VSB symbol index associated with the trellis state transition

( S_k→¾-_ )^■

[0030] In Figure 8, observe that the LLR unit computes and stores its values backwards in time for each data processing block consisting of L_pb symbols. On the following data block period, the LLR values are retrieved in reverse order of storage (LIFO), being therefore delivered in the correct order at the MAP decoder output. For example, the arrows show that when p_w = 3, the data processing block 0 is being processed by the LLR unit and the accumulated metrics LLR(k, j) are being stored; when p_w = 4 the LLR accumulated metrics of the data processing block 0 are then retrieved from memory in the correct order and made available at the output, while the LLR unit is processing the data processing block 1. This represents an overall latency of 4 data processing blocks, or 4xL_p symbols with respect to the MAP decoder input.

[0031] The MAP controller unit directs the calculations of the metric generator, alpha, beta and LLR units, by sending all the necessary control signals: reset, logic enables, memory read/write enables and memory read/write address values. Since the TCM code is not a block code, in order to continuously generate the decoded symbol, a sliding window approach is used. Figure 9 shows a simplified diagram of the sliding window approach. The alpha unit processes the data processing block (L_pb) symbols in the forward direction; each beta sub- unit processes 2xL_pb symbols in the backward direction and the LLR unit computes soft information for L_pb bit-pairs in the backward direction. The beta units process twice the number of symbols to avoid large data processing blocks and allow the beta metrics to converge before the actual LLR calculations start. After the LLR calculations are completed, the window advances by L_pb symbols, or a data processing block. For alternate windows, alternate beta sub-units are utilized.

[0032] Figure 10 shows the diagram of Figure 9 in time, as the data processing blocks are processed. In Figure 10, p_w represents time, associated with the data processing block index at the MAP decoder input, and k represents the index of the input symbols being processed by the various units. For example, when 4 <p_w < 5, the alpha unit (Al) is processing symbols of index 2xL_pb-l≤ k < 3xL_pb-l in the forward direction; the beta unit 0 (B0) is processing symbols of index 4 L_pb-l≥ k > 3xLpb-l in the backward direction; the beta unit 1 (B l) and LLR unit are processing symbols of index 2xL_pb-l≥ k > Lpb-1 the backward direction; the LLR unit (LLR) is outputting soft bit-pairs associated with the first data block, that is, symbols of index 0 < k < L_pb-1 in the forward direction. Hence, we can observe once again that the latency of the MAP decoder is 4 data processing blocks.

[0033] As discussed above, the MAP decoder architecture of Figure 7 must be duplicated 12 times in order to achieve a straightforward design of the trellis decoder and deinterleaver of Figure 4. Alternately, the MAP decoder for the ATSC-DTV trellis code may be implemented as expressed in copending US Patent Application No. XX/XXX,XXX which is incorporated by reference in its entirety. In that application, a MAP decoder architecture for an ATSC- DTV Trellis Code is presented wherein the decoder design merges the 12 decoders into a single decoder to save silicon area. However, the present invention may use either a straightforward multiple leg decoder, such as where M=12 decoders, such as in Figure 4, or a consolidated decoder such as in the above-referenced copending application.

[0034] Figure 11 depicts an example decoding system according to aspects of the invention. The decoder of Figure 11 is typically implemented as a combination of hardware and software. In Figure 11, only one decoder is used shown, instead of, for example, the 12 decoders in parallel of Figure 4 for ATSC-DTV signal decoding. As mentioned above, either the full 12 parallel decoder stages or a single decoder leg design may be used in the current invention. The single, consolidated design is shown in Figure 11 for clarity. Figure 11 depicts the addition of a sync processor block which inputs the segment and field synchronization signals shown in Figure 5 and outputs derived synchronization signals for use by the MAP controller for distribution to the various components of the MAP decoder. For example, the segment and field synchronization signals are input to the sync processor via the sync lines of the sync processor of Figure 11. Derived sync signals are then provided by the sync processor to the to the MAP controller which can further derive synchronization signals and distribute any of the original or derived sync signals to the alpha unit, the beta unit, and the LLR unit. In one aspect of the invention, synchronization signals that are provided to the various MAP decoder components from the MAP decoder are in response to the latency input of the MAP decoder.

[0035] In the case of the ATSC trellis code depicted in Figures 2 and 3, the MAP decoder of Figure 11 can be used to obtain the soft output of the decision bit-pair (two bits per trellis branch), which is the a posteriori probability (app) of the decision bit-pair, or equivalently, of the TCM code output symbols. In addition the trellis deinterleaving operation must take into account the skipping of 4 decoders every segment sync, according to the ATSC-DTV standard.

[0036] In such a system, the receiver may require two different latency modes of turbo decoding between the ATSC-DTV trellis code and another code in the added FEC layer, these two modes constituting two separate forward error correction (FEC) paths in the receiver. The first mode uses a low latency MAP decoder to provide reliable enough decoding that may be ultimately fed to the equalizer, either for error generation purposes or as symbol inputs to its feedback filter, in order to help with its convergence. The second mode uses a high latency MAP decoder to provide decoded data with a higher degree of reliability needed to ultimately feed the transport and video decoding sub-systems in channel environments with strong multipath and very low SNR.

[0037] It is desirable to simplify the design of the MAP decoder to fit the different needs of the receiver, such that it can easily adapt to one of the two desired modes: high or low latency. In another aspect of the present invention, by encapsulating the parameter L_pb (length of data processing block) into the frame structure of the ATSC-DTV standard, the initialization and synchronization of the MAP decoders and remaining receiver units become concurrent, simplifying the controller design, particularly the features of reset and debugging. That way, a loss of synchronization followed by resyncrhonization in the receiver sync detector results in automatic resynchronization of the MAP decoder without any additional hardware. As mentioned above, Figure 11 shows a block diagram of the MAP decoder where a new block, sync processor, is introduced. This sync processor block generates the necessary syncs to initialize the remaining blocks of the decoder, as a function

1 of the original synchronization signals, that is, the segment and field sync in the ATSC standard.

[0038] In another aspect of the present invention, by encapsulating the data processing block, Lp_b (length of path memory block) into the data frame structure, the enable structure of the receiver and distribution of data enable gaps (during the field and segment syncs) is consistent with the data frame structure and repetitive within the data frame. That way, it is possible to design a system for which no enable gaps or a fixed number of enable gaps exist within the data processing blocks, L_pb. and the latency of the output data processing blocks with respect to the input is consistent and predictable within the data frame structure, facilitating the design of data interfaces in an iterative (turbo) implementation of the MAP decoder. The architecture of the present invention takes advantage of the (field and segment) sync structure in the current ATSC-DTV (A/53) standard. In addition, the high latency architecture can fold into the low latency architecture with a change of a parameter reflecting the size of the data processing block, Lpb- [0039] In one aspect of the present invention, latency can be selected using the data processing block parameter L_pb based on symbols in a segment as defined in Figure 5. The simplest way to take advantage of the sync structure of the ATSC-DTV standard is by noticing from Figures 5 and 6 that, by subtracting the 4 symbols of a segment sync, the amount of data symbols in each segment is Dseg=828 = 22x32x23 = 12x3x23, which is a multiple of 12, the number of decoders in the ATSC-DTV trellis code. This provides the following latency selection possibilities:

(a) L_pb= most simple form of low latency decoder, where the window size and all the operations happen on a symbol basis. This is desirable when the need for low latency is higher than the need for reliability, for example, in the aid of the equalizer convergence. (b) L_pb=3: another form of low latency decoder for which additional reliability is required.

(c) L_pb=23: most simple form of the high latency decoder and one with a good enough reliability. This results in 3 L]_2pb data processing blocks per segment, where L_12pb = 12*L_pb-

(d) L_pb=69: another form of high latency decoder with one Li_2pb data processing block per segment, giving an increased reliability.

[0040] In these instances (a-d above), the controller design is tied to the segment sync and may use every segment sync or every other segment sync as a reset for the controller counters associated with the various MAP decoder units, that is, the metric generator, alpha, beta and LLR units. The necessary synchronization, that is, the segment sync or the derived segment sync which signals every other segment sync would be provided by the sync processor in Figure 11 above.

[0041] As shown in Figure 11, the latency can be selected via a latency input into the MAP controller such that a value of L_pb can be selected to operate the MAP decoder in either a high or a low latency mode. For example, for the instance of an ATSC-DTV decoder, an input to the MAP controller that specifies a value of L_pb to be 3 would be considered a low latency selection for the operation of the MAP decoder. An input, to the MAP controller that specified a value of L_pb to be 23 would be considered a high latency selection for the operation of the MAP decoder.

[0042] In another aspect of the present invention, latency can be selected using the data processing block parameter L_pb based on symbols in multiple segments. More options for high and low latency can be derived from considering a higher number of segments, N. This is represented as Dseg*N=828xN = 22x32x23xN = 12x3x23 xN. For example, if N=2, then a low latency decoder could also have the value L_pb = 2 or 6, and a high latency decoder could also have the value L_pb = 46 or 138.

[0043] In these cases, the controller design needs to add a segment sync counter to count up to N. It is tied to the N segment sync counter and may use every N segment syncs or every other N segment sync as a reset for the controller counters associated with the various MAP decoder units, that is, the metric generator, alpha, beta and LLR units. It is also of interest that N is a factor of the number of data segments per field, 312, such that the data processing block window is encapsulated in a field sync. In that case, the controller counter will also be reset every field sync. The necessary synchronization, that is, the segment sync, field sync or the derived syncs would be provided by the sync processor in Figure 11 above.

[0044] Values of N < 10 are of particular interest for the low latency cases, since these will yield desirable values of low latency L_pb. In particular, if N must be a factor of 312, these will yield L_pb = 1, 2, 3, 4, 6, 8 and 9.

[0045] For the high latency cases, larger values of N might be of interest, since one can simplify the architecture by choosing an appropriately large data processing block L_pb- This simplification can result in the elimination of one of the two beta sub-units, since there will be enough symbols in the data processing block for the beta calculations to converge without substantially affecting the overall reliability. For example, for N = 156, it is possible to create a data processing block L_pb = 10764 symbols per decoder.

[0046] In one aspect of the present invention, latency can be selected using the data processing block parameter L_pb based a number N of data field symbols, wherein each data field has DFELD = 828x312 symbols, as defined in Figure 5. These cases are of interest for high latency decoders only, since it results in large values of data processing blocks, Lp_b. Similarly to the multiple segment case, the architecture can be simplified by the elimination of the one of the two beta sub-units, since there will be enough symbols in the data processing block for the beta calculations to converge without substantially affecting the overall reliability. For N > 1, there are already Lp_b = 21528 symbols per decoder in the data processing block and the counters in the MAP controller are reset every field sync. For N > 1 , there will be a need for a field counter up to N, which will provide a reset to the remaining counters in the MAP controller. It may use every N field sync or every other N field sync as a reset for the controller counters associated with the various MAP decoder units, that is, the metric generator, alpha, beta and LLR units. The necessary synchronization, that is, the field sync or the derived sync would be provided by the sync processor in Figure 1 1 above.

[0047] In one example embodiment, where a 12 trellis encoder is used (M=12), and a high latency decoder is selected such that L_pb = 23 and a low latency decoder is selected with L_pb = 1 , then there would be L_12pb = 12x23=276 symbols in the high latency processing block and L_12pb = 12x1 symbols in the low latency processing block. The segment size of 828 symbols is a multiple of both these numbers. So, there are 3 processing blocks per segment in the high latency decoder (828/276) and 69 processing blocks per segment in the low latency decoder (828/12). There is an integer number of processing blocks per segment to which a reset or initialization of the decoders to the segment sync detector can be attached such that whenever a segment sync is detected, the decoder counters can be reset. In a mobile terrestrial broadcast system, it is possible that the system will lose lock due to temporary channel conditions, such as travel through a tunnel for example, or other movement by a mobile receiver. Whenever the sync is lost and recovered, the decoder will reinitialize automatically and maintain compatibility with the incoming DTV data frame to achieve receiver synchronization.

[0048] Figure 12 is a timing diagram showing the relationships among the metric generator metrics for the alpha, beta 0 and beta 1 units, the MAP decoder LLR outputs, the respective data processing block (Lp_b) numbers, and the field and segment sync signals for the case where Lp_b is selected to be 23. The metric generator receives data and outputs the metrics with a latency of 2 data processing blocks. In this case of a high latency decoder where Lp_b=23, there are 12x23=276 symbols in a data processing block, 3 blocks per data segment, and 936 blocks in a field. Since the blocks are contained within a field, this structure is repetitive on every field. Also, although not specified in Figure 12, the segment sync is 4 symbols long and exists between blocks. Observe that there are specific gaps in the metric data streams and LLR output stream associated with the presence of the field and segment sync outputs, and these patterns are repetitive on every field, facilitating the MAP decoder operation and synchronization. In Figure 12, the hashed boxes depict the 4 symbol wide gaps at the input or output of specific data blocks that are associated with the segment sync. Other MAP decoder cases can be easily derived from this one. In this example, the MAP controller may use both the segment and field sync to create the necessary generated syncs needed to initialize the various MAP decoder units, since the processing block or path memory of the MAP decoder is tied to both synchronization signals.

[0049] In one aspect of the invention, a variable latency MAP decoder is realized that inputs a stream of digital symbols of size S. The data stream is encoded by a plurality M of interleaved trellis encoders, wherein M is greater than or equal to 1. The trellis encoder provides a trellis encoded data group for interleaving. The data group includes a stream of trellis encoded symbols. The MAP decoder includes a metric generator unit that outputs metrics corresponding to each symbol of the interleaved trellis-encoded data groups, the metrics including alpha and beta metrics, an alpha unit that inputs the alpha metrics and outputs accumulated alpha state metrics for each trellis encoded data group, a beta unit that inputs the beta metrics and outputs accumulated beta state metrics for each trellis encoded data group, and a log likelihood ratio unit that computes output values corresponding to the digital data using the accumulated alpha state metrics and accumulated beta state metrics. The MAP decoder provides a latency selection input wherein a processing block size per decoder in symbols, Lpb, is determinable. The latency input may be either a data input for values of Lpb or a selection input where a range of Lpb values is selectable. In either implementation, the latency input allows effective selection of either a low latency processing time or a high latency processing time in computing the output values of a soft decision from the LLR unit. The input selection of Lp is valid for a range where N*S is a multiple of D*M*Lpb where N and D are integer numbers greater than or equal to 1 and S is a particular size in which the data stream is organized, for example, a data segment or data field, and such that a synchronization signal is received by the decoder every S symbols, that is a segment or field sync, respectively. The low latency processing time is selected when Lpb is greater than or equal to 1. The high latency processing time is selected when Lpb is less than or equal to N*S/M. In addition, the low latency processing time is selected when Lpb is less than or equal to a threshold, Lthreshoid, and the high latency processing time is selected when Lpb is greater than Lthreshoid, wherein Lthreshoid is a selectable latency threshold value. [0050] If D is selected as an odd number and a first synchronization signal, such as a segment sync or field sync, is received with each S number of symbols, the MAP decoder generates a derived second synchronization signal every N first synchronization signals to initialize the metric generator alpha counters, alpha unit, and the log likelihood ratio unit. A derived third synchronization signal is also generated every other first synchronization signal to initialize the metric generator beta counters and beta unit.

[0051] If D is selected as an even number and a first synchronization signal, such as the segment or field sync signal, is received with each S number of symbols, then the MAP decoder generates a derived second synchronization signal every N first synchronization signals to initialize the metric generator metric counters, and the alpha, beta and log likelihood ratio units.

[0052] In addition, the input data stream may be organized in digital symbols of size F = K*S, where K is an integer. In this instance, a fourth synchronization signal is received with each F number of symbols. For example, this would be the case where S is the size of a data segment and F is the size of a data field. Here, the decoder initializes the metric generator counters, and the alpha, and the log likelihood ratio unit with every fourth synchronization signal.

[0053] If K is even, then the MAP decoder initializes the metric generator beta counters and beta unit with every fourth synchronization signal. If K is odd and the apparatus generates a fifth synchronization signal every other fourth synchronization signal to initialize the metric generator beta counters and beta unit.

[0054] The decoder can receive an Advanced Television Systems Committee (ATSC) standard segment synchronization signal with each S number of symbols, where S is the size of a data segment and a field synchronization signal with each F number of symbols, where F is the size of a data field. Alternately, the decoder can receive an Advanced Television Systems Committee (ATSC) standard field synchronization signal with each S number of symbols, where S is the size of a data field.

[0055] The implementations described herein may be implemented in, for example, a method or process, an apparatus, or a combination of hardware and software or hardware and firmware. Even if only discussed in the context of a single form of implementation, the implementation of features discussed may also be implemented in other forms (for example, an apparatus or a program executed in a computer). An apparatus may be implemented in, for example, appropriate hardware, software, and firmware. The methods may be implemented in, for example, an apparatus such as, for example, a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processing devices also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs"), and other devices that facilitate communication of information between end-users.

[0056] Implementations of the various processes and features described herein may be embodied in a variety of different equipment or applications, particularly, for example, equipment or applications associated with data transmission and reception. Examples of equipment include video coders, video decoders, video codecs, web servers, set-top boxes, laptops, personal computers, and other communication devices. As should be clear, the equipment may be mobile and even installed in a mobile vehicle.

[0057] Additionally, the methods may be implemented by instructions being performed by a processor, and such instructions may be stored on a processor-readable medium such as, for example, an integrated circuit, a software carrier or other storage device such as, for example, a hard disk, a compact diskette, a random access memory ("RAM"), a read-only memory ("ROM") or any other magnetic optical, or solid state media. The instructions may form an application program tangibly embodied on a processor-readable medium such as any of the media listed above. As should be clear, a processor may include, as part of the processor unit, a processor-readable medium having, for example, instructions for carrying out a process.

[0058] As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting; but rather, to provide an understandable description of the invention.

Claims

1. A maximum a posteriori (MAP) decoder apparatus operating with an input data stream organized in blocks, each block having S number of digital symbols, wherein the data stream is encoded by a plurality of M interleaved trellis encoders, each trellis encoder providing a trellis encoded data group for interleaving, the data group including a stream of trellis encoded symbols, the apparatus comprising:

a metric generator unit that accepts the input data stream and produces metrics corresponding to each digital symbol;

a log likelihood ratio unit that computes output values corresponding to the digital symbols, the output values derived from the metrics; and

a controller having a latency selection input, wherein a processing block size in symbols, L_pb, is selectable to provide one of a low latency processing time and a high latency processing time in computing the output values.

2. The apparatus of claim 1, wherein the metric generator unit outputs metrics that include alpha metrics and beta metrics.

3. The apparatus of claim 2, wherein the apparatus further comprises:

an alpha unit that inputs the alpha metrics and outputs accumulated alpha state metrics for each trellis encoded data group;

a beta unit that inputs the beta metrics and outputs accumulated beta state metrics for each trellis encoded data group; and

wherein the log likelihood ratio unit computes output values corresponding to the digital symbols using the accumulated alpha state metrics and accumulated beta state metrics.

4. The apparatus of claim 1, wherein the low latency processing time is selected when Lpb is less than or equal to a threshold value of latency and the high latency processing time is selected when L_pb is greater than the threshold value of latency.

5. The apparatus of claim 1, wherein the controller operates provided that N*S is a multiple of D*M*L_pb where M, N, and D are integer numbers greater than or equal to 1.

6. The apparatus of claim 5, wherein the low latency processing time is selected when L_pb is greater than or equal to 1.

7. The apparatus of claim 5, wherein the high latency processing time is selected when L_pb is less than or equal to N*S/M.

8. The apparatus of claim 5, wherein D is selected as an odd number and a first synchronization signal is received with each S number of symbols, the apparatus generates a second synchronization signal every N first synchronization signals to initialize the metric generator alpha counters, alpha unit and the log likelihood ratio unit and a third

synchronization signal every other first synchronization signal to initialize the metric generator beta counters and beta unit.

9. The apparatus of claim 5, wherein D is selected as an even number and a first synchronization signal is received with each S number of symbols, the apparatus generates a second synchronization signal every N first synchronization signals to initialize the metric generator metric counters, and the alpha unit, the beta unit, and the log likelihood ratio unit in the apparatus.

10. The apparatus of claim 5, wherein the input data stream is organized in digital symbols of size F = K*S, where K is an integer and a fourth synchronization signal is received with each F number of symbols, and the apparatus initializes the metric generator alpha counters, the alpha unit and the log likelihood ratio unit with every fourth

synchronization signal.

11. The apparatus of claim 10, wherein K is even and the apparatus initializes the metric generator beta counters and beta unit with every fourth synchronization signal.

12. The apparatus of claim 10, wherein K is odd and the apparatus generates a fifth synchronization signal every other fourth synchronization signal to initialize the metric generator beta counters and beta unit.

13. The apparatus of claim 10, wherein the apparatus receives an Advanced Television Systems Committee (ATSC) standard segment synchronization signal with each S number of symbols and a field synchronization signal with each F number of symbols.

14. The apparatus of claim 1, wherein the apparatus receives an Advanced Television Systems Committee (ATSC) standard segment synchronization signal with each S number of symbols.

15. The apparatus of claim 1, wherein the apparatus receives an Advanced Television Systems Committee (ATSC) standard field synchronization signal with each S number of symbols.

16. The apparatus of claim 1, wherein the digital data stream is encoded using 12 interleaved trellis encoders in accordance with the Advanced Television Systems Committee (ATSC) standard for digital television.