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WO2010055614A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2010055614A1
WO2010055614A1 PCT/JP2009/005557 JP2009005557W WO2010055614A1 WO 2010055614 A1 WO2010055614 A1 WO 2010055614A1 JP 2009005557 W JP2009005557 W JP 2009005557W WO 2010055614 A1 WO2010055614 A1 WO 2010055614A1
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WO
WIPO (PCT)
Prior art keywords
inductor
inductor element
semiconductor substrate
semiconductor
semiconductor device
Prior art date
Application number
PCT/JP2009/005557
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French (fr)
Japanese (ja)
Inventor
松永朋弘
広藤裕一
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パナソニック株式会社
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Publication of WO2010055614A1 publication Critical patent/WO2010055614A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a semiconductor device having an inductor element.
  • an inductor element there is one in which a conductive film such as aluminum is spirally or wound on an insulating film formed on the surface of a semiconductor substrate.
  • the semiconductor substrate exists in the vicinity of the inductor element. For this reason, it is known that an eddy current that prevents a change in magnetic field generated when a current is passed through the inductor element is generated in the semiconductor substrate, resulting in a deterioration in the characteristics of the inductor element.
  • the semiconductor substrate containing impurities itself has a low resistance value, and thus acts like a short-circuited secondary coil in a high-frequency region. Since the deterioration of the characteristics of the inductor element due to the presence of the secondary coil appears remarkably in the high frequency region, a proposal has been made for preventing the generation of eddy currents in the semiconductor substrate.
  • Japanese Patent Application Laid-Open No. 07-183468 discloses that a plurality of PN junctions are formed on the surface of a silicon substrate, and eddy current is suppressed by a depletion layer formed by the PN junctions.
  • the above publication discloses a configuration in which eddy currents are suppressed by dividing a path of eddy currents formed on the surface of a semiconductor substrate by a plurality of depletion layers.
  • This known example also shows that the generation of eddy currents can be suppressed by the depletion layer formed on the surface of the semiconductor substrate.
  • FIG. 5 is a diagram showing the structure of the above-described known inductor element.
  • An N-type impurity region 14 is formed on the surface of the P-type semiconductor substrate 11, and thus a plurality of PN junctions are formed on the surface of the semiconductor substrate 11.
  • a spiral conductive film 16 is formed on the insulating film 12 formed on the surface of the semiconductor substrate 11.
  • One end 16 A of the conductive film 16 is connected to a wiring (not shown), and the other end 16 B of the conductive film 16 is connected to a lower wiring 18 formed in the insulating film 12.
  • a current is passed in the direction of arrow 22 in the figure from one end 16A to the other end 16B of the conductive film 16, a magnetic field perpendicular to the surface of the semiconductor substrate 11 is generated in the spiral wiring.
  • the width (thickness) of the depletion layer formed in the semiconductor substrate below the inductor element is about 1 to 10 ⁇ m, the magnetic flux generated in the inductor element passes through the depletion layer. The semiconductor substrate under the depletion layer is reached. Thereby, since an eddy current is induced in the semiconductor substrate, it is difficult to suppress the generation of the eddy current.
  • the self-resonant frequency of the inductor element cannot be increased due to the parasitic capacitance between the semiconductor substrate and the inductor wiring. Therefore, it is difficult to increase the maximum usable frequency, and it is difficult to increase the Q value (Quality Factor) that is an index of the performance of the inductor element.
  • the present invention has been made in view of such problems, and an object thereof is to increase the maximum usable frequency and improve the Q value in a semiconductor device having an inductor element.
  • a semiconductor device of the present invention includes a semiconductor integrated circuit and an inductor element electrically connected to the semiconductor integrated circuit, and the inductor element is disposed outside a semiconductor substrate constituting the semiconductor integrated circuit.
  • both terminals provided at each end in the longitudinal direction of the inductor element are electrically connected to the semiconductor substrate.
  • a conductor pad may be provided on the surface of the semiconductor substrate, and the terminals of the inductor element may be connected to the semiconductor substrate via the conductor pad.
  • the inductor element is composed of a winding of one turn or more, and the terminals of the inductor element may be arranged on the same side with respect to the winding center of the inductor element.
  • the inductor element is preferably composed of one or more turns.
  • the semiconductor device of the present invention preferably includes a plurality of inductor elements, and the plurality of inductor elements are preferably arranged so as not to be inductively coupled.
  • the semiconductor device of the present invention since there is no semiconductor substrate immediately below the inductor element, eddy currents induced by the magnetic field of the inductor element are suppressed, and the parasitic capacitance between the inductor element and the semiconductor substrate is reduced. Therefore, the loss of the inductor element is suppressed, the maximum operating frequency is increased, and the Q value is improved.
  • FIG. 1A is a perspective view of a semiconductor device according to the first embodiment of the present invention
  • FIG. 1B is a sectional view thereof
  • FIG. 1C is a plan view thereof
  • FIG. 2 is a plan view showing the arrangement of inductances in the first embodiment of the present invention
  • 3A is a perspective view of the semiconductor device according to the first embodiment of the present invention
  • FIG. 3B is a sectional view thereof
  • FIG. 3C is a plan view thereof.
  • FIG. 4A is a plan view showing the arrangement of inductance in the second embodiment of the present invention
  • FIG. 4B is a cross-sectional view taken along the line IVB-IVB ′ shown in FIG.
  • FIG. 5 is a perspective view of a conventional semiconductor device.
  • FIG. 1A is a perspective view of a semiconductor device 1 according to the present embodiment
  • FIG. 1B is a cross-sectional view thereof
  • FIG. 1C is a plan view thereof.
  • the semiconductor chip 20 has inductor elements 201 and 202, vias 203 and wirings 204 inside an insulator, and has a conductor pad 205 on the surface.
  • the conductor pad refers to a region where a conductor forming a metal wiring or the like is exposed, and serves as a connection terminal for wire bonding or a connection terminal with another chip.
  • FIG. 2 shows an example of a layout diagram of the inductor elements 201 and 202.
  • the inductor element 201 is a normal inductor in which wirings of the same layer are formed in a spiral shape
  • the inductor element 202 is a differential type inductor in which the spiral shape is symmetrical from either of the two terminals.
  • inductor elements 201 and 202 terminals (provided at the ends in the longitudinal direction of the inductor elements) are arranged on the same side with respect to the winding centers of the inductor elements 201 and 202, respectively.
  • two differently shaped inductor elements are shown side by side, but this is to show that the inductor elements of various shapes are targeted, and in fact, one inductor element is arranged. In some cases, a plurality of inductor elements having the same shape may be arranged.
  • the inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, and are arranged so that lines of magnetic force are generated in a direction perpendicular to the main surface of the semiconductor substrate 11.
  • a semiconductor chip 10 is formed on the semiconductor substrate 11, and the semiconductor chip 10 is a semiconductor chip constituting a semiconductor integrated circuit including transistors, resistors, capacitors, and the like.
  • the arrangement without inductive coupling means an arrangement in which the magnetic lines of force induced by one inductor do not substantially generate an electromotive force in the other inductor.
  • one terminal of the plurality of inductor elements may be shared. Furthermore, as a shape other than the inductor element shown in FIG.
  • the inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, but may be arranged to be inductively coupled to each other depending on the application. For example, if a lead wire is provided in the middle of the winding of the inductor element 202 and the windings of the two inductor elements overlap each other, both inductor elements are inductively coupled, and a magnetic field generated in one inductor element. Thus, it is possible to generate an electromotive force in the other inductor element.
  • the semiconductor chip 10 and the semiconductor chip 20 are sequentially provided on the lead frame 40 of the GND potential.
  • Conductive pads 205 are arranged on the surface of the semiconductor chip 20, and vias 203 are connected to the conductive pads 205, and wirings 204 are connected to each other in the longitudinal direction of the vias 203 at intervals.
  • lead wires 206 are connected to the terminals of the inductor elements 201 and 202 provided inside the semiconductor chip 20, and vias 203 are connected to the lead wires 206.
  • Vias 203 connected to the conductor pads 205 and the lead-out wirings 206 are connected to the conductor pads 101 disposed on the surface of the semiconductor chip 10 via the gold bumps 50, respectively. Are electrically connected to each other. Further, the conductor pads 205 of the semiconductor chip 20 are connected to the leads 41 of the lead frame 40 via the wires 30, whereby the semiconductor chip 20 and the lead frame 40 are electrically connected to each other.
  • the conductor pad 101 and the via 203 are connected via the gold bump 50 so that the inductor elements 201 and 202 are arranged outside the semiconductor substrate.
  • each element such as a transistor, a resistor and a capacitor formed on the semiconductor chip 10 is electrically connected to the inductor elements 201 and 202 and the wiring 204 of the semiconductor chip 20 via the conductor pad 101 and the gold bump 50. ing.
  • the bottom surface of the via 203 is exposed so that the back surface can be electrically connected to the semiconductor chip 10. Thinned.
  • the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202. Therefore, the distance between the inductor elements 201 and 202 and GND is longer than when the semiconductor substrate 11 is disposed directly below the inductor elements 201 and 202 between the inductor element and the lead frame 40. Therefore, the eddy current induced in the semiconductor substrate 11 by the magnetic field of the inductor elements 201 and 202 is reduced, and the loss of the inductor elements 201 and 202 is suppressed.
  • the parasitic capacitance value C between the wiring of the inductor elements 201 and 202 and GND is reduced, the self-resonance frequency is increased and the maximum usable frequency is increased.
  • the parallel capacitance component is reduced, the Q values of the inductor elements 201 and 202 are improved.
  • the inductor elements 201 and 202 by providing a cutout in the lead frame 40 immediately below the inductor elements 201 and 202, it is possible to suppress the generation of eddy currents in the lead frame 40, and the inductor elements 201 and 202 and the lead frame Parasitic capacitance between 40 can also be reduced. Therefore, the characteristics of the inductor element can be improved by further improving the Q value.
  • the inductor elements 201 and 202 having excellent high frequency characteristics can be integrated by adopting a mounting layout in which the semiconductor chip 10 is not disposed immediately below the inductor elements 201 and 202. Incidentally, even if the inductor elements 201 and 202 are arranged outside the semiconductor chip 10, the inductor elements 201 and 202 are not arranged outside the lead frame 40, so that it is not necessary to enlarge the package.
  • FIG. 3 is a structural diagram of the semiconductor device 2 according to the second embodiment.
  • FIGS. 3A, 3B, and 3C are a perspective view, a cross-sectional view, and a plan view, respectively.
  • the semiconductor chip 20 is a dedicated chip for the inductor element in which only the inductor elements 201 and 202 are provided, and the wire 30 is drawn from the conductor pad 205 on the surface of the semiconductor chip 10.
  • the semiconductor chip 20 is disposed on the semiconductor chip 10 so that the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202 of the semiconductor chip 20.
  • Each terminal of the inductor elements 201 and 202 is connected to the gold bump 50 through the lead wiring 206 and the via 203, and the gold bump 50 is connected to the conductor pad 205 disposed on the peripheral edge of the surface of the semiconductor chip 10. ing.
  • the spiral portions of the inductor elements 201 and 202 are disposed outside the semiconductor substrate 11 and are electrically connected to each element of the semiconductor substrate 11 by connection wirings at both ends of the inductor elements 201 and 202.
  • FIG. 4A is a schematic plan view of the semiconductor chip 20 dedicated to the inductor element, in which only the inductor element 201 shown in FIG. 3 is extracted and described.
  • the inductor element 201 is formed on a substrate 200 made of, for example, a resin material.
  • the substrate 200 may be a material other than a resin such as ceramic as long as the substrate 200 is an insulating material.
  • FIG. 4B is a cross-sectional view taken along the line IVB-IVB ′ of FIG.
  • An inductor element 201 made of metal is formed on the upper surface of the substrate 200.
  • Lead wires 206 made of metal are connected to both ends of the inductor element 201, one of the lead wires 206 is provided on the lower surface of the substrate 200, and is connected to one end of the inductor element through the through electrode 207. Electrically connected.
  • a conductor pad 101 for connecting the semiconductor chip 20 to the semiconductor chip 10 is formed on the lower surface of the substrate 200. Therefore, the conductor pad 101 is formed on the same surface as the one lead wiring 206. ing.
  • the conductor pad 101 of the semiconductor chip 20 configured as described above is connected to the conductor pad 205 provided on the peripheral edge of the surface of the semiconductor chip 10 via, for example, a gold bump 50.
  • a gold bump 50 for example, a gold bump 50.
  • the inductor elements 201 and 202 are arranged outside the semiconductor substrate 11 as in the first embodiment.
  • the semiconductor substrate 11 is not disposed. Therefore, also in this embodiment, the same effect as in the first embodiment can be obtained.
  • the inductor element is installed so that the magnetic field generated in the inductor element is oriented perpendicular to the main surface of the semiconductor substrate 11 forming the semiconductor chip 10. It is also possible to install the inductor element so as to be parallel to the main surface. That is, the inductor element may protrude from the end portion of the semiconductor substrate 11 to the side surface, and the windings constituting the inductor element may be formed substantially perpendicular to the main surface of the semiconductor substrate 11 and the protruding side surface.
  • the magnetic field induced by the inductor element is generated at an angle that is neither parallel nor perpendicular to the main surface of the semiconductor substrate, the magnetic field can be prevented from directly affecting the semiconductor chip.
  • the same effects as in the first and second embodiments can be obtained.
  • the entire inductor element is disposed outside the semiconductor substrate 11 to suppress the magnetic field from reaching the semiconductor substrate.
  • the semiconductor device such as the operating frequency
  • a predetermined value is obtained if the entire inductor element is not arranged outside the semiconductor substrate 11 but at least the center of the winding portion is arranged outside the semiconductor substrate 11, a predetermined value is obtained. An effect can be obtained. Also in this case, since the range covered by the magnetic field from the inductor element is the periphery of the semiconductor chip, it is possible to prevent the layout of transistors and the like that may cause malfunctions from being restricted by the magnetic field.
  • the present invention is not limited to the above-described embodiment, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention.
  • the inductor element only needs to have one or more turns, and the number of turns is not particularly limited.
  • the eddy current induced in the semiconductor substrate by the magnetic field of the inductor element is reduced, the loss of the inductor element is suppressed, and the parasitic capacitance between the wiring of the inductor element and GND is reduced. Is effective as a high-frequency semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

In a semiconductor device (1), inductor elements (201, 202) are arranged at the outer side as compared to a semiconductor substrate (11).

Description

半導体装置Semiconductor device

　本発明は、インダクタ素子を有する半導体装置に関するものである。 The present invention relates to a semiconductor device having an inductor element.

　近年、携帯電話等の携帯通信機器の小型化が進められている。携帯通信機器の小型化のために、高周波回路をシリコン集積回路に１チップ化する要求が高まってきている。ところが、高周波回路には、トランジスタ、抵抗および容量に加えて、コイル又はトランスといったインダクタ素子が必要である。よって、シリコン基板上に、トランジスタ又は抵抗等を利用した集積回路と共にインダクタ素子を形成する方法が開発されている。インダクタ素子は、電圧制御型発振回路（VCO；voltage-controlled oscillator）等の発振回路に用いられており、安定な発振周波数および高い周波数の発振波形を得るために、より高性能なインダクタ素子が求められる。 In recent years, mobile communication devices such as mobile phones have been reduced in size. In order to reduce the size of portable communication devices, there is an increasing demand for a high-frequency circuit to be integrated into a silicon integrated circuit on a single chip. However, the high frequency circuit requires an inductor element such as a coil or a transformer in addition to a transistor, a resistor, and a capacitor. Therefore, a method for forming an inductor element on a silicon substrate together with an integrated circuit using a transistor or a resistor has been developed. Inductor elements are used in oscillation circuits such as voltage-controlled oscillators (VCO), and higher-performance inductor elements are required to obtain stable oscillation frequencies and high-frequency oscillation waveforms. It is done.

　インダクタ素子として、半導体基板の表面に形成した絶縁膜上に、アルミニウム等の導電膜が渦巻き状にあるいは巻き線状に形成されたものがある。しかしながら、このような構成では、インダクタ素子の近傍に半導体基板が存在する。そのため、インダクタ素子に電流を流した時に発生する磁界の変化を妨げる渦電流がその半導体基板中に発生して、インダクタ素子の特性低下を伴うということが知られている。 As an inductor element, there is one in which a conductive film such as aluminum is spirally or wound on an insulating film formed on the surface of a semiconductor substrate. However, in such a configuration, the semiconductor substrate exists in the vicinity of the inductor element. For this reason, it is known that an eddy current that prevents a change in magnetic field generated when a current is passed through the inductor element is generated in the semiconductor substrate, resulting in a deterioration in the characteristics of the inductor element.

　即ち、巻き線状に形成された帯状導電層をトランスにおける一次コイルと考えると、不純物を含む半導体基板そのものは、抵抗値が低いので、高周波領域では短絡された二次コイルのように作用する。この二次コイルの存在によるインダクタ素子の特性低下は特に高周波領域において顕著に現れるので、半導体基板内の渦電流の発生を防止する為の提案がなされている。例えば、特開平０７－１８３４６８号公報には、シリコン基板の表面に複数のＰＮ接合を形成し、そのＰＮ接合により形成される空乏層により渦電流を抑制することが示されている。つまり、上記公報には、半導体基板の表面に形成される渦電流の経路を複数の空乏層により分断することにより渦電流を抑制するという構成が開示されている。この公知例においても、半導体基板の表面に形成される空乏層により渦電流の発生が抑えられることが示されている。 That is, when the band-shaped conductive layer formed in a winding shape is considered as a primary coil in a transformer, the semiconductor substrate containing impurities itself has a low resistance value, and thus acts like a short-circuited secondary coil in a high-frequency region. Since the deterioration of the characteristics of the inductor element due to the presence of the secondary coil appears remarkably in the high frequency region, a proposal has been made for preventing the generation of eddy currents in the semiconductor substrate. For example, Japanese Patent Application Laid-Open No. 07-183468 discloses that a plurality of PN junctions are formed on the surface of a silicon substrate, and eddy current is suppressed by a depletion layer formed by the PN junctions. That is, the above publication discloses a configuration in which eddy currents are suppressed by dividing a path of eddy currents formed on the surface of a semiconductor substrate by a plurality of depletion layers. This known example also shows that the generation of eddy currents can be suppressed by the depletion layer formed on the surface of the semiconductor substrate.

　図５は、上記公知例のインダクタ素子の構造を示す図である。Ｐ型の半導体基板１１の表面にＮ型の不純物領域１４が形成されており、よって、半導体基板１１の表面に複数のＰＮ接合が形成される。そして、半導体基板１１の表面上に形成された絶縁膜１２上に、渦巻き状の導電膜１６が形成される。この導電膜１６の一端１６Ａは、図示しない配線に接続され、また、この導電膜１６の他端１６Ｂは、絶縁膜１２内に形成された下層の配線１８に接続される。導電膜１６の一端１６Ａから他端１６Ｂに向かって図中の矢印２２の方向に電流を流すと、半導体基板１１の表面に垂直な磁界が渦巻き配線内に発生する。 FIG. 5 is a diagram showing the structure of the above-described known inductor element. An N-type impurity region 14 is formed on the surface of the P-type semiconductor substrate 11, and thus a plurality of PN junctions are formed on the surface of the semiconductor substrate 11. Then, a spiral conductive film 16 is formed on the insulating film 12 formed on the surface of the semiconductor substrate 11. One end 16 A of the conductive film 16 is connected to a wiring (not shown), and the other end 16 B of the conductive film 16 is connected to a lower wiring 18 formed in the insulating film 12. When a current is passed in the direction of arrow 22 in the figure from one end 16A to the other end 16B of the conductive film 16, a magnetic field perpendicular to the surface of the semiconductor substrate 11 is generated in the spiral wiring.

　図５に示された構成では、複数のＰＮ接合により空乏層が形成されるので、半導体基板１１の表面側に空乏層が多く形成される。よって、渦電流が流れる抵抗を高くすることができる。従って、渦電流を抑制し、渦電流によるインダクタ素子の特性低下とインダクタンスの低下とを防止することができる。 In the configuration shown in FIG. 5, since a depletion layer is formed by a plurality of PN junctions, many depletion layers are formed on the surface side of the semiconductor substrate 11. Therefore, the resistance through which eddy current flows can be increased. Therefore, it is possible to suppress eddy currents and prevent a decrease in inductor element characteristics and inductance due to eddy currents.

特開平０７－１８３４６８号公報Japanese Patent Application Laid-Open No. 07-183468

　しかしながら、従来の半導体装置において、インダクタ素子の下部の半導体基板中に形成される空乏層の幅（厚さ）は1～10μm程度であるため、インダクタ素子で発生した磁束は空乏層を透過して、空乏層下の半導体基板に到達する。これにより、半導体基板中に渦電流が誘起するので、渦電流の発生を抑制することは難しい。また、半導体基板とインダクタ配線との間の寄生容量により、インダクタ素子の自己共振周波数を高くできない。そのため、最大使用周波数を上げることは難しく、また、インダクタ素子の性能の指標となるQ値（Quality Factor）を上げることは難しい。更に、空乏層を半導体基板中に形成する必要があるため、インダクタ下部の半導体基板中に集積回路素子を形成できないという課題がある。このことは、半導体基板内に回路を構成するためのレイアウト設計上の大きな制約になるとともに、インダクタは一般に大きな面積を要するためにチップサイズが大きくなるという問題を引き起こす。 However, in the conventional semiconductor device, since the width (thickness) of the depletion layer formed in the semiconductor substrate below the inductor element is about 1 to 10 μm, the magnetic flux generated in the inductor element passes through the depletion layer. The semiconductor substrate under the depletion layer is reached. Thereby, since an eddy current is induced in the semiconductor substrate, it is difficult to suppress the generation of the eddy current. In addition, the self-resonant frequency of the inductor element cannot be increased due to the parasitic capacitance between the semiconductor substrate and the inductor wiring. Therefore, it is difficult to increase the maximum usable frequency, and it is difficult to increase the Q value (Quality Factor) that is an index of the performance of the inductor element. Furthermore, since it is necessary to form a depletion layer in the semiconductor substrate, there is a problem that an integrated circuit element cannot be formed in the semiconductor substrate below the inductor. This is a major limitation in layout design for configuring a circuit in a semiconductor substrate, and causes a problem that an inductor generally requires a large area and thus has a large chip size.

　本発明はかかる問題点に鑑みてなされたものであって、インダクタ素子を有する半導体装置において最大使用周波数を高くするとともにQ値を向上させることを目的とする。 The present invention has been made in view of such problems, and an object thereof is to increase the maximum usable frequency and improve the Q value in a semiconductor device having an inductor element.

　本発明の半導体装置は、半導体集積回路と半導体集積回路と電気的に接続されたインダクタ素子とを有しており、インダクタ素子は、半導体集積回路を構成する半導体基板よりも外側に配置されている。かかる構成により、インダクタ素子に発生する磁界による半導体基板内での渦電流の誘起が抑制され、インダクタ素子と半導体基板との間の寄生容量が低減される。よって、インダクタ素子の損失が抑制されるので、最大使用周波数が高くなり、Q値が向上する。 A semiconductor device of the present invention includes a semiconductor integrated circuit and an inductor element electrically connected to the semiconductor integrated circuit, and the inductor element is disposed outside a semiconductor substrate constituting the semiconductor integrated circuit. . With this configuration, induction of eddy currents in the semiconductor substrate due to the magnetic field generated in the inductor element is suppressed, and the parasitic capacitance between the inductor element and the semiconductor substrate is reduced. Therefore, since the loss of the inductor element is suppressed, the maximum usable frequency is increased and the Q value is improved.

　本発明の半導体装置では、インダクタ素子の長手方向における各端に設けられた端子はどちらも、半導体基板に電気的に接続されていることが好ましい。この場合、半導体基板の表面に導体パッドを有し、インダクタ素子の端子がそれぞれ導体パッドを介して半導体基板に接続されていればよい。また、インダクタ素子は１ターン以上の巻き線からなり、インダクタ素子の端子はインダクタ素子の巻き中心に対して互いに同じ側に配置されていればよい。 In the semiconductor device of the present invention, it is preferable that both terminals provided at each end in the longitudinal direction of the inductor element are electrically connected to the semiconductor substrate. In this case, a conductor pad may be provided on the surface of the semiconductor substrate, and the terminals of the inductor element may be connected to the semiconductor substrate via the conductor pad. Further, the inductor element is composed of a winding of one turn or more, and the terminals of the inductor element may be arranged on the same side with respect to the winding center of the inductor element.

　本発明の半導体装置では、インダクタ素子は、１ターン以上の巻き線からなることが好ましい。 In the semiconductor device of the present invention, the inductor element is preferably composed of one or more turns.

　本発明の半導体装置では、複数のインダクタ素子を具備することが好ましく、複数のインダクタ素子は誘導結合しないように配置されていることが好ましい。 The semiconductor device of the present invention preferably includes a plurality of inductor elements, and the plurality of inductor elements are preferably arranged so as not to be inductively coupled.

　本発明による半導体装置によれば、インダクタ素子の直下に半導体基板がないため、インダクタ素子の磁界により誘起される渦電流が抑制され、インダクタ素子と半導体基板との間の寄生容量が低減される。よって、インダクタ素子の損失が抑制され、更に、最大使用周波数が高くなり、Q値が向上する。 According to the semiconductor device of the present invention, since there is no semiconductor substrate immediately below the inductor element, eddy currents induced by the magnetic field of the inductor element are suppressed, and the parasitic capacitance between the inductor element and the semiconductor substrate is reduced. Therefore, the loss of the inductor element is suppressed, the maximum operating frequency is increased, and the Q value is improved.

図１（ａ）は本発明の実施の形態１に係る半導体装置の斜視図であり、図１（ｂ）はその断面図であり、図１（ｃ）はその平面図である。FIG. 1A is a perspective view of a semiconductor device according to the first embodiment of the present invention, FIG. 1B is a sectional view thereof, and FIG. 1C is a plan view thereof. 図２は、本発明の実施の形態１におけるインダクタンスの配置を示す平面図である。FIG. 2 is a plan view showing the arrangement of inductances in the first embodiment of the present invention. 図３（ａ）は本発明の実施の形態１に係る半導体装置の斜視図であり、図３（ｂ）はその断面図であり、図３（ｃ）はその平面図である。3A is a perspective view of the semiconductor device according to the first embodiment of the present invention, FIG. 3B is a sectional view thereof, and FIG. 3C is a plan view thereof. 図４（ａ）は本発明の実施の形態２におけるインダクタンスの配置を示す平面図であり、図４（ｂ）は図４（ａ）に示すIVB－IVB'線における断面図である。FIG. 4A is a plan view showing the arrangement of inductance in the second embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along the line IVB-IVB ′ shown in FIG. 図５は従来の半導体装置の斜視図である。FIG. 5 is a perspective view of a conventional semiconductor device.

　以下、半導体装置等の実施形態について図面を参照して説明する。なお、実施の形態において同じ符号を付した構成要素は同様の動作を行うので、説明を省略する場合がある。また、本発明は以下に示す構成に限定されない。 Hereinafter, embodiments of a semiconductor device and the like will be described with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted. Further, the present invention is not limited to the configuration shown below.

　（実施の形態１）
　本発明の実施の形態１について説明する。 (Embodiment 1)
Embodiment 1 of the present invention will be described.

　図１（ａ）は、本実施の形態に係る半導体装置１の斜視図であり、図１（ｂ）はその断面図であり、図１（ｃ）はその平面図である。 1A is a perspective view of a semiconductor device 1 according to the present embodiment, FIG. 1B is a cross-sectional view thereof, and FIG. 1C is a plan view thereof.

　半導体チップ２０は、絶縁物の内部にインダクタ素子２０１、２０２、ビア２０３および配線２０４を有し、表面に導体パッド２０５を有している。導体パッドとは、金属配線等を形成する導体が露出した領域を示し、ワイヤボンディングを行う際の接続端子又は他のチップとの接続端子となる。図２に、インダクタ素子２０１、２０２の配置図の一例を示す。インダクタ素子２０１は、同一層の配線を渦巻き状に形成した通常のインダクタであり、インダクタ素子２０２は、２端子のどちらの端子からも渦巻き形状が対称になる差動タイプのインダクタである。インダクタ素子２０１、２０２では、それぞれ、端子（インダクタ素子の長手方向における端に設けられている）がインダクタ素子２０１、２０２の巻き中心に対して互いに同じ側に配置されている。ここでは、便宜上２つの異なる形状のインダクタ素子を並べて示しているが、これは種々の形状のインダクタ素子を対象としていることを示すためであって、実際には一つのインダクタ素子が配置されている場合や同じ形状のインダクタ素子が複数配置されている場合がある。 The semiconductor chip 20 has inductor elements 201 and 202, vias 203 and wirings 204 inside an insulator, and has a conductor pad 205 on the surface. The conductor pad refers to a region where a conductor forming a metal wiring or the like is exposed, and serves as a connection terminal for wire bonding or a connection terminal with another chip. FIG. 2 shows an example of a layout diagram of the inductor elements 201 and 202. The inductor element 201 is a normal inductor in which wirings of the same layer are formed in a spiral shape, and the inductor element 202 is a differential type inductor in which the spiral shape is symmetrical from either of the two terminals. In the inductor elements 201 and 202, terminals (provided at the ends in the longitudinal direction of the inductor elements) are arranged on the same side with respect to the winding centers of the inductor elements 201 and 202, respectively. Here, for the sake of convenience, two differently shaped inductor elements are shown side by side, but this is to show that the inductor elements of various shapes are targeted, and in fact, one inductor element is arranged. In some cases, a plurality of inductor elements having the same shape may be arranged.

　インダクタ素子２０１、２０２は互いに誘導結合しないように配置されており、半導体基板１１の主表面に対して垂直方向に磁力線が発生するように配置されている。ここで、半導体基板１１には半導体チップ１０が形成されており、半導体チップ１０はトランジスタ、抵抗および容量などを含む半導体集積回路を構成する半導体チップである。また、誘導結合しない配置とは、一方のインダクタによって誘起される磁力線が実質的に他方のインダクタに起電力を生じさせることがない配置のことを言う。また、複数のインダクタ素子を具備する場合、複数のインダクタ素子の一方の端子を共用する場合がある。更に、図２に示したインダクタ素子以外の形状として、スパイラル部における巻き線の数が異なるインダクタ素子、又は、平面的な巻き線だけでなく立体的な巻き線からなるインダクタ素子を使用することもできる。また、本実施の形態ではインダクタ素子２０１、２０２は、互いに誘導結合しないように配置されているとしているが、用途により互いに誘導結合するように配置されていても良い。例えば、インダクタ素子２０２の巻き線の中間に引き出し線を設けて、２つのインダクタ素子の巻き線が互いに重なった構成とすれば、双方のインダクタ素子は誘導結合し、一方のインダクタ素子に発生する磁界により他方のインダクタ素子に起電力を生じさせることが可能である。 The inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, and are arranged so that lines of magnetic force are generated in a direction perpendicular to the main surface of the semiconductor substrate 11. Here, a semiconductor chip 10 is formed on the semiconductor substrate 11, and the semiconductor chip 10 is a semiconductor chip constituting a semiconductor integrated circuit including transistors, resistors, capacitors, and the like. The arrangement without inductive coupling means an arrangement in which the magnetic lines of force induced by one inductor do not substantially generate an electromotive force in the other inductor. When a plurality of inductor elements are provided, one terminal of the plurality of inductor elements may be shared. Furthermore, as a shape other than the inductor element shown in FIG. 2, it is also possible to use an inductor element having a different number of windings in the spiral portion, or an inductor element having not only a planar winding but also a three-dimensional winding. it can. In the present embodiment, the inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, but may be arranged to be inductively coupled to each other depending on the application. For example, if a lead wire is provided in the middle of the winding of the inductor element 202 and the windings of the two inductor elements overlap each other, both inductor elements are inductively coupled, and a magnetic field generated in one inductor element. Thus, it is possible to generate an electromotive force in the other inductor element.

　ここで、本実施の形態に係る半導体装置の構成を簡潔に記すと、GND電位のリードフレーム４０の上に半導体チップ１０および半導体チップ２０が順に設けられている。半導体チップ２０の表面には導体パッド２０５が配置されており、この導体パッド２０５にはそれぞれビア２０３が接続されており、各ビア２０３の長手方向には配線２０４が互いに間隔を開けて接続されている。また、半導体チップ２０の内部に設けられたインダクタ素子２０１、２０２の端子にはそれぞれ引き出し配線２０６が接続されており、引き出し配線２０６にはそれぞれビア２０３が接続されている。 Here, when the configuration of the semiconductor device according to the present embodiment is briefly described, the semiconductor chip 10 and the semiconductor chip 20 are sequentially provided on the lead frame 40 of the GND potential. Conductive pads 205 are arranged on the surface of the semiconductor chip 20, and vias 203 are connected to the conductive pads 205, and wirings 204 are connected to each other in the longitudinal direction of the vias 203 at intervals. Yes. In addition, lead wires 206 are connected to the terminals of the inductor elements 201 and 202 provided inside the semiconductor chip 20, and vias 203 are connected to the lead wires 206.

　導体パッド２０５および引き出し配線２０６に接続されたビア２０３はそれぞれ金バンプ５０を介して半導体チップ１０の表面に配置された導体パッド１０１に接続されており、これにより、半導体チップ１０と半導体チップ２０とは互いに電気的に接続されている。また、半導体チップ２０の導体パッド２０５はワイヤー３０を介してリードフレーム４０のリード４１に接続されており、これにより、半導体チップ２０とリードフレーム４０とは互いに電気的に接続されている。 Vias 203 connected to the conductor pads 205 and the lead-out wirings 206 are connected to the conductor pads 101 disposed on the surface of the semiconductor chip 10 via the gold bumps 50, respectively. Are electrically connected to each other. Further, the conductor pads 205 of the semiconductor chip 20 are connected to the leads 41 of the lead frame 40 via the wires 30, whereby the semiconductor chip 20 and the lead frame 40 are electrically connected to each other.

　そして、本実施の形態に係る半導体装置では、インダクタ素子２０１、２０２が半導体基板よりも外側に配置されるように金バンプ５０を介して導体パッド１０１とビア２０３とを接続している。これにより、半導体チップ１０に形成されているトランジスタ、抵抗および容量などの各素子と半導体チップ２０のインダクタ素子２０１、２０２および配線２０４とを導体パッド１０１および金バンプ５０を介して電気的に接続している。 In the semiconductor device according to the present embodiment, the conductor pad 101 and the via 203 are connected via the gold bump 50 so that the inductor elements 201 and 202 are arranged outside the semiconductor substrate. Thereby, each element such as a transistor, a resistor and a capacitor formed on the semiconductor chip 10 is electrically connected to the inductor elements 201 and 202 and the wiring 204 of the semiconductor chip 20 via the conductor pad 101 and the gold bump 50. ing.

　なお、半導体チップ２０は、インダクタ素子２０１、２０２、ビア２０３、配線２０４、導体パッド２０５および引き出し配線２０６を形成後、裏面を半導体チップ１０と電気的に接続できるようビア２０３の底面が露出するまで薄膜化加工されている。 In the semiconductor chip 20, after the inductor elements 201 and 202, the via 203, the wiring 204, the conductor pad 205, and the lead wiring 206 are formed, the bottom surface of the via 203 is exposed so that the back surface can be electrically connected to the semiconductor chip 10. Thinned.

　本実施の形態において得られる効果を以下にまとめて記載する。 The effects obtained in the present embodiment are summarized below.

　本実施の形態によれば、インダクタ素子２０１、２０２は半導体基板１１よりも外側に配置されているので、インダクタ素子２０１、２０２の直下には半導体基板１１が配置されない。よって、インダクタ素子２０１、２０２とＧＮＤとの間の距離は、インダクタ素子とリードフレーム４０との間においてインダクタ素子２０１、２０２の直下に半導体基板１１が配置される場合より長くなる。従って、インダクタ素子２０１、２０２の磁界により半導体基板１１に誘起される渦電流が低減され、インダクタ素子２０１、２０２の損失が抑制される。更にインダクタ素子２０１、２０２の配線とGNDとの間の寄生容量値Cが低減されるため、自己共振周波数が高くなり、最大使用周波数が高くなる。また、並列容量成分が低減されることから、インダクタ素子２０１、２０２のQ値が向上する。 According to the present embodiment, since the inductor elements 201 and 202 are disposed outside the semiconductor substrate 11, the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202. Therefore, the distance between the inductor elements 201 and 202 and GND is longer than when the semiconductor substrate 11 is disposed directly below the inductor elements 201 and 202 between the inductor element and the lead frame 40. Therefore, the eddy current induced in the semiconductor substrate 11 by the magnetic field of the inductor elements 201 and 202 is reduced, and the loss of the inductor elements 201 and 202 is suppressed. Furthermore, since the parasitic capacitance value C between the wiring of the inductor elements 201 and 202 and GND is reduced, the self-resonance frequency is increased and the maximum usable frequency is increased. In addition, since the parallel capacitance component is reduced, the Q values of the inductor elements 201 and 202 are improved.

　更に、好ましくは、インダクタ素子２０１、２０２直下におけるリードフレーム４０に切り欠きを設けることにより、リードフレーム４０内でも渦電流の発生を抑制することが可能であると共に、インダクタ素子２０１、２０２とリードフレーム４０との間の寄生容量も低減できる。よって、Q値の更なる向上により、インダクタ素子の特性向上を達成できる。 Further, preferably, by providing a cutout in the lead frame 40 immediately below the inductor elements 201 and 202, it is possible to suppress the generation of eddy currents in the lead frame 40, and the inductor elements 201 and 202 and the lead frame Parasitic capacitance between 40 can also be reduced. Therefore, the characteristics of the inductor element can be improved by further improving the Q value.

　なお、本実施の形態によれば、インダクタ素子２０１、２０２直下に半導体チップ１０が配置されない実装レイアウトにすることで、高周波特性に優れたインダクタ素子２０１、２０２を集積化することができる。ちなみに、インダクタ素子２０１、２０２を半導体チップ１０よりも外側に配置しても、インダクタ素子２０１、２０２はリードフレーム４０よりも外側に配置されないので、パッケージを大きくする必要はない。 In addition, according to the present embodiment, the inductor elements 201 and 202 having excellent high frequency characteristics can be integrated by adopting a mounting layout in which the semiconductor chip 10 is not disposed immediately below the inductor elements 201 and 202. Incidentally, even if the inductor elements 201 and 202 are arranged outside the semiconductor chip 10, the inductor elements 201 and 202 are not arranged outside the lead frame 40, so that it is not necessary to enlarge the package.

　（実施の形態２）
　図３は、本実施の形態２における半導体装置２の構造図であり、図３（ａ）、図３（ｂ）および図３（ｃ）はそれぞれ斜視図、断面図および平面図である。 (Embodiment 2)
FIG. 3 is a structural diagram of the semiconductor device 2 according to the second embodiment. FIGS. 3A, 3B, and 3C are a perspective view, a cross-sectional view, and a plan view, respectively.

　本実施の形態２では、半導体チップ２０はインダクタ素子２０１、２０２のみが設けられたインダクタ素子の専用のチップであり、半導体チップ１０の表面の導体パッド２０５からワイヤー３０が引き出されている。それ以外の構成については、本実施の形態１と同様で、半導体チップ２０のインダクタ素子２０１、２０２の直下には半導体基板１１が配置されないように、半導体チップ２０が半導体チップ１０の上に配置されている。インダクタ素子２０１、２０２の各端子は、引き出し配線２０６およびビア２０３を介して金バンプ５０に接続されており、その金バンプ５０は半導体チップ１０の表面の周縁に配置された導体パッド２０５に接続されている。これにより、インダクタ素子２０１、２０２のスパイラル部は半導体基板１１よりも外側に配置され、インダクタ素子２０１、２０２の両端の接続配線により半導体基板１１の各素子と電気的に接続している。 In the second embodiment, the semiconductor chip 20 is a dedicated chip for the inductor element in which only the inductor elements 201 and 202 are provided, and the wire 30 is drawn from the conductor pad 205 on the surface of the semiconductor chip 10. Other configurations are the same as those in the first embodiment, and the semiconductor chip 20 is disposed on the semiconductor chip 10 so that the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202 of the semiconductor chip 20. ing. Each terminal of the inductor elements 201 and 202 is connected to the gold bump 50 through the lead wiring 206 and the via 203, and the gold bump 50 is connected to the conductor pad 205 disposed on the peripheral edge of the surface of the semiconductor chip 10. ing. As a result, the spiral portions of the inductor elements 201 and 202 are disposed outside the semiconductor substrate 11 and are electrically connected to each element of the semiconductor substrate 11 by connection wirings at both ends of the inductor elements 201 and 202.

　図４を用いて、インダクタ素子専用の半導体チップ２０の構造について説明する。図４（ａ）はインダクタ素子専用の半導体チップ２０の平面概要図で、図３に示したインダクタ素子２０１だけを抜き出して記載しており、インダクタ素子２０１は例えば樹脂材料からなる基板２００の上に設けられており、基板２００は絶縁性の材料であればセラミックのような樹脂以外の材料でも構わない。図４（ｂ）は、図４（ａ）のIVB－IVB’における断面図である。基板２００の上面上には、金属からなるインダクタ素子２０１が形成されている。インダクタ素子２０１の両端にはそれぞれ金属からなる引き出し配線２０６が接続されており、そのうち一方の引き出し配線２０６は基板２００の下面上に設けられ、貫通電極２０７を介してインダクタ素子の一方の端部に電気的に接続されている。また、基板２００の下面には、半導体チップ２０を半導体チップ１０に接続するための導体パッド１０１が形成されており、よって、この導体パッド１０１は、上記一方の引き出し配線２０６と同一面に形成されている。 The structure of the semiconductor chip 20 dedicated to the inductor element will be described with reference to FIG. FIG. 4A is a schematic plan view of the semiconductor chip 20 dedicated to the inductor element, in which only the inductor element 201 shown in FIG. 3 is extracted and described. The inductor element 201 is formed on a substrate 200 made of, for example, a resin material. The substrate 200 may be a material other than a resin such as ceramic as long as the substrate 200 is an insulating material. FIG. 4B is a cross-sectional view taken along the line IVB-IVB ′ of FIG. An inductor element 201 made of metal is formed on the upper surface of the substrate 200. Lead wires 206 made of metal are connected to both ends of the inductor element 201, one of the lead wires 206 is provided on the lower surface of the substrate 200, and is connected to one end of the inductor element through the through electrode 207. Electrically connected. In addition, a conductor pad 101 for connecting the semiconductor chip 20 to the semiconductor chip 10 is formed on the lower surface of the substrate 200. Therefore, the conductor pad 101 is formed on the same surface as the one lead wiring 206. ing.

　上記構成の半導体チップ２０の導体パッド１０１は、半導体チップ１０の表面の周縁に設けられている導体パッド２０５に、例えば金バンプ５０を介して接続される。このとき、インダクタ素子２０１、２０２を半導体チップ１０よりも外側に配置することにより、インダクタ素子２０１、２０２に電流が流れた結果、磁界が誘起されても、半導体基板１１の内部に磁界が及ぶことがない。 The conductor pad 101 of the semiconductor chip 20 configured as described above is connected to the conductor pad 205 provided on the peripheral edge of the surface of the semiconductor chip 10 via, for example, a gold bump 50. At this time, by disposing the inductor elements 201 and 202 outside the semiconductor chip 10, as a result of a current flowing through the inductor elements 201 and 202, the magnetic field reaches the inside of the semiconductor substrate 11 even if a magnetic field is induced. There is no.

　以上説明したように、本実施の形態によれば、上記実施の形態１と同じく、インダクタ素子２０１、２０２は半導体基板１１よりも外側に配置されているので、インダクタ素子２０１、２０２の直下には半導体基板１１が配置されない。よって、本実施の形態においても上記実施の形態１と同一の効果を得ることができる。 As described above, according to the present embodiment, the inductor elements 201 and 202 are arranged outside the semiconductor substrate 11 as in the first embodiment. The semiconductor substrate 11 is not disposed. Therefore, also in this embodiment, the same effect as in the first embodiment can be obtained.

　（その他の実施の形態）
　上記実施の形態１および２では、インダクタ素子において発生する磁界が半導体チップ１０を形成する半導体基板１１の主表面に対して垂直な向きになるようにインダクタ素子を設置したが、磁界が半導体基板１１の主表面に対して平行になるようにインダクタ素子を設置することもできる。すなわち、インダクタ素子は半導体基板１１の端部から側面に突き出し、インダクタ素子を構成する巻き線が半導体基板１１の主表面および突き出した側面とほぼ垂直に形成されていても良い。さらに、インダクタ素子によって誘起される磁界が半導体基板の主表面に対して平行でも垂直でもない角度に傾いて発生しても、その磁界が半導体チップに直接影響を与えることを阻止することができるので、上記実施の形態１および２と同様の効果を得ることができる。 (Other embodiments)
In the first and second embodiments, the inductor element is installed so that the magnetic field generated in the inductor element is oriented perpendicular to the main surface of the semiconductor substrate 11 forming the semiconductor chip 10. It is also possible to install the inductor element so as to be parallel to the main surface. That is, the inductor element may protrude from the end portion of the semiconductor substrate 11 to the side surface, and the windings constituting the inductor element may be formed substantially perpendicular to the main surface of the semiconductor substrate 11 and the protruding side surface. Furthermore, even if the magnetic field induced by the inductor element is generated at an angle that is neither parallel nor perpendicular to the main surface of the semiconductor substrate, the magnetic field can be prevented from directly affecting the semiconductor chip. The same effects as in the first and second embodiments can be obtained.

　また、上記実施の形態１および２では、インダクタ素子の全体を半導体基板１１よりも外側に配置することによって、磁界が半導体基板に及ぶことを抑制している。しかし、使用周波数などの半導体装置の仕様により、インダクタ素子の全体を半導体基板１１よりも外側に配置させるのではなく、少なくとも巻き線部の中心を半導体基板１１よりも外側に配置すれば、所定の効果を得ることができる。この場合にも、インダクタ素子からの磁界が及ぶ範囲は半導体チップの周辺部であるので、磁界によって誤作動を引き起こす可能性のあるトランジスタ等のレイアウトに制約がかかることを防ぐことができる。 In the first and second embodiments, the entire inductor element is disposed outside the semiconductor substrate 11 to suppress the magnetic field from reaching the semiconductor substrate. However, depending on the specifications of the semiconductor device such as the operating frequency, if the entire inductor element is not arranged outside the semiconductor substrate 11 but at least the center of the winding portion is arranged outside the semiconductor substrate 11, a predetermined value is obtained. An effect can be obtained. Also in this case, since the range covered by the magnetic field from the inductor element is the periphery of the semiconductor chip, it is possible to prevent the layout of transistors and the like that may cause malfunctions from being restricted by the magnetic field.

　さらに、本発明は、以上の実施の形態に限定されることなく、種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることは言うまでもない。例えば、インダクタ素子は１ターン以上の巻き線からなれば良く、その巻き数は特に限定されない。 Furthermore, the present invention is not limited to the above-described embodiment, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention. For example, the inductor element only needs to have one or more turns, and the number of turns is not particularly limited.

　以上のように、本発明にかかる半導体装置は、インダクタ素子の磁界により半導体基板に誘起される渦電流が低減し、インダクタ素子の損失が抑制され、インダクタ素子の配線とGNDとの間の寄生容量が低減し、最大使用周波数が高くなるという効果を有するので、高周波の半導体装置として有用である。 As described above, in the semiconductor device according to the present invention, the eddy current induced in the semiconductor substrate by the magnetic field of the inductor element is reduced, the loss of the inductor element is suppressed, and the parasitic capacitance between the wiring of the inductor element and GND is reduced. Is effective as a high-frequency semiconductor device.

　1 　　　半導体装置 
　2 　　　半導体装置 
　10　　　半導体チップ 
　11　　　半導体基板 
　20　　　半導体チップ 
　30　　　ワイヤー 
　40　　　リードフレーム 
　41　　　リード 
　50　　　金バンプ 
　101 　　導体パッド 
　200 　　基板 
　201 　　インダクタ素子 
　202　 　インダクタ素子 
　203　 　ビア 
　204 　　配線 
　205 　　導体パッド 
　206 　　引き出し配線 
　207 　　貫通電極  1 Semiconductor devices
2 Semiconductor devices
10 Semiconductor chip
11 Semiconductor substrate
20 Semiconductor chip
30 wires
40 lead frame
41 lead
50 gold bump
101 Conductor pad
200 substrates
201 Inductor element
202 Inductor element
203 Beer
204 Wiring
205 Conductor pad
206 Lead-out wiring
207 Through electrode

Claims (7)

　半導体集積回路と、前記半導体集積回路と電気的に接続されたインダクタ素子とを有し、
　前記インダクタ素子は、前記半導体集積回路を構成する半導体基板よりも外側に配置されていることを特徴とする半導体装置。 A semiconductor integrated circuit, and an inductor element electrically connected to the semiconductor integrated circuit,
The semiconductor device according to claim 1, wherein the inductor element is disposed outside a semiconductor substrate constituting the semiconductor integrated circuit. 　前記インダクタ素子の長手方向における各端に設けられた端子はどちらも、前記半導体基板に電気的に接続されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein both terminals provided at each end in the longitudinal direction of the inductor element are electrically connected to the semiconductor substrate. 　前記インダクタ素子は、１ターン以上の巻き線からなることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the inductor element comprises a winding of one turn or more. 　前記半導体基板の表面に設けられた導体パッドを有し、
　前記インダクタ素子の前記端子は、それぞれ、前記導体パッドを介して前記半導体基板に接続されていることを特徴とする請求項２に記載の半導体装置。 A conductor pad provided on the surface of the semiconductor substrate;
The semiconductor device according to claim 2, wherein each of the terminals of the inductor element is connected to the semiconductor substrate via the conductor pad. 　前記インダクタ素子は、１ターン以上の巻き線からなり、
　前記インダクタ素子の前記端子は、前記インダクタ素子の巻き中心に対して互いに同じ側に配置されていることを特徴とする請求項２に記載の半導体装置。 The inductor element comprises a winding of one turn or more,
The semiconductor device according to claim 2, wherein the terminals of the inductor element are disposed on the same side with respect to a winding center of the inductor element. 　前記インダクタ素子を複数有していることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, comprising a plurality of the inductor elements. 　複数のインダクタ素子は互いに誘導結合しないように配置されていることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the plurality of inductor elements are arranged so as not to be inductively coupled to each other.
PCT/JP2009/005557 2008-11-12 2009-10-22 Semiconductor device WO2010055614A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039924A (en) * 2002-07-04 2004-02-05 Fujitsu Ltd Semiconductor device
JP2005538560A (en) * 2002-09-10 2005-12-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Semiconductor device and method having wire bond inductor
JP2007073600A (en) * 2005-09-05 2007-03-22 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004039924A (en) * 2002-07-04 2004-02-05 Fujitsu Ltd Semiconductor device
JP2005538560A (en) * 2002-09-10 2005-12-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Semiconductor device and method having wire bond inductor
JP2007073600A (en) * 2005-09-05 2007-03-22 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same

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