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WO2010049974A1 - Dispositif d'affichage par plasma et son procédé de commande - Google Patents

Dispositif d'affichage par plasma et son procédé de commande Download PDF

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Publication number
WO2010049974A1
WO2010049974A1 PCT/JP2008/003119 JP2008003119W WO2010049974A1 WO 2010049974 A1 WO2010049974 A1 WO 2010049974A1 JP 2008003119 W JP2008003119 W JP 2008003119W WO 2010049974 A1 WO2010049974 A1 WO 2010049974A1
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WO
WIPO (PCT)
Prior art keywords
scan
potential
period
address
electrode
Prior art date
Application number
PCT/JP2008/003119
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English (en)
Japanese (ja)
Inventor
坂本哲也
高木彰浩
Original Assignee
日立プラズマディスプレイ株式会社
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Filing date
Publication date
Application filed by 日立プラズマディスプレイ株式会社 filed Critical 日立プラズマディスプレイ株式会社
Priority to PCT/JP2008/003119 priority Critical patent/WO2010049974A1/fr
Publication of WO2010049974A1 publication Critical patent/WO2010049974A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0228—Increasing the driving margin in plasma displays

Definitions

  • the present invention relates to a plasma display device and a driving method thereof.
  • the plasma display device has a plasma display panel and a drive circuit for driving the plasma display panel.
  • the plasma display panel has, for example, a plurality of X electrodes that have a phosphor and a plurality of address electrodes (A electrodes) on a back substrate, and intersect the address electrodes on a front substrate provided on the back substrate via a plasma discharge space. , Y electrodes (a pair of display electrodes) and a dielectric layer covering them.
  • a region where the A electrode and the X and Y electrodes intersect is a cell region.
  • the panel driving by the driving circuit includes a reset period in which reset discharge is generated between the X and Y electrodes, between the A and Y electrodes, and between the A and X electrodes to reset the wall charge state on each electrode to an adjusted state, An address period in which an address pulse is selectively applied to the A electrode while the scan pulse is sequentially applied to the Y electrode and the cell is selectively lit by discharging between the A and Y electrodes, and a sustain pulse between the X and Y electrodes And a sustain period in which a sustain discharge is generated in a cell that is lit in the address period.
  • the reset discharge in the reset period adjusts the wall charge on the electrode in the cell region to an ideal state, and further, priming particles (charged particles and excited particles) are formed in the discharge space. Selective discharge becomes possible.
  • the adjusted wall charge amount and the priming particles in the discharge space are reduced, and the selective discharge of the cell is less likely to occur. Therefore, it has been proposed that the difference between the address selection potential Va of the A electrode and the potential Vy of the scan pulse of the Y electrode in the second half of the address period is made larger than that in the first half of the address period. For example, as described in Patent Document 1.
  • the potential of the scan pulse of the Y electrode is controlled to a lower potential (a deeper negative potential) in the second half than in the first half of the address period.
  • the scan pulse is applied to the drive transistor of the scan circuit.
  • the voltage becomes larger. For this reason, it is necessary to increase the breakdown voltage of the drive transistor of the scan circuit, resulting in an increase in cost.
  • the pulse amplitude can be made relatively low, and the breakdown voltage of the drive transistor of the scan circuit can be lowered.
  • a weak discharge may occur between the Y electrode at the non-scan potential and the A electrode to which the address pulse is applied. is there.
  • this weak discharge occurs before the scan pulse is applied, the amount of wall charge on the electrode adjusted during the reset period changes, and it is assumed that selective discharge does not occur reliably when the scan pulse is applied. This leads to display driving.
  • an object of the present invention is to provide a plasma display apparatus that performs driving in a new address period that solves the above-described problems, and a driving method thereof.
  • the plasma display includes a plurality of address electrodes, a plurality of scan electrodes intersecting with the address electrodes, and a cell formed at the intersection of the address electrodes and the scan electrode.
  • the drive circuit maintains the scan electrode at a standby potential between the address selection potential and the scan potential during the address period, and then drives the scan electrode to a non-scan potential between the standby potential and the scan potential.
  • the non-scan potential and the scan potential are a first non-scan potential and a first scan potential, and a second period after the first period of the address period.
  • the non-scan potential and the scan potential are a second non-scan potential and a second scan potential
  • the address selection potential and the second scan potential are determined by the difference between the address selection potential and the first scan potential.
  • the difference between the address selection potential and the first non-scanning potential is larger than the difference between the address selection potential and the first non-scanning potential.
  • the drive circuit maintains the scan electrode at the standby potential from the start of the address period to immediately before the scan drive timing, and the scan electrode Is driven to the non-scanning potential immediately before the scan driving timing.
  • the drive circuit includes a plurality of first scan electrodes that are scanned in the first period, immediately before the scan drive timing from the start of the first period. And the plurality of second scan electrodes scanned in the second period are maintained at the standby potential from the start of the drive period to the start of the second period, The non-scan potential is driven from the start of the second period to immediately before the scan drive timing.
  • FIG. 1 It is structural drawing of the panel of the plasma display apparatus in this Embodiment. It is a block diagram of the drive circuit of the plasma display apparatus in this Embodiment. It is a block diagram of the drive circuit of another plasma display apparatus in this Embodiment. It is a figure which shows the outline of the drive waveform of the plasma display apparatus in this Embodiment. It is a figure which shows an example of the drive method of an address period. It is a figure which shows the drive waveform by the 1st drive method of the address period in this Embodiment. It is a figure which shows the 1st Y drive circuit in this Embodiment. 4 is a timing chart of a first Y drive circuit in the present embodiment.
  • FIG. 1 Y drive circuit in the present embodiment FIG.
  • Vb standby potential
  • Vsc1 non-scan potential
  • Vy1 scan potential
  • T1-T3 address period
  • T1-T2 first half of address period
  • T2-T3 second half of address period
  • Y1-Ym Y electrode Ym + 1-Yn: Y electrode
  • FIG. 1 is a structural diagram of a panel of a plasma display device according to the present embodiment.
  • a plurality of sets of display electrodes 11A and 11B each including a transparent electrode 11 extending in the lateral direction and a metal electrode 12 stacked thereon are formed, and a dielectric covering the display electrodes 11A and 11B.
  • a body layer 14 is formed.
  • the display electrode 11A is a sustain electrode to which a sustain pulse is applied during the sustain period
  • the display electrode 11B is a scan electrode that is driven to the scan potential during the address period.
  • a plurality of sustain electrodes 11A and scan electrodes 11B are formed on the front substrate 1 respectively.
  • a plurality of address electrodes 21 extending in the vertical direction, a dielectric layer 22 covering the address electrodes 21, a partition wall 23 surrounding the cell region, and a cell region surrounded by each partition wall
  • An inner phosphor 24 is formed on the substrate 2 on the back side.
  • the partition wall 23 has a vertical partition wall 23A extending in the vertical direction and a horizontal partition wall 23B extending in the horizontal direction. A position where the display electrodes 11A and 11B intersect with the address electrode 21 is a cell region, and the cell region is surrounded by a partition wall 23.
  • the front substrate 1 and the rear substrate 2 are disposed with a discharge space therebetween, and a discharge gas is injected into the discharge space and sealed from the outside.
  • FIG. 2 is a configuration diagram of a driving circuit of the plasma display device according to the present embodiment.
  • the plasma display panel PNL includes a plurality of sustain electrodes (X electrodes) X, a plurality of scan electrodes (Y electrodes) Y1 to Yn, and a plurality of address electrodes (A electrodes) intersecting with these electrodes. ) A1 to Ak. Then, cells C11 to Ckn are respectively provided at the positions where the scan electrodes Y1 to Yn and the sustain electrode X intersect the address electrodes A1 to Ak.
  • the sustain electrode X is connected to the X drive circuit XDR, the scan electrodes Y1 to Yn are connected to the Y drive circuit YDR, and the address electrodes A1 to Ak are connected to the address electrode drive circuit ADR.
  • the control circuit CON receives a data signal DATA, a synchronization clock CLOCK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC from a tuner or a reproduction circuit (not shown), and an X drive circuit XDR, a Y drive circuit YDR, A drive control signal is supplied to the address electrode drive circuit ADR.
  • the Y drive circuit YDR has a Y drive circuit and a scan circuit.
  • the Y drive circuit YDR is disposed below the panel PNL, the drive circuit 31 and the scan circuit 32 that drive the scan electrodes Y1 to Ym-1 disposed above the panel PNL among the plurality of scan electrodes Y.
  • the drive circuit 33 and the scan circuit 34 drive the scan electrodes Ym to Yn.
  • the scan circuit 32 sequentially drives the scan electrodes Y1 to Ym-1 to the scan potential, and subsequently, the scan circuit 34 sequentially drives the scan electrodes Ym to Yn to the scan potential.
  • the scan of the scan electrode is performed in order line-sequentially from the top to the bottom of the panel PNL.
  • the drive circuits 31 and 33 of the X drive circuit XDR and the Y drive circuit YDR reset the sustain electrode X and the scan electrode Y during the reset period, and further, sustain pulses are applied to the sustain electrode X and the scan electrode Y during the sustain period. Are applied alternately.
  • the scan circuits 32 and 34 drive the scan electrodes Y to the scan potential line-sequentially during the address period.
  • the address electrode drive circuit ADR drives the address electrodes A1 to Ak to the address selection potential according to the data to be displayed in synchronization with the scan drive timing of the scan electrode Y in the address period.
  • FIG. 3 is a configuration diagram of a driving circuit of another plasma display device according to the present embodiment.
  • the structure of the panel PNL, the X drive circuit XDR, the address drive circuit ADR, and the control circuit CON are the same as those in FIG.
  • interlaced scanning is performed in the address period. Therefore, the drive circuit 31 and the scan circuit 32 of the Y drive circuit YDR sequentially drive the odd-numbered scan electrodes, and then the drive circuit 33 and the scan circuit 34 The even-numbered scan electrodes Y are sequentially driven. Even if the even number is sequentially driven first, and then the odd number is sequentially driven, the interlace scanning can be similarly performed.
  • FIG. 4 is a diagram showing an outline of a driving waveform of the plasma display device in the present embodiment.
  • a subfield including a reset period Reset, an address period Address, and a sustain period Sustain is repeated.
  • a reset period while maintaining the A electrode at a reference voltage, for example, ground, a negative pulse that gradually decreases from the ground to the negative potential Vxn is applied to the X electrode, and the potential from the ground gradually increases to the Y electrode.
  • a positive reset pulse is applied which rises to reach the positive potential Vyp.
  • a weak discharge is repeatedly generated between Y and X, and the positive wall on the X electrode is determined from the state of the negative wall charge on the X electrode and the positive wall charge on the Y electrode in the last sustain period. Charge and negative wall charge on the Y electrode. Subsequently, in the reset period, the X electrode is driven to the positive potential Vxp to apply a positive pulse, and a negative pulse that gradually decreases from the ground to the negative potential Vyn is applied to the Y electrode. .
  • a weak discharge is repeatedly generated between X and Y, the amount of wall charges on the X and Y electrodes is adjusted, and priming particles are formed in the discharge space of the cell.
  • a pulse of the negative potential Vy is sequentially applied to the Y electrode, which is the scan electrode, and in synchronization therewith, a pulse of the address selection potential Va is applied to the A electrode according to display data.
  • a pulse of the address selection potential Va is applied to the A electrode to be lit, and the A electrode that is not to be lit is maintained at the ground potential of the address non-selection potential.
  • an address discharge between A and Y occurs in the cell at the intersection of the Y electrode to which the scan pulse is applied and the A electrode to which the address selection pulse is applied.
  • a discharge is generated between X and Y by being induced by the address discharge between A and Y.
  • a negative wall charge and a positive wall charge are formed on the X and Y electrodes of the cell in which discharge has occurred.
  • the scan pulse of the negative potential Vy is applied after the Y electrode is once driven to the non-scan potential Vsc.
  • the voltage applied to the switch for applying the scan pulse of the negative potential Vy that is, the MOS transistor can be set to Vsc ⁇ Vy.
  • the voltage applied to the MOS transistor can be lowered. As a result, the breakdown voltage of the MOS transistor can be reduced.
  • a scan pulse Ps of the scan potential Vs is applied to the Y electrode while negative wall charges and positive wall charges are respectively formed on the X and Y electrodes of the cell.
  • X generates a sustain discharge.
  • a scan pulse Ps having a scan potential Vs is applied to the X electrode, and a sustain discharge is generated between X and Y.
  • a sustain pulse Ps is alternately applied to the Y and X electrodes to repeatedly generate a sustain discharge. The phosphor emits light by this sustain discharge, and a desired display is performed.
  • the emission brightness of each cell is a value corresponding to the number of sustain pulses. Therefore, the light emission luminance in the subfield period is controlled according to the number of sustain pulses in the sustain period in the subfield period in FIG. 4, and a desired luminance display is performed by combining a plurality of subfields having different sustain periods.
  • FIG. 5 is a diagram illustrating an example of a driving method in the address period.
  • the Y electrode is scanned in the line sequential manner shown in FIG.
  • the driving method of FIG. 5 similarly to FIG. 4, the Y electrode which is a scan electrode is once driven to the non-scan potential Vsc in the address period, and the scan electrode Vy is set to the Y electrode at the timing of applying the scan pulse. Apply.
  • the wall charges on the X and Y electrodes and the state of the priming particles in the discharge space are reduced in the second half compared to the first half of the address period. Therefore, it is necessary to control the difference Va ⁇ Vy between the address selection potential Va and the scan potential Vy so that the latter half becomes larger than the first half of the address period.
  • the scan potential Vy needs to be lower (deep negative potential) in the second half than in the first half of the address period.
  • the scan potential Vy1 of the Y electrode Yf of the electrodes Y1 to Ym scanned in the first half of the address period (time T1 to T2) is more than the electrodes Ym + 1 to scan scanned in the second half of the address period (time T2 to T3).
  • the scan potential Vy2 of the Y electrode Ys of Yn is a lower potential (deep negative potential). That is, Va ⁇ Vy1 ⁇ Va ⁇ Vy2.
  • Vsc1-Vy1 Vsc2-Vy2. Accordingly, the non-scan potential Vsc of the Y electrode Ys scanned in the second half is lower than the non-scan potential Vsc of the Y electrode Yf scanned in the first half (deep negative potential). That is, Va ⁇ Vsc1 ⁇ Va ⁇ Vsc2.
  • the pulse of the address selection potential Va is applied to the A electrode in synchronization with the application of the scan pulses of the scan potentials Vy1 and Vy2 to the Y electrode. Therefore, the address discharge is not generated by the difference voltage between the address selection potential Va and the non-scan potentials Vsc1 and Vsc2, but the address discharge is generated by the difference voltage between the address selection potential Va and the scan potentials Vy1 and Vy2. Potentials Vsc1 and Vsc2 are set.
  • Va ⁇ Vsc1 ⁇ Va ⁇ Vsc2 is set. Therefore, in the Y electrode Ys scanned in the second half of the address period, a weak discharge is generated between the Y electrode of the non-scan potential Vsc2 and the address electrode of the address selection potential Va before and after the scan pulse is applied. It becomes easy to do. The occurrence of this weak discharge is also possible in the Y electrode Yf scanned in the first half of the address period. This weak discharge is a false discharge, which hinders display control.
  • the amount of wall charges on the X and Y electrodes adjusted in the reset period changes, specifically, the adjusted negative wall on the Y electrode. In some cases, the amount of charge decreases and address discharge does not occur normally when a reset pulse is applied thereafter. This causes display defects.
  • FIG. 6 is a diagram showing a driving waveform by the first method in the address period in the present embodiment.
  • FIG. 6 shows the drive waveform of the A electrode in the address period, the drive waveform of the Y electrode Yf scanned in the first half (time T1 to T2) and the Y electrode Ys scanned in the second half (time T2 to T3). It is shown.
  • Y electrodes Yf scanned in the first half are Y1 to Ym
  • Y electrodes Ys scanned in the second half are Ym + 1 to Yn.
  • the Y electrode Yf scanned in the first half is an odd-numbered Y electrode
  • the Y electrode Ys scanned in the second half is an even-numbered Y electrode.
  • the drive waveforms of the Y electrode Yf scanned in the first half of the address period (time T1 to T2) and the Y electrode Ys scanned in the second half (time T2 to T3) are the scan potentials Vy1 and Vy2.
  • the potentials Vsc1 and Vsc2 are different. That is, as in FIG. 5, Va ⁇ Vy1 ⁇ Va ⁇ Vy2 is set, and Va ⁇ Vsc1 ⁇ Va ⁇ Vsc2 is set. That is, Vy1> Vy2 and Vsc1> Vsc2 are set.
  • the Y electrode is maintained at the standby potential Vb between the address selection potential Va and the scan potentials Vy1 and Vy2 from the start of the address period to just before the scan pulse Psc drive timing, and then the scan pulse.
  • the non-scan potentials Vsc1 and Vsc2 are driven.
  • the Y electrode is driven to the standby potential Vb at T3.
  • the standby potential Vb may be a potential between the address selection potential Va and the non-scan potential Vsc, and is a ground potential, for example.
  • the Y electrode may be returned to the standby potential Vb via the non-scan potentials Vsc1 and Vsc2 after the scan pulse drive timing.
  • the Y electrode is maintained at the standby potential Vb higher than the non-scan potentials Vsc1 and Vsc2 instead of the non-scan potential from the start of the address period to immediately before the scan pulse drive timing. Therefore, Va ⁇ Vb ⁇ Va ⁇ Vsc1 and 2, and it is possible to suppress or avoid the occurrence of weak discharge between the A electrode and the Y electrode of the address selection potential Va in a period before the scan pulse driving timing. Therefore, the selective discharge when the scan pulse is applied can be generated normally.
  • the Y electrode is once driven to the non-scan potentials Vsc1 and Vsc2 immediately before the scan pulse drive timing, and then driven to the scan potentials Vy1 and Vy2 at the scan pulse drive timing, it is applied to the transistors in the scan circuit. Can be suppressed.
  • the time T2 does not necessarily need to be an intermediate time between the times T1 and T3, and may be set earlier or later than the intermediate time between the times T1 and T3 depending on the characteristics of the panel.
  • the Y electrode Yf driven in the first half of the address period may be driven to the non-scan potential Vsc1 as shown in FIG. 5 at the start of the address period.
  • the Y electrode Ys driven in the second half of the address period is maintained at the standby potential Vb from the disclosure of the address period until just before the scan driving timing. Since Va ⁇ Vsc1 ⁇ Va ⁇ Vsc2, the weak discharge between the Y electrode Ys and the A electrode driven in the second half is generated rather than the weak discharge between the Y electrode Yf and the A electrode driven in the first half. This is because the possibility is high.
  • FIG. 7 is a diagram showing a first Y drive circuit in the present embodiment.
  • the Y drive circuit YDR is a circuit that performs the first drive method of FIG. 6 and corresponds to line sequential scanning.
  • the Y drive circuit controls the switch group SW on and off to connect the plurality of power supplies Vb, Vsc1, and Vy1 to the Y electrode Yf, and controls the switch group SW on and off to control the plurality of power supplies Vb, Vsc2, and Vy2. Is connected to the Y electrode Ys.
  • the Y electrode Y1 is driven to the power source Vsc1 by the on state of the switch SW11, and is driven to the power source Vb or Vy1 by the on state of the SW21.
  • the remaining Y electrodes Y2 to Ym are driven to the power supply Vsc1 when the switch SW12 is turned on, and are driven to the power supply Vb or Vy1 when the switches SW22 and SW82 are turned on.
  • the node n1 is connected to the power source Vb when the switches SW6 and SW51 are on, and is connected to the power source Vy1 when the switch SW31 is on.
  • the Y electrode Ym + 1 is driven to the power supply Vsc2 by the ON state of the switch SW13, and is driven to the power supply Vb or Vy2 by the ON state of the SW23.
  • the remaining Y electrodes Ym + 1 to Yn are driven to the power supply Vsc2 when the switch SW14 is turned on, and are driven to the power supply Vb or Vy2 when the switches SW24 and SW84 are turned on.
  • the node n2 is connected to the power source Vb when the switches SW6 and SW52 are on, and is connected to the power source Vy2 when the switch SW32 is on.
  • the switches SW11, SW12, SW13, and SW14 are required to cut off the bidirectional current path when the switches are off.
  • Other switches are composed of a power MOS transistor in which a parasitic diode is formed between the source and drain. That is, only the current path in one direction is blocked.
  • the power source Vs and the switch SW7, and the power source Vb and the switch SW6 in FIG. 7 constitute a Y drive circuit that applies the ground potential Vb and the sustain pulse potential Vs to the Y electrode during the sustain period. Other than that constitutes a scan circuit. Then, the switches SW1 * and SW2 * surrounded by broken lines become scan drivers that drive the Y electrodes.
  • FIG. 8 is a timing chart of the first Y drive circuit in the present embodiment.
  • the switch SW6 is always on and SW7 is always off.
  • the switches SW51 and SW52 are turned on and the nodes n1 and n2 are set to the standby potential Vb.
  • the switches SW21, SW22, and SW82 are turned on and the Y electrodes Yf (Y1 to Ym) are driven to the standby potential Vb.
  • the switches SW23, SW24, and SW84 are turned on and the Y electrode Ys (Ym + 1 to Yn) are also driven to the standby potential Vb.
  • the switches SW21, SW22, SW82, and SW51 are turned off.
  • Y2 to Ym (typically Ym) other than Y1 of the Y electrode Yf are maintained at the standby potential Vb until time t4 immediately before the scan drive. Thereafter, similarly to Y1, SW12 is turned on at time t4 and the Y electrode Ym is driven to the non-scan potential Vsc1, and SW12 is turned off and SW22 and SW82 are turned on at the time t5 immediately after the scan drive. The electrode Ym is driven to the scan potential Vy1. At time t6, SW22 and SW82 are turned off, SW12 is turned on, and the Y electrode Ym is driven to the non-scan potential Vsc1.
  • the switch SW82 is turned off from time T1 to t5, and disconnects the scan driver SW22 of the Y electrodes Y2 to Ym maintained at the standby potential Vb from the node n1 that is set to the non-scan potential Vsc1. Therefore, the switch SW82 is required for the Y electrodes Y2 to Ym other than the Y electrode Y1.
  • Ym + 2 to Yn (typically Yn) other than Ym + 1 of the Y electrode Ys are maintained at the standby potential Vb until time t10 immediately before the scan drive. Then, similarly to Ym + 1, SW14 is turned on at time t10 and the Y electrode Yn is driven to the non-scan potential Vsc2, and SW14 is turned off and SW24 and SW84 are turned on at time t11 immediately after the scan drive. The electrode Yn is driven to the scan potential Vy2. At time t12, SW24 and SW84 are turned off, SW14 is turned on, and the Y electrode Yn is driven to the non-scan potential Vsc2.
  • the switch SW84 is turned off from time T2 to t11, and disconnects the scan driver SW24 of the Y electrodes Ym + 2 to Yn maintained at the standby potential Vb from the node n2 that is set to the non-scan potential Vsc2. Therefore, the switch SW84 is provided for the Y electrodes Ym + 2 to Yn other than the Y electrode Ym + 1.
  • FIG. 9 is a diagram showing a driving waveform according to the second driving method in the address period in the present embodiment. Also in the second driving method, Va ⁇ Vy1 ⁇ Va ⁇ Vy2 is set, and Va ⁇ Vsc1 ⁇ Va ⁇ Vsc2 is set similarly to the first driving method in FIGS.
  • the Y electrode Yf driven in the first half T1 to T2 of the address period is driven to the non-scan potential Vsc1 at time T1, driven to the scan potential Vy1 at each scan drive timing, and the scan drive ends. Thereafter, it is driven again to the non-scanning potential Vsc1.
  • the Y electrode Ys driven in the second half of the address period T2 to T3 is maintained at the standby potential Vb from the time T1 to T2 in the first half of the address period, and is driven to the non-scan potential Vsc1 at the time T2. It is driven to the scan potential Vy2 at the timing, and again driven to the non-scan potential Vsc2 after the end of the scan drive.
  • the Y electrode Yf driven in the first half of the address period is not maintained at the standby potential Vb until just before the timing of the scan driving, and the non-period from the start of the address period T1.
  • Va ⁇ Vsc2 since Va ⁇ Vsc2 is relatively large, the Y electrode Ys driven in the second half of the address period is maintained at the standby potential Vb for at least the first half T1 to T2, and is driven to the non-scan potential Vsc2 from time T2.
  • the weak discharge between the Y electrode Ys driven in the second half of the address period and the A electrode in the first half of the address period is suppressed or avoided. Therefore, the generation of weak discharge can be suppressed as a whole.
  • FIG. 10 is a diagram showing a second Y drive circuit in the present embodiment.
  • this Y drive circuit YDR with respect to the configuration different from the first Y drive circuit of FIG. 7, the switches SW82 and SW84 provided in the scan drivers other than the Y electrodes Y1 and Ym + 1 are not provided.
  • SW12, SW13, and SW14 do not need to be bi-directionally cut off as long as they can be cut off from Vsc1, Vsc2 in the Y electrode direction. The reason will be described in the following explanation of the operation.
  • the second driving method it is possible to reduce the circuit cost by reducing the switches of the Y driving circuit.
  • FIG. 11 is a timing chart of the second Y drive circuit in the present embodiment.
  • the times T1, T2, and T3 in FIG. 11 and t1 to t12 excluding the times t4 and t10 are the same as those in FIG.
  • differences from the first driving method of FIG. 9 will be described.
  • the state before the address period start time T1 is the same as in the first driving method, and all the Y electrodes are driven to the standby potential Vb by turning on the switches SW21, 22, 23, and 24. These switches are turned off at time T1.
  • any Y electrode is not driven to the scan potentials Vy1 and Vy2 while the Y electrodes Yf and Ys are maintained at the standby potential Vb. That is, the switch SW32 that connects Vsc2 to the node n2 is turned on only after time t8 after the Y electrodes Ys are all driven to Vsc2. Therefore, the switches SW82 and SW84 for separating the nodes n1 and n2 and the scan driver in FIG. 7 are not necessary in the drive circuit in FIG.
  • the address discharge is reliably generated between the A electrode of the address selection potential Va and the Y electrode of the scan potential Vy2 even in the latter half of the address period. Can do.
  • the weak discharge of the Y electrode Ys scanned in the second half of the address period is suppressed or avoided in the first half. Thereby, the subsequent address discharge can be performed more reliably.
  • the plasma display device and the driving method thereof according to the present invention can perform stable display driving.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

Selon l'invention, dans un dispositif d'affichage par plasma, un circuit de commande maintient un potentiel d'une électrode de balayage (Y) à un potentiel de repos (Vb) entre un potentiel de sélection d'adresse (Va) et des potentiels de balayage (Vy1, Vy2) dans une période d'adresse. Après cela, il est commandé vers des potentiels de non balayage (Vsc1, Vc2) entre le potentiel de repos (Vb) et les potentiels de balayage (Vy1, Vy2) une fois, il est commandé vers les potentiels de balayage (Vy1, Vy2) à la temporisation de la commande de balayage, et il est commandé vers les potentiels de non-balayage ou le potentiel de repos après la temporisation de la commande de balayage. Va – Vy2 dans une seconde période après une première période est supérieur à Va – Vy1 dans la première période de la période d'adresse et Va – Vsc2 est supérieur à Va – Vsc1.
PCT/JP2008/003119 2008-10-30 2008-10-30 Dispositif d'affichage par plasma et son procédé de commande WO2010049974A1 (fr)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1165516A (ja) * 1997-08-18 1999-03-09 Hitachi Ltd プラズマディスプレイパネルの駆動方法および駆動装置
JP2000293136A (ja) * 1999-04-07 2000-10-20 Nec Corp プラズマディスプレイパネルの駆動方法及び駆動装置
JP2001183999A (ja) * 1999-12-22 2001-07-06 Nec Corp プラズマディスプレイパネル及びそれを有するプラズマディスプレイ装置
JP2001255848A (ja) * 2000-03-13 2001-09-21 Fujitsu Ltd Ａｃ型ｐｄｐの駆動方法および駆動装置
JP2002140032A (ja) * 2000-11-02 2002-05-17 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動方法
JP2003015602A (ja) * 2001-06-29 2003-01-17 Fujitsu Ltd Ａｃ型ｐｄｐの駆動方法および駆動装置
JP2003255891A (ja) * 2002-03-06 2003-09-10 Lg Electronics Inc プラズマディスプレーパネルの駆動方法及び装置
JP2003345292A (ja) * 2002-05-24 2003-12-03 Fujitsu Hitachi Plasma Display Ltd プラズマディスプレイパネルの駆動方法
JP2006139285A (ja) * 2004-11-10 2006-06-01 Lg Electronics Inc プラズマディスプレイ装置及びその駆動方法
JP2007249207A (ja) * 2006-03-14 2007-09-27 Lg Electronics Inc プラズマディスプレイ装置の駆動方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1165516A (ja) * 1997-08-18 1999-03-09 Hitachi Ltd プラズマディスプレイパネルの駆動方法および駆動装置
JP2000293136A (ja) * 1999-04-07 2000-10-20 Nec Corp プラズマディスプレイパネルの駆動方法及び駆動装置
JP2001183999A (ja) * 1999-12-22 2001-07-06 Nec Corp プラズマディスプレイパネル及びそれを有するプラズマディスプレイ装置
JP2001255848A (ja) * 2000-03-13 2001-09-21 Fujitsu Ltd Ａｃ型ｐｄｐの駆動方法および駆動装置
JP2002140032A (ja) * 2000-11-02 2002-05-17 Matsushita Electric Ind Co Ltd プラズマディスプレイパネルの駆動方法
JP2003015602A (ja) * 2001-06-29 2003-01-17 Fujitsu Ltd Ａｃ型ｐｄｐの駆動方法および駆動装置
JP2003255891A (ja) * 2002-03-06 2003-09-10 Lg Electronics Inc プラズマディスプレーパネルの駆動方法及び装置
JP2003345292A (ja) * 2002-05-24 2003-12-03 Fujitsu Hitachi Plasma Display Ltd プラズマディスプレイパネルの駆動方法
JP2006139285A (ja) * 2004-11-10 2006-06-01 Lg Electronics Inc プラズマディスプレイ装置及びその駆動方法
JP2007249207A (ja) * 2006-03-14 2007-09-27 Lg Electronics Inc プラズマディスプレイ装置の駆動方法

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