WO2009109587A1

WO2009109587A1 - Semiconductor device

Info

Publication number: WO2009109587A1
Application number: PCT/EP2009/052522
Authority: WO
Inventors: Yong Hai Hu; Elizabeth Ching Tee Kho; Zheng Chao Liu; Michael Mee Gouh Tiong; Jian Liu; Kia Yaw Kee; William Siang Lim Lau
Original assignee: X-Fab Semiconductor Foundries Ag
Priority date: 2008-03-03
Filing date: 2009-03-03
Publication date: 2009-09-11

Abstract

A Voltage-Adaptor capable of converting an externally supplied high voltage connected e.g. to the drain of a MOS or other semiconductor device to a lower voltage. The device comprises a first structure (225) comprising an at least partially conducting material, the voltage adaptor being arranged to influence a first voltage at a portion of a second structure (222) comprising a semiconductor material such that the first voltage at said portion of the second structure is different from a second voltage applied to the second structure, wherein the first structure is arranged to be connected to a bias voltage, and the voltage adaptor further comprises an insulating material (155) arranged to separate the first and second structures.

Description

SEMICONDUCTOR DEVICE

The present invention relates to semiconductor devices. It can be applied for example to transistors. It finds particular application in high voltage devices wherever mixed power supplies are available, such as in automotive or off-line switching power supplies. They can be used in sensing high voltages, and thus used in controllers, sensors and other monitoring and controlling applications.

Embodiments of the present invention relate to a PN junction device where high voltages are applied. More particularly, some embodiments of the present invention relate to a metal oxide semiconductor field effect transistor (MOSFET) which has an extended breakdown voltage between Drain and Source (BVds) in an otherwise standard complementary MOS (CMOS) process using high voltage laterally diffused MOSFETs (HV LDMOS).

Complementary MOS (CMOS) technologies are well known. By incorporating reduced surface field (RESURF) technology and laterally diffused MOS (LDMOS) architecture, the maximum operating voltage has been extended to around 70V in an otherwise standard CMOS device. Such high voltages are used in charge pumps, programming non-volatile memory circuits, on-chip LCD (liquid crystal display) display drivers, on- chip field emission display drivers, and the like. High voltages are also of increasing importance for applications in automotive electronics for Smart Power ICs. Current technology based on standard CMOS processes is limited to voltage extension (BVds<80V) applications.

A typical LDNMOS 5 cross-section is shown in Fig. 1. LDNMOS 5 is fabricated in a p- substrate 10. A first p- doped layer is formed as HV Pwell 21 , and an n doped layer is disposed inside the Pwell forming an HV n Drift region 22. The drain 25 is formed by an n+ doped active area formed inside the HV n Drift 22; drain 25 is laterally separated from the channel by a high voltage, shallow trench isolation oxide (STI) 132, and the drain 25 then connects to the metal 1 12 through a salicided layer 118 and tungsten plug 115. The HV-LDNMOS Source 23 is also formed by an n+ doping inside the HV- PWeII 21 ; the source 23 is laterally connected from the channel by an n-doped lightly doped drain (LDD) 24, and then connected to the metal inter-connection 102 through salicided layer 108 and tungsten plug 105. The HV-LDNMOS channel is defined between LDD 24 and Drift 22 under n-doped poly 27. A gate oxide layer 152 is grown between the poly 27 and silicon (Pwell 21 ) in order to form a MOS gate construction. In building the device, L-shaped spacers are formed on the left 142 and right 145 sides of the polysilicon 27. The LDNMOS has a p+ doped active area 26 to form a pick-up contact to the HV-Pwell 21 , and it connects to metal inter-connection 122 through salicided layer 128 and tungsten plug 125. Between the n+ Drain 25 and HV-Pwell Pickup 26 there is another STI 135 for isolation. The poly gate 27 is also connected to metal but this is not shown in the cross-section. All tungsten plugs are encapsulated by the inter metal dielectric layer (IMD) 155 for isolation.

The present inventors have appreciated that problems may occur if a transistor (or other semiconductor device) is to be operated with a voltage which would normally not be suitable for the transistor or other semiconductor device, for example a voltage which would normally damage the device. Such a situation could arise for example if the device is to be operated on the same chip as some other device operated at the higher voltage. The present invention aims to address this problem.

Aspects of the present invention are set out in the claims.

In embodiments of the present invention an additional lightly doped poly layer is electrically extended from the MOS drain; this lightly doped poly plate forms a SOI- RESURF structure. An additional poly or metal field plate is provided and normally also a dielectric material, such as a normal inter-layer dielectric oxide, deposited therebetween. This SOI construction (hereafter Voltage-Adaptor) can sustain a voltage drop from an externally applied voltage to the MOS Drain for both "on" and "off" states, enabling higher voltages to be used for MOS device applications than would otherwise be the case. Fabrication of the Voltage Adaptor can be achieved with a minimum of additional process steps based on a standard process flow.

The invention can be applied to NMOS and PMOS transistors but also to other semiconductor devices (including devices other than transistors).

Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: Fig. 1 is a cross-sectional view of a known LDNMOS device combining RESURF technology and laterally diffused construction.

Fig. 2-a is a cross-sectional view of an LDNMOS with one form of a vertical Voltage- Adaptor extended from the MOS drain according to a first embodiment of the present invention.

Fig. 2-b is a cross-sectional view of an LDNMOS with a poly-insulator-poly (PIP) Voltage-Adaptor extended from the MOS drain according to a second embodiment of the present invention.

Fig. 2-c is a cross-sectional view of an LDNMOS with a poly/IMD/metal1 Voltage- Adaptor extended from the MOS drain according to a third embodiment of the present invention.

Fig. 2-d is a cross-sectional view of an LDNMOS with a poly^*/IMD/metal2 Voltage- Adaptor extended from the MOS drain, where poly^* is independently formed after Tungsten plug Chemical Mechanical Polishing (CMP) according to a fourth embodiment of the present invention.

Fig. 3-a is a cross-sectional view of an LDPMOS with one form of a vertical Voltage- Adaptor extended from the MOS drain similar to the first embodiment of the present invention.

Fig. 3-b is a cross-sectional view of an LDPMOS with a PIP Voltage-Adaptor extended from the MOS drain similar to the second embodiment of the present invention.

Fig. 3-c is a cross-sectional view of an LDPMOS with a poly/IMD/metal1 Voltage- Adaptor extended from the MOS drain similar to the third embodiment of the present invention.

Fig. 3-d is a cross-sectional view of an LDPMOS with a poly^*/IMD/metal2 Voltage- Adaptor extended from the MOS drain, where poly^* is independently formed after Tungsten plug CMP similar to the fourth embodiment of the present invention. Table A contains a list of elements used in the drawings including possible specifications. These specifications indicate preferred values but are not to be regarded in a restrictive sense.

Fig. 2-a shows a cross-section of an integrated device in accordance with a first embodiment of the invention. This figure shows an HV LDNMOS transistor 5 and a Voltage-Adaptor 6a. The transistor 5 (without Voltage Adaptor 6a) is substantially similar to the transistor shown in Fig. 1. Voltage-Adaptor 6a has a structure 222 forming an n-type poly Drain extension 222, which connects to the LDNMOS n+ Drain 25 through HV drain cobalt salicidation layer 118 (HV drain Co Salicidation layer 1 18 and HV n+ Drain 25 can be omitted in a variant so that n-poly Drain extension 222 contacts directly to the HV n Drift 22). The n-poly Drain extension 222 extends generally perpendicular to the substrate. A structure 225 forming an HV p+ poly Field- plate 225 is arranged substantially parallel to n-poly extension 222. An Inter-Metal Dielectric (IMD) 155 (formed e.g. by a deposition process) is used to fill the space between n-poly extension 222 and p+ poly Field plate 225, as well as the area laterally surrounding these, so as to form an SOI structure. An HV drain Metal inter-connection 1 12 connects to HV n+ Drain 25 through n-poly extension 222. A Metal inter- connection 288 is connected to HV p+ poly Field-plate 225 for biasing the lightly-doped n-poly RESURF region.

In use, a voltage (which may be a high voltage) is applied to Drain Metal interconnection 1 12. This high voltage could be one which would normally damage the device (i.e. if the device did not have the Voltage Adaptor 6a). However, a bias voltage of opposite polarity to the high voltage is applied to contact 288, which creates a field across dielectric 155 between p+poly field plate 225 and n-poly extension 222, modifying the distribution of charges in the semiconductor material, and creating a channel in Drain extension 222. This channel limits the current through the Drain extension 222 and thus ensures that the voltage at a bottom portion of Drain extension 222 (near HV drain cobalt salicidation layer 1 18) is lower than at the top portion (near drain Metal inter-connection 1 12 - sufficiently low so that it does not damage the device). Hence it can be seen that the Voltage Adaptor 6a can be used to couple devices, such as transistors, to higher voltages than would normally be possible. Fig. 2-b shows a second embodiment with an alternative construction for Voltage- Adaptor 6b as a poly-insulator-poly (PIP) scheme. An n-polysilicon extension 222 is formed on top of, and substantially parallel to, an STI field region 135a, with an isolated HV Nwell 61 formed underneath. A dielectric layer 282 is then formed (directly) on top of n-polysilicon extension 222, followed by HV p+ polysilicon Field-plate 225 stacked on the dielectric layer. One end of n-polysilicon extension 222 connects via Tungsten (W) plug 283 to Metal inter-connection 287, and then via Tungsten (W) plug 1 15 to MOS device drain active 25. Another end of n-poly extension 222 connects to HV drain Metal inter-connection 112 via Tungsten (W) plug 283a. A Metal inter-connection 288 connects to HV p+ poly Field-plate 225 via Tungsten (W) plug 286.

Distance L1 is chosen such that HV Nwell 61 is isolated from HV n-poly drain extension 222. L1 is chosen so that the device does not have a low breakdown voltage. Typically this distance might be about 1 micrometer.

In this embodiment, HV p+ poly Field-plate 225 is oriented substantially parallel to n- poly extension 222, which in turn is oriented substantially parallel to the substrate.

Another embodiment of a Voltage-Adaptor 6c is shown in Fig 2-c - a variant of 6b. Instead of having a HV Field-plate 225 made from polysilicon, it has a Metal Field-plate 285 covering, overlaying, or overlapping with, the HV n-poly drain extension 222, with IMD 155 as a dielectric in-between, resulting in a SOI construction. The material, position and/or size of the HV n-poly drain extension 222 may be the same as in Fig. 2- b.

Another embodiment of a Voltage-Adaptor 6d is shown in Fig 2-d. It has an interlayer n-poly 228 formed independently after IMD 155 as a drain extension. The interlayer n- poly 228 has one end connected to MOS device drain 25 via Tungsten (W) plug 115 and Cobalt (Co) Salicidation layer 1 18, while it has another end linked to HV drain Metal inter-connection 1 12 via Tungsten (W) plug 283. Metal Field-plate 285 covers, overlays, or overlaps with interlayer n-Poly 228 with IMD 155 in-between to result in a SOI construction. Interlayer n-Poly 228 may be substantially midway between STI field region 135 and the surface of the semiconductor (near Metal Field-plate 285). A field created by the bias voltage applied to Metal Field-plate 285 creates a channel in interlayer n-Poly 228 to reduce the voltage applied to Metal inter-connection 112 for the purpose of supplying it to drain active 25.

As shown in Fig 3a, HV LDPMOS transistor 8 has a similar construction compared to HV LDNMOS transistor 5 shown in Fig. 2a. It is formed with HV Nwell 51 , p-drift 52, p+

Source 53, p-doped LDD 54, p+ Drain 55, n+ doped well Pickup 56 and p-doped Poly gate 57, instead of components 21 , 22, 23, 24, 25, 26 and 27 in HV LDNMOS transistor 5 respectively. HV LDPMOS 8 has four variants embodying LDPMOS

Voltage-Adaptors 9a, 9b, 9c and 9d as shown in Figs 3a, 3b, 3c and 3d . In these cases the Drain extension 252 is p-doped and interlayer Poly 258 is also p-doped, while the poly Field-plate 255 is n+ doped.

In addition to distance L1 , the voltage to be sustained depends on distance L2 (Figs. 3- b and 3-c), which isolates Nwell 61 and HV Nwell 51.

In the above discussion, the invention has been demonstrated with respect to its application with transistors. The skilled person will appreciate that the voltage adaptor could be used with many semiconductor devices, as part of a larger integrated circuit, or on its own. The voltage adaptor pursuant to this invention may also be put into effect as a separate component, which may then be attached to a semiconductor device such as a transistor.

Whilst in the above embodiments the Voltage adaptor is connected to the drain, it is equally possible to provide a Voltage adaptor for the source, gate or any other part of the transistor. Likewise, the application of the present invention to transistors is not limited to MOSFETs but can be extended to other types of transistors such as bipolar transistors or FETs.

The present invention may be embodied using various topological shapes, such as a square or a rounded shape for example.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed.

Table A:

Claims

CLAIMS:

1. A voltage adaptor comprising a first structure comprising an at least partially conducting material, the voltage adaptor being arranged to influence a first voltage at a portion of a second structure comprising a semiconductor material such that the first voltage at said portion of the second structure is different from a second voltage applied to the second structure, wherein the first structure is arranged to be connected to a bias voltage, and the voltage adaptor further comprises an insulating material arranged to separate the first and second structures.

2. The adaptor of claim 1 , wherein the first structure comprises a terminal for connecting the bias voltage to the first structure.

3. The adaptor of any preceding claim, wherein the first structure comprises an electrical conductor.

4. The ada ptor of clai m 1 or 2, wherein the first structure comprises a semiconductor material.

5. The adaptor of claim 4, wherein the doping concentration of the first structure is between 1 E18 and 1 E21 , preferably between 4E19 and 4E20.

6. The adaptor of claim 4 or 5, wherein the doping polarity of the first structure is opposite to the doping polarity of the second structure.

7. The adaptor of any preceding claim, connected, or arranged to be connected, to a transistor, the transistor comprising a gate.

8. The adaptor of any preceding claim, wherein the adaptor comprises the second structure.

9. The adaptor of any preceding claim, wherein the second structure comprises a terminal for connecting the second voltage to the second structure.

10. The adaptor of any preceding claim, wherein the voltage influence is such that the first voltage at said portion of the second structure is substantially lower than the second voltage applied to the second structure.

1 1. The adaptor of any preceding claim, wherein the second structure is arranged to be connected to a drain, gate, source, collector, base or emitter of a transistor, or a P-node or N-node of a diode.

12. The adaptor of claim 1 1 , wherein the second structure is arranged to be connected to the drain, gate, source, collector, base or emitter of the transistor, or the

P-node or N-node of the diode, by wiring.

13. The adaptor of any preceding claim, wherein the semiconductor material of the second structure is lightly doped, and preferably comprises lightly doped polysilicon material.

14. The adaptor of any preceding claim, wherein the semiconductor material of the second structure has a doping concentration of between 1 E14 and 1 E21 , preferably between 1 E15 and 1 E17.

15. The adaptor of any preceding claim, wherein the first and second structures are positioned such that the voltage influence is substantial.

16. The adaptor of any preceding claim, wherein the first and/or second structures comprise a field plate.

17. The adaptor of any of claims 1 to 15, wherein the first structure substantially encloses or surrounds the second structure, or vice versa.

18. The adaptor of any preceding claim, wherein the first structure is positioned, or arranged to be positioned, with respect to the second structure such that the first structure substantially overlaps the second structure.

19. The adaptor of any preceding claim, wherein the conductivity of the first and/or second structures is such that the voltage influence is substantial.

20. The adaptor of any preceding claim, wherein a surface area of the first structure and/or a surface area of the second structure is such that the voltage influence is substantial.

21. The adaptor of any preceding claim, wherein a thickness of the first structure and/or a thickness of the second structure is such that the voltage influence is substantial.

22. A semiconductor device comprising: a transistor; and the adaptor of any preceding claim.

23. The semiconductor device of claim 22, wherein a main extent of the first and second structures is substantially parallel to a substrate of the transistor.

24. The semiconductor device of claim 22, wherein a main extent of the first and second structures is substantially perpendicular to a substrate of the transistor.

25. The semiconductor device of any of claims 22 to 24, wherein the adaptor is integrally formed with the transistor, preferably as part of the transistor fabrication.

26. The semiconductor device of any one of claims 22 to 25, wherein the transistor has an insulating layer disposed over at least a portion of a drain, gate, source, collector, base or emitter, and at least a portion of the voltage adaptor is embedded in the insulating layer, and at least a portion of the insulating layer constitutes the insulating material of the voltage adaptor.

27. The semiconductor device of claim 26, wherein the first and/or second structure is positioned in the insulating layer such that the insulating layer substantially surrounds the exterior surface respectively of the first and/or second structure.

28. The semiconductor device of claim 26, wherein the first structure is located on an exterior surface of the insulating layer.

29. The semiconductor device of any one of claims 22 to 28, wherein the second structure is connected, or arranged to be connected, to a drain, gate, source, collector, base or emitter of the transistor by a first connection means, and the second voltage is applied, or arranged to be applied, to the second structure via a second connection means.

30. The semiconductor device of claim 29, wherein the first and second connection means comprise tungsten.

31. A transistor comprising a structure comprising a semiconductor material arranged to be connected to a drain, gate, source, collector, base or emitter of the transistor, and an insulator material adjacent the semiconductor material, wherein when the structure is subjected to an electric field and a first voltage is applied to the semiconductor material, a second voltage at a portion of the semiconductor material is different from the first voltage.

32. The transistor of claim 31 , wherein the transistor is arranged to receive a further structure comprising an at least partially conductive material to be placed adjacent the insulator material.

33. The transistor of claim 31 or 32, wherein the semiconductor material is connected to the drain, gate, source, collector, base or emitter by a conductor.

34. The transistor of claim 33, wherein the conductor is located at least partially on an exterior surface of the insulator material.

35. A transistor comprising first and second regions in close proximity to each other, the second region being arranged to be influenced by the first region and comprising a lightly doped polysilicon layer connected to the drain, gate, source, collector, base or emitter of said transistor, the transistor further comprising an insulating layer disposed around said second region, the first region comprising metal or polysilicon of opposite doping to said second region, the second region forming an SOI-RESURF region thereby extending the operating voltage of the transistor.

36. A semiconductor device comprising a transistor and a SOI-RESURF region connected to the drain, gate, source, collector, base or emitter of said transistor, the SOI-RESURF region comprising a lightly doped polysilicon layer disposed over an insulating layer adjacent to said transistor, a further insulating layer being disposed on said polysilicon layer, and a metal layer or a further polysilicon layer being disposed on said further insulating layer such that the first polysilicon layer is arranged to be influenced by the metal layer or further polysilicon layer in order to provide a higher voltage capability in said transistor.

37. A method of enhancing a semiconductor device comprising: disposing a lightly doped polysilicon layer over an insulating layer adjacent to the device, the lightly doped polysilicon layer being electrically connected to the device; and disposing a second insulating layer over said polysilicon layer; and disposing a metal layer or a further doped polysilicon layer over said second insulating layer so as to form an SOI-RESURF region in said first polysilicon layer so as to extend the operating voltage capability of said device.

38. A voltage adaptor, semiconductor device, transistor or method, substantially as herein described with reference to, or as illustrated in, the accompanying drawings.