WO2009098895A1 - 映像信号処理方法、集積回路および映像再生装置 - Google Patents
映像信号処理方法、集積回路および映像再生装置 Download PDFInfo
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Definitions
- the present invention relates to video signal processing for combining and outputting two image data having different resolutions, such as those recorded on a large-capacity recording medium such as a Blu-ray disc.
- the picture-in-picture function combines and displays two pieces of image data with the same playback time prepared in advance by the content creator.
- the resolution, frame rate, and composition of image data for the main screen and sub-screen The size conversion magnification on the small screen side when doing so is defined by the standard.
- the image size conversion process provided in the conventional configuration only performs size conversion.
- the parent screen is high resolution data
- the child screen is standard resolution data
- the parent screen image data is enlarged and converted to a predetermined size.
- the present invention solves this problem.
- the image data to be a main screen is a combination of high resolution and the image data to be a sub screen is a combination of standard resolutions.
- An object of the present invention is to enable output of a high-quality composite image in which the difference in resolution between the two screens is minimized when displaying the picture on the main screen and picture-in-picture while enlarging to a predetermined image size.
- the present invention provides a video signal processing method using first and second image data having an interlaced scanning structure as input, performing image size conversion on the first image data, and providing third image data having an interlaced scanning structure.
- An image conversion step for outputting the first image data, and a synthesis step for performing a process for synthesizing the third image data and the second image data.
- a step (a) for performing the p-conversion process, and the progressive scan structure image data generated in step (a) is subjected to a filter process according to the magnification of the image size conversion to generate the third image data.
- the present invention is obtained by performing image size conversion processing on the first image data as an integrated circuit which receives the first and second image data of the interlace scanning structure as input and performs video signal processing.
- An image conversion unit that outputs third image data having an interlaced scanning structure, and a combining unit that performs a process of combining the third image data and the second image data.
- An ip conversion unit that performs an ip conversion process on the first image data, and a progressive scanning structure image data generated by the ip conversion unit according to an image size conversion magnification
- a size conversion unit that performs processing and generates the third image data.
- the present invention also provides a data playback device for playing back data on a recording medium as a video playback device, and two independent compressed video data supplied from the data playback device to decode first and second image data. And an integrated circuit according to the present invention, to which the first and second image data output from the video decoder are input.
- the image size conversion process is performed after the ip conversion process is performed on the first image data, it is possible to improve the sense of resolution as compared with the conventional case.
- the difference in resolution between the two screens can be suppressed to be smaller than in the past.
- image data to be a main screen is a combination of high resolution and image data to be a sub screen is a combination of standard resolutions, and the sub screen side is enlarged to a predetermined image size.
- FIG. 1 is a diagram illustrating an example of an integrated circuit for video signal processing according to the embodiment.
- FIG. 2 is a block diagram of the video playback apparatus according to the embodiment.
- FIG. 3 is a diagram showing fields and line positions of image data having an interlace scanning structure.
- FIG. 4 is a diagram showing the field and line position of the image data converted into the progressive scan structure by the ip conversion.
- FIG. 5 is a diagram illustrating an example of vertical size conversion processing when image data having an interlaced scanning structure is input.
- FIG. 6 is a diagram illustrating an example of vertical size conversion processing when image data converted into a progressive scanning structure by ip conversion is input.
- FIG. 7 is a diagram illustrating another example of the integrated circuit for video signal processing according to the embodiment.
- FIG. 1 is a diagram illustrating an example of an integrated circuit for video signal processing according to the embodiment.
- FIG. 2 is a block diagram of the video playback apparatus according to the embodiment.
- FIG. 3 is a diagram showing fields and line
- FIG. 8 is a diagram illustrating an example of signal processing when the magnification of image size conversion is equal.
- FIG. 9 is a diagram illustrating an example of signal processing when the image size conversion magnification is 1 ⁇ 2.
- FIG. 10 is a diagram illustrating an example of signal processing when the image size conversion magnification is 2 times.
- FIG. 11 is a diagram illustrating an example of signal processing when the image size conversion magnification is 1.5 times.
- FIG. 1 shows an example of an integrated circuit for video signal processing according to this embodiment.
- the integrated circuit in FIG. 1 performs image size conversion on the input terminal 10 to which the first image data is input, the input terminal 11 to which the second image data is input, and the first image data.
- An image conversion unit 12 that outputs the image data and a combining unit 15 that combines the third image data with the second image data are provided.
- the image conversion unit 12 includes an ip conversion unit 13 that performs an ip conversion process, and a size conversion unit 14 that performs an image size conversion process by performing a filter process according to a magnification of the image size conversion.
- the video signal processing method according to the present embodiment is realized in the configuration of FIG.
- FIG. 2 shows an example of the configuration of the video reproduction apparatus according to the present embodiment, which further includes a data reproduction apparatus 100 and a video decoder 101 in addition to the integrated circuit 103 for video signal processing of FIG.
- the data reproducing apparatus 100 reproduces data on the recording medium and supplies two pieces of compressed video data to the video decoder 101.
- the video decoder 101 decodes the two compressed video data, and supplies the generated two image data to the input terminals 10 and 11 as first image data and second image data, respectively.
- the integrated circuit is actually illustrated as having two input terminals 11 and 12 for the input of two image data.
- the present invention is not necessarily limited to this configuration. You may comprise so that one input terminal may be shared. In that case, the two image data are multiplexed and supplied from one input terminal, and separated into two image data in an integrated circuit for video signal processing.
- the input terminal may be a serial method or a parallel method.
- the two independent image data input to this configuration are both in an interlaced scanning structure, the first image data has a standard resolution, the second image data has a high resolution, and the second image data is The realization of picture-in-picture display in which the main screen and the first image data are set as a sub-screen and the sub-screen side is enlarged and combined with the main screen will be described.
- the i-p conversion unit 13 receives the first image data having the interlaced scanning structure as an input, performs i-p conversion, and converts the image data to the progressive scanning structure.
- the size conversion unit 14 performs size conversion processing to a predetermined size using the image data converted into the progressive scanning structure, and then outputs the third image data.
- the image composition unit 15 composes and outputs the third image data to a predetermined position on the second image data as a child screen. Specifically, the third image data is output in a region where the third image is effective, and the second image data is output in other regions. In an area where the third image is effective, the third image data and the second image data may be multiplied by a predetermined ratio and then added and output. Further, the size conversion process here is a process for inputting image data having a progressive scan structure and generating image data having an interlace structure having a predetermined size.
- the ip conversion processing includes, for example, the method proposed in Japanese Patent Laid-Open No. 2000-36944.
- the time direction correlation detection method and the interpolation pixel generation method related to the performance of the ip conversion processing are described. Is not limited.
- FIG. 3 shows the relationship between the field and line position of the image data in the interlaced scanning structure
- FIG. 4 shows the relationship between the field of the image and the line position converted into the progressive scanning structure by the ip conversion
- FIG. 5 shows the structure of the interlaced scanning structure.
- FIG. 6 is a diagram showing vertical size conversion processing when image data is input
- FIG. 6 is a diagram showing vertical size conversion processing when image data converted into a progressive scanning structure by ip conversion is input. is there.
- Conventional size conversion processing in the vertical direction has received image data of an interlaced scanning structure as shown in FIG.
- image data converted into a progressive scanning structure by ip conversion is input.
- the data at the position t26 in FIGS. 5 and 6 is generated, in the conventional processing shown in FIG. 5, the data is generated by performing a filter operation or the like using the data at the positions t10, 12, 14, and 16.
- the vertical position is close to the data at the position of t26 to be interpolated, that is, at the positions of t11, 12, 13, and 14 where the vertical correlation is stronger. It can be generated using some data.
- the vertical size conversion processing shown in FIGS. 5 and 6 performs interpolation processing using four pieces of data in the vertical direction, the number of data used for the interpolation processing is not limited to this.
- the progressive scan structure image data generated by performing the ip conversion process is used as an input, and size conversion is performed using data having a stronger vertical correlation.
- the sense of resolution can be improved compared to the image generated by the enlargement process.
- the processing may be performed as follows.
- FIG. 7 shows another example of an integrated circuit for video signal processing according to this embodiment.
- the same reference numerals as those in FIG. 1 are attached to the same components as those in FIG. 1, and detailed description thereof is omitted here.
- the image conversion unit 12 ⁇ / b> A includes a selector 21 in addition to the ip conversion unit 13 and the size conversion unit 14.
- the selector 21 selectively outputs either the output of the size converter 14 or the original first image data.
- the selector 21 selects and outputs the original first image data.
- the ip conversion processing and the filter processing according to the image size conversion magnification are not executed, and the first image data is directly used as the third image data. Is output. That is, with the configuration of FIG. 7, when the image size conversion magnification is equal, the execution of the filter process is omitted. As a result, the amount of calculation for image size conversion is reduced, and the original image is output as it is, so image quality does not deteriorate.
- FIG. 8 is a diagram showing another signal processing when the magnification of the image size conversion is equal.
- the ip conversion unit 13 generates a progressive image including the original pixel and the interpolation pixel.
- the size conversion unit 14 performs a process of thinning out the interpolation pixels generated by the ip conversion process instead of the filter process.
- the third image data output from the size converter 14 is the same as the original first image data. That is, when the image size conversion magnification is equal to 1 in the process of FIG. 8, the execution of the filter process is omitted. As a result, the amount of calculation for image size conversion is reduced, and the original image is output as it is, so image quality does not deteriorate.
- FIG. 9 is a diagram illustrating an example of signal processing when the image size conversion magnification is 1 ⁇ 2.
- the ip conversion unit 13 does not execute the ip conversion process when 1/2 magnification is designated as the image size conversion magnification. That is, as shown in FIG. 9, the size converter 14 generates third image data from the first image data having the original interlaced scanning structure. Furthermore, as shown in FIG. 9, the size conversion unit 14 performs a process of thinning out pixels instead of the filter process every other field to generate third image data. That is, the filtering process is executed every other field. This makes it possible to reduce the amount of calculation for image size conversion.
- the image size conversion magnification is 1 ⁇ 2, for example, the signal processing, the ip conversion processing, and the filter shown in FIG. You may make it perform selectively the signal processing which performs a process.
- FIG. 10 is a diagram illustrating an example of signal processing when the image size conversion magnification is 2 times.
- the size conversion unit 14 performs filter processing for centroid correction by shifting the pixel position by half a pixel every other field. Assumed to be performed. For a field that is not subjected to center of gravity correction, for example, the execution of the filter process may be omitted. This makes it possible to reduce the amount of calculation for image size conversion.
- FIG. 11 is a diagram illustrating an example of signal processing when the magnification of image size conversion is 1.5 times.
- a i is an original pixel in the first image data
- b i is an interpolation pixel generated by the ip conversion process
- c i is a new pixel generated by the size conversion.
- the size conversion unit 14 from four pixels including two original pixels and two interpolation pixels, It is assumed that the filter operation for generating three new pixels is repeatedly executed. For example, in FIG.
- new pixels c 0 , c 1 , c 2 are generated from the original pixels a 1 , a 2 and the interpolation pixels b 0 , b 1 , and the original pixels a 3 , a 4 and the interpolation pixels b 2 , b 3 are generated.
- new pixels c 3 , c 4 , and c 5 are coefficients of the filter operation. As a result, it is possible to patternize the filter operation, and to reduce the amount of calculation for image size conversion.
- each filter calculation includes a process of using one interpolation pixel as it is as one new pixel by matching the position of the center of gravity of the new pixel with the interpolation pixel.
- the interpolation pixel b 0 is used as it is as a new pixel c 0
- the interpolation pixel b 2 is used as it is as a new pixel c 3 .
- the image data to be the parent screen is 1080i data and the image data to be the child screen is 480i data as defined in the BD-ROM standard, and the child screen is enlarged to a predetermined size.
- the image data to be the parent screen is 1080i data and the image data to be the child screen is 480i data as defined in the BD-ROM standard, and the child screen is enlarged to a predetermined size.
- image data input as the parent screen or the child screen is not limited to the resolution used in the description of the present embodiment.
- a high-quality composite image with a minimal sense of resolution between the two screens can be output. It is useful for video signal processing for combining and outputting two image data having different resolutions, which is used in a BD recorder or the like.
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Abstract
Description
13 i-p変換部
14 サイズ変換部
15 合成部
21 セレクタ
100 データ再生装置
101 ビデオデコーダ
103 集積回路
図7は本実施形態に係る映像信号処理のための集積回路の他の例である。図7において、図1と共通の構成要素には図1と同一の符号を付しており、ここではその詳細な説明は省略する。図7において、画像変換部12Aは、i-p変換部13とサイズ変換部14に加えて、セレクタ21を有している。セレクタ21は、サイズ変換部14の出力と、元の第一の画像データとのいずれかを選択出力する。ここでは、画像サイズ変換の倍率として等倍が指定されたとき、セレクタ21は元の第一の画像データを選択出力するものとする。これにより、画像サイズ変換の倍率が等倍であるとき、i-p変換処理と画像サイズ変換の倍率に従ったフィルタ処理とが実行されないで、第一の画像データがそのまま第三の画像データとして出力される。すなわち、図7の構成によって、画像サイズ変換の倍率が等倍であるときには、フィルタ処理の実行が省かれる。これにより、画像サイズ変換の演算量が削減されるとともに、元の画像がそのまま出力されるため画質劣化が生じない。
図9は画像サイズ変換の倍率が1/2倍であるときの信号処理の一例を示す図である。ここでは、画像サイズ変換の倍率として1/2倍が指定されたとき、i-p変換部13はi-p変換処理を実行しないものとする。すなわち、図9に示すように、サイズ変換部14は、元のインタレース走査構造の第一の画像データから第三の画像データを生成する。さらにサイズ変換部14は、図9に示すように、1フィールドおきにフィルタ処理の代わりに画素を間引く処理を行い、第三の画像データを生成する。すなわち、フィルタ処理は1フィールドおきに実行される。これにより、画像サイズ変換の演算量を削減することが可能になる。
図10は画像サイズ変換の倍率が2倍であるときの信号処理の一例を示す図である。ここでは、画像サイズ変換の倍率として2倍が指定されたとき、図10に示すように、サイズ変換部14は、1フィールドおきに、画素位置を半画素分ずらす重心補正のためのフィルタ処理を行うものとする。重心補正を行わないフィールドについては、例えば、フィルタ処理の実行を省けばよい。これにより、画像サイズ変換の演算量を削減することが可能になる。
図11は画像サイズ変換の倍率が1.5倍であるときの信号処理の一例を示す図である。図11において、ai は第一の画像データにおける原画素、bi はi-p変換処理によって生成された補間画素、ci はサイズ変換によって生成された新画素である。ここでは、画像サイズ変換の倍率として1.5倍が指定されたとき、図11に示すように、サイズ変換部14は、原画素2個と補間画素2個とからなる4個の画素から、3個の新画素を生成するフィルタ演算を繰り返し実行するものとする。例えば図11において、原画素a1 ,a2 と補間画素b0 ,b1 から新画素c0 ,c1 ,c2 を生成し、原画素a3 ,a4 と補間画素b2 ,b3 から新画素c3 ,c4 ,c5 を生成している。α,β(α>β)はフィルタ演算の係数である。これにより、フィルタ演算のパターン化が可能になり、画像サイズ変換の演算量を削減することが可能になる。
Claims (23)
- インターレース走査構造の第一および第二の画像データを入力とする映像信号処理方法であって、
前記第一画像データに対して画像サイズ変換を行い、インターレース走査構造の第三の画像データとして出力する画像変換ステップと、
前記第三の画像データと前記第二の画像データを合成する処理を行う合成ステップとを備え、
前記画像変換ステップは、
前記第一の画像データに対して、i-p変換処理を行うステップ(a)と、
ステップ(a)によって生成されたプログレッシブ走査構造の画像データに対して、画像サイズ変換の倍率に従ってフィルタ処理を行い、前記第三の画像データを生成するステップ(b)とを有している
ことを特徴とする映像信号処理方法。 - 請求項1記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が等倍であるとき、フィルタ処理の実行を省く
ことを特徴とする映像信号処理方法。 - 請求項2記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が等倍であるとき、
前記ステップ(a)および(b)を実行しないで、前記第一の画像データをそのまま前記第三の画像データとして出力する
ことを特徴とする映像信号処理方法。 - 請求項2記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が等倍であるとき、
前記ステップ(b)において、フィルタ処理の代わりに、ステップ(a)で生成された補間画素を間引く処理を行う
ことを特徴とする映像信号処理方法。 - 請求項1記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が1/2倍であるとき、
前記ステップ(a)を実行しないで、前記ステップ(b)において1フィールドおきにフィルタ処理の代わりに画素を間引く処理を行い、前記第三の画像データを生成する
ことを特徴とする映像信号処理方法。 - 請求項1記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が1/2倍であるとき、
前記ステップ(a)および(b)を実行するか、または、前記ステップ(a)を実行しないで、前記ステップ(b)において1フィールドおきにフィルタ処理の代わりに画素を間引く処理を行うかを、選択的に実行する
ことを特徴とする映像信号処理方法。 - 請求項1記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が2倍であるとき、
前記ステップ(b)において、1フィールドおきに、画素位置を半画素分ずらす重心補正のためのフィルタ処理を行う
ことを特徴とする映像信号処理方法。 - 請求項7記載の映像信号処理方法において、
前記ステップ(b)において、重心補正を行わないフィールドについて、フィルタ処理の実行を省く
ことを特徴とする映像信号処理方法。 - 請求項7記載の映像信号処理方法において、
前記ステップ(b)において、重心補正を行わないフィールドについて、新画素の生成のために、重心位置が当該画素と同一の画素を含む奇数個の画素を用いたフィルタ処理を実行する
ことを特徴とする映像信号処理方法。 - 請求項1記載の映像信号処理方法において、
前記画像変換ステップにおいて、画像サイズ変換の倍率が1.5倍であるとき、
前記ステップ(b)において、前記第一の画像データにおける原画素2個と前記ステップ(a)によって生成された補間画素2個とからなる4個の画素から、3個の新画素を生成するフィルタ演算を繰り返し実行する
ことを特徴とする映像信号処理方法。 - 請求項10記載の映像信号処理方法において、
前記フィルタ演算は、1個の補間画素をそのまま、1個の新画素とする処理を含む
ことを特徴とする映像信号処理方法。 - インタレース走査構造の第一および第二の画像データを入力とし、映像信号処理を行う集積回路であって、
前記第一の画像データに対して画像サイズ変換処理を行い、得られたインタレース走査構造の第三の画像データを出力する画像変換部と、
前記第三の画像データと前記第二の画像データを合成する処理を行う合成部とを備え、
前記画像変換部は、
前記第一の画像データに対してi-p変換処理を行うi-p変換部と、
前記i-p変換部によって生成されたプログレッシブ走査構造の画像データに対して、画像サイズ変換の倍率に従ってフィルタ処理を行い、前記第三の画像データを生成するサイズ変換部とを有している
ことを特徴とする集積回路。 - 請求項12記載の集積回路において、
前記画像変換部は、画像サイズ変換の倍率が等倍であるとき、フィルタ処理の実行を省く
ことを特徴とする集積回路。 - 請求項13記載の集積回路において、
前記画像変換部は、画像サイズ変換の倍率が等倍であるとき、前記第一の画像データをそのまま前記第三の画像データとして出力する
ことを特徴とする集積回路。 - 請求項13記載の集積回路において、
前記画像変換部において、画像サイズ変換の倍率が等倍であるとき、
前記サイズ変換部は、フィルタ処理の代わりに、前記i-p変換部によって生成された補間画素を間引く処理を行う
ことを特徴とする集積回路。 - 請求項12記載の集積回路において、
前記画像変換部において、画像サイズ変換の倍率が1/2倍であるとき、
前記i-p変換部がi-p変換処理を実行しないで、前記サイズ変換部が、1フィールドおきにフィルタ処理の代わりに画素を間引く処理を行い、前記第三の画像データを生成する
ことを特徴とする集積回路。 - 請求項12記載の集積回路において、
前記画像変換部において、画像サイズ変換の倍率が1/2倍であるとき、
前記i-p変換部がi-p変換処理を実行するとともに前記サイズ変換部がフィルタ処理を実行するか、または、前記i-p変換部がi-p変換処理を実行しないで、前記サイズ変換部が、1フィールドおきにフィルタ処理の代わりに画素を間引く処理を行うかを、選択的に実行する
ことを特徴とする集積回路。 - 請求項12記載の集積回路において、
前記画像変換部において、画像サイズ変換の倍率が2倍であるとき、
前記サイズ変換部は、1フィールドおきに、画素位置を半画素分ずらす重心補正のためのフィルタ処理を行う
ことを特徴とする集積回路。 - 請求項18記載の集積回路において、
前記サイズ変換部は、重心補正を行わないフィールドについて、フィルタ処理の実行を省く
ことを特徴とする集積回路。 - 請求項18記載の集積回路において、
前記サイズ変換部は、重心補正を行わないフィールドについて、新画素の生成のために、重心位置が当該画素と同一の画素を含む奇数個の画素を用いたフィルタ処理を実行する
ことを特徴とする集積回路。 - 請求項12記載の集積回路において、
前記画像変換部において、画像サイズ変換の倍率が1.5倍であるとき、
前記サイズ変換部は、前記第一の画像データにおける原画素2個と前記i-p変換部によって生成された補間画素2個とからなる4個の画素から、3個の新画素を生成するフィルタ演算を繰り返し実行する
ことを特徴とする集積回路。 - 請求項21記載の集積回路において、
前記フィルタ演算は、1個の補間画素をそのまま、1個の新画素とする処理を含む
ことを特徴とする集積回路。 - 記録媒体のデータを再生するデータ再生装置と、
前記データ再生装置から供給された二つの独立した圧縮ビデオデータをデコードし、第一および第二の画像データとして出力するビデオデコーダと、
前記ビデオデコーダから出力された前記第一および第二の画像データを入力とする、請求項12記載の集積回路とを備えた
ことを特徴とする映像再生装置。
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JPH05304654A (ja) * | 1992-04-27 | 1993-11-16 | Haikomu:Kk | 走査線数の拡大方法 |
JPH05304657A (ja) * | 1992-04-27 | 1993-11-16 | Haikomu:Kk | 走査線数の縮小方法 |
JP2003198980A (ja) * | 2000-11-20 | 2003-07-11 | Victor Co Of Japan Ltd | 映像表示装置 |
JP2003324695A (ja) * | 2002-05-07 | 2003-11-14 | Hitachi Ltd | 映像表示装置及び映像フォーマット変換装置 |
JP2005123775A (ja) * | 2003-10-15 | 2005-05-12 | Sony Corp | 再生装置、再生方法、再生プログラムおよび記録媒体 |
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JPH05304654A (ja) * | 1992-04-27 | 1993-11-16 | Haikomu:Kk | 走査線数の拡大方法 |
JPH05304657A (ja) * | 1992-04-27 | 1993-11-16 | Haikomu:Kk | 走査線数の縮小方法 |
JP2003198980A (ja) * | 2000-11-20 | 2003-07-11 | Victor Co Of Japan Ltd | 映像表示装置 |
JP2003324695A (ja) * | 2002-05-07 | 2003-11-14 | Hitachi Ltd | 映像表示装置及び映像フォーマット変換装置 |
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