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WO2009076324A3 - Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system - Google Patents

Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system Download PDF

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Publication number
WO2009076324A3
WO2009076324A3 PCT/US2008/085990 US2008085990W WO2009076324A3 WO 2009076324 A3 WO2009076324 A3 WO 2009076324A3 US 2008085990 W US2008085990 W US 2008085990W WO 2009076324 A3 WO2009076324 A3 WO 2009076324A3
Authority
WO
WIPO (PCT)
Prior art keywords
strandware
microprocessor
threaded
strand
high performance
Prior art date
Application number
PCT/US2008/085990
Other languages
French (fr)
Other versions
WO2009076324A2 (en
Inventor
Matt Yourst
Original Assignee
Strandera Corp
Matt Yourst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Strandera Corp, Matt Yourst filed Critical Strandera Corp
Priority to US12/331,425 priority Critical patent/US20090150890A1/en
Priority to US12/391,248 priority patent/US20090217020A1/en
Publication of WO2009076324A2 publication Critical patent/WO2009076324A2/en
Publication of WO2009076324A3 publication Critical patent/WO2009076324A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Advance Control (AREA)

Abstract

Strand-based computing hardware and dynamically optimizing strandware are included in a high performance microprocessor system. The system operates in real time automatically and unobservably to parallelize single-threaded software into a plurality of parallel strands for execution by cores implemented in a multi-core and/or multi-threaded microprocessor of the system. The microprocessor executes a native instruction set tailored for speculative multithreading. The strandware directs hardware of the microprocessor to collect dynamic profiling information while executing the single-threaded software. The strandware analyzes the profiling information for the parallelization, and uses binary translation and dynamic optimization to produce native instructions to store in a translation cache later accessed to execute the produced native instructions instead of some of the single-threaded software. The system is capable of parallelizing a plurality of single-threaded software applications (e.g. application software, device drivers, operating system routines or kernels, and hypervisors).
PCT/US2008/085990 2004-11-22 2008-12-08 Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system WO2009076324A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/331,425 US20090150890A1 (en) 2007-12-10 2008-12-09 Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system
US12/391,248 US20090217020A1 (en) 2004-11-22 2009-02-23 Commit Groups for Strand-Based Computing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1274107P 2007-12-10 2007-12-10
US61/012,741 2007-12-10

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/994,774 Continuation-In-Part US7496735B2 (en) 2004-11-22 2004-11-22 Method and apparatus for incremental commitment to architectural state in a microprocessor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/331,425 Continuation-In-Part US20090150890A1 (en) 2004-11-22 2008-12-09 Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system

Publications (2)

Publication Number Publication Date
WO2009076324A2 WO2009076324A2 (en) 2009-06-18
WO2009076324A3 true WO2009076324A3 (en) 2009-08-13

Family

ID=40756092

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/085990 WO2009076324A2 (en) 2004-11-22 2008-12-08 Strand-based computing hardware and dynamically optimizing strandware for a high performance microprocessor system

Country Status (2)

Country Link
TW (1) TW200935303A (en)
WO (1) WO2009076324A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8230410B2 (en) * 2009-10-26 2012-07-24 International Business Machines Corporation Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization
US8495307B2 (en) 2010-05-11 2013-07-23 International Business Machines Corporation Target memory hierarchy specification in a multi-core computer processing system
US8751714B2 (en) * 2010-09-24 2014-06-10 Intel Corporation Implementing quickpath interconnect protocol over a PCIe interface
US20120079245A1 (en) * 2010-09-25 2012-03-29 Cheng Wang Dynamic optimization for conditional commit
WO2013101138A1 (en) * 2011-12-30 2013-07-04 Intel Corporation Identifying and prioritizing critical instructions within processor circuitry
US9405551B2 (en) * 2013-03-12 2016-08-02 Intel Corporation Creating an isolated execution environment in a co-designed processor
US9292288B2 (en) 2013-04-11 2016-03-22 Intel Corporation Systems and methods for flag tracking in move elimination operations
US9195493B2 (en) * 2014-03-27 2015-11-24 International Business Machines Corporation Dispatching multiple threads in a computer
US9870226B2 (en) * 2014-07-03 2018-01-16 The Regents Of The University Of Michigan Control of switching between executed mechanisms
TWI868624B (en) * 2023-03-20 2025-01-01 新加坡商星展銀行有限公司 Source code optimizer and method of optimizing source codes

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JP2003030050A (en) * 2001-07-18 2003-01-31 Nec Corp Method for executing multi-thread and parallel processor system
US20040216101A1 (en) * 2003-04-24 2004-10-28 International Business Machines Corporation Method and logical apparatus for managing resource redistribution in a simultaneous multi-threaded (SMT) processor
US20050138622A1 (en) * 2003-12-18 2005-06-23 Mcalpine Gary L. Apparatus and method for parallel processing of network data on a single processing thread

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003030050A (en) * 2001-07-18 2003-01-31 Nec Corp Method for executing multi-thread and parallel processor system
US20040216101A1 (en) * 2003-04-24 2004-10-28 International Business Machines Corporation Method and logical apparatus for managing resource redistribution in a simultaneous multi-threaded (SMT) processor
US20050138622A1 (en) * 2003-12-18 2005-06-23 Mcalpine Gary L. Apparatus and method for parallel processing of network data on a single processing thread

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NIKO DEMUS ET AL.: "A Thread Partitioning Algorithm using Structural Analysis", INFORMATION PROCESSING SOCIETY OF JAPAN (IPSJ), vol. 74, 2000, pages 37 - 42, Retrieved from the Internet <URL:http://lab.iisec.ac.jp/labs/tanaka/publications/pdf/kennkyukai/kennkyukai-00-13.pdf> *

Also Published As

Publication number Publication date
WO2009076324A2 (en) 2009-06-18
TW200935303A (en) 2009-08-16

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