WO2009000118A1

WO2009000118A1 - A method and an apparatus for smoothly exchanging the data of bus interface in time division multiplex system

Info

Publication number: WO2009000118A1
Application number: PCT/CN2007/003476
Authority: WO
Inventors: Xinan Chen; Jiantu Zhong
Original assignee: Zte Corporation
Priority date: 2007-06-22
Filing date: 2007-12-06
Publication date: 2008-12-31
Also published as: CN101079686A

Abstract

A method for smoothly exchanging the data of bus interface in time division multiplex system is provided, and the technical scheme is: determining the data rate of each interface accessing the time division multiplex system, and providing a corresponding clock signal and a frame synchronization signal to each interface based on the rate determined, including following steps: A, judging whether the rate of source data interface is equal to the rate of destination data interface (S404), if yes going to step B, else going to step C; B, transparently transmitting the data of source data interface to the destination data interface and ending current process (S406); C, buffering the data of source data interface, and the destination data interface reading the data buffered basing on the clock signal and the frame synchronization signal of itself during the buffering process and transmitting it (S408). This invention also provides an apparatus for implementing the above method.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplexing system bus interface data conversion technique, and more particularly to a method and apparatus for data smooth conversion between high speed path interfaces in a time division multiplexing system. BACKGROUND In order to improve the utilization of a channel, a plurality of low-speed data terminals are combined to use a high-speed channel in the transmission of data. This processing technique is called multiplexing, and a common multiplexing technique has frequency division multiplexing and Time Division Multiplex (TDM). Time division multiplexing is to divide a physical channel into a number of time slices (i.e., time slots) in turn, and each user is occupied by a multiplexed user. The time division multiplexing technology is characterized in that the time slot is planned and allocated in advance and is fixed. Because the time slot allocation is fixed, it is convenient to adjust the control and is suitable for the transmission of digital information. Time-division multiplexing technology is widely used, such as Synchronous Digital Hierarchy (SDH). Asynchronous Transfer Mode (ATM), Internet Protocol (IP), etc. The technology used. With the continuous development of access network technology, TDM + IP bus technology is more and more common in the access network architecture. With the advent of new access technologies such as Voice over IP (VoIP) and the increasing demand for bandwidth, it is inevitable to increase the bandwidth of the system TDM bus. In the traditional access network system, the common bandwidth of the TDM bus is 2 Mbps, 4 Mbps, 8 Mbps, and with the increase of bandwidth demand and the integration of the access network system, the application of higher TDM bandwidth such as 16 Mbps and 32 Mbps. More and more. In the traditional TDM switching system, only a single backplane rate is supported, such as 2 Mbps or 8 Mbps. The trunk board is generally developed according to the TDM backplane rate, and is only suitable for the backplane of the corresponding rate. Once the system TDM backplane bandwidth is to be increased, the relay board that it is adapted to cannot continue to be used in the new system. In this way, the old relay board cannot be compatible with the backplane in the new system, resulting in waste of resources, especially where some systems can be upgraded by expansion; in addition, due to the development of new TDM backplane rates The relay board causes the development cycle of the system to be extended, and the R&D and production costs are also high. SUMMARY OF THE INVENTION In view of one or more of the problems described above, the present invention provides a method and apparatus for data smoothing conversion of a time division multiplexing system bus interface to implement data between interfaces of different rates of high speed (HW). Smooth conversion. A method for data smoothing conversion of a time division multiplexing system bus interface according to an embodiment of the present invention is used to determine a data rate of each interface of an access time division multiplexing system, and provide a corresponding clock signal and a frame synchronization signal for each interface according to the determined rate. Specifically, the method includes the following steps: A: determining whether the source data interface rate is equal to the destination data interface rate, if yes, proceeding to step B, otherwise proceeding to step C; B, transparently transmitting the source data interface data to the destination data interface And ending the current processing; and buffering the source data interface data, the destination data interface reads the buffered data and sends the data according to the clock signal and the frame synchronization signal according to the clock signal and the frame synchronization signal. Step B further includes: synchronously adjusting the data of the transparent source data interface when the data is out of synchronization. The process of determining the data rate of each interface includes: periodically scanning each interface of the access time division multiplexing system, and determining the data rate supported by the interface according to the interface type. An apparatus for smoothing data transition of a time division multiplexing system bus interface according to an embodiment of the present invention includes: an interface rate determining unit, configured to determine a data rate of each interface of the access time division multiplexing system; and a clock and frame synchronization signal providing unit, configured to Providing a corresponding clock signal and a frame synchronization signal for each interface according to the rate determined by the interface rate determining unit; an interface rate conversion unit, configured to implement data conversion between the source data interface and the destination data interface; and a data sending unit, configured to send The interface rate conversion unit converts the data. The interface rate conversion unit includes: a data interaction interface rate determining module, configured to determine whether the source data interface rate is equal to the destination data interface rate, trigger the source data interface data transparent transmission module when equal to, and trigger the source data interface data when not equal to a cache module; a source data interface data transparent transmission module, configured to transparently transmit source data interface data to a destination data interface; a source data interface data cache module for buffering source data interface data; and a destination data interface data reading module, The buffered data is read according to the clock signal and the frame synchronization signal of the destination data interface during the buffering of the data in the data interface module of the source data interface, and the data sending unit is triggered. The interface rate conversion unit further includes: a source data interface data out-of-step adjustment module, configured to synchronously adjust the data to be transparently transmitted by the source data interface data transparent transmission module. The present invention determines the rate supported by each HW interface in an access time division multiplexing system, and Support for these HW interfaces is achieved by providing corresponding clock signals and frame synchronization signals for these HW interfaces. In addition, in the present invention, when there is data interaction between the HW interfaces, it is first determined whether the rate supported by the interactive interface matches, the data is directly transmitted through the matching, the source data interface data is cached when the matching is not performed, and the destination data is reused. The interface clock signal and the frame synchronization signal read the buffered source data interface data and transmit, thereby completing smooth conversion of data between the HW interfaces. The invention can support data conversion between different speed HW data interfaces of various relay boards and HW data interfaces supporting high bandwidth, thereby realizing protection of existing investment equipment. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 is a schematic structural diagram of a time division multiplexing system bus interface data smoothing conversion apparatus according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of an interface rate conversion unit according to an embodiment of the present invention; A schematic diagram of a structure implementation of a data smoothing conversion apparatus for a time division multiplexing system bus interface according to an embodiment of the present invention; and FIG. 4 is a flowchart of a data smoothing conversion method of a time division multiplexing system bus interface according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The core idea of the present invention is: In a time division multiplexing system, in order to adapt to current high bandwidth requirements and to protect existing investment equipment, it is required to perform between a high bandwidth HW interface and a low speed relay board HW interface. Smooth data conversion. The present invention achieves support by determining the rate of each access riw interface. In the case of rate matching between the HW interfaces currently performing data conversion, the HW interfaces directly transmit transparently, and in the case of rate mismatch, the data to be transmitted is buffered, and the destination data interface uses its own clock signal and frame. The synchronization signal reads the buffered source data interface data and transmits it, thereby supporting high bandwidth and protecting the original equipment investment. The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. 1 is a time division multiplexing system bus interface data smoothing conversion device according to an embodiment of the present invention Schematic diagram of the composition. As shown in FIG. 1, the TDM system bus interface data smoothing conversion apparatus includes an interface rate determining unit 10, a clock and frame synchronization signal providing unit 11, an interface rate converting unit 12, and a data transmitting unit 13. The interface rate determining unit 10 is configured to determine a data rate of each interface of the access time division multiplexing system. For the TDM system, the high bandwidth provided by the TDM system is generally determined, for example, 32 Mbps or 64 Mbps, etc., and the interface rate determining unit 10 is mainly to determine the MN interface rate of the relay board in the TDM system. The HW interface rates provided by the different relay boards are different, and the HW interfaces provided by the relay boards are dynamically changed. The present invention periodically identifies the relay boards inserted in each slot. The purpose of identifying the trunk board is to determine the board type of the trunk board in a certain slot. The HW interface rate supported by the board type of each trunk board is also different. The type of the trunk board is determined. The HW interface rate of the currently inserted relay board. The clock and frame synchronization signal providing unit 11 is configured to provide a corresponding clock signal and a frame synchronization signal for each interface according to the rate determined by the interface rate determining unit. The clock and frame synchronization signal providing unit 11 provides clock signals and frame synchronization signals for all HW interfaces accessing the TDM system, so as to implement support for all HW interfaces accessing the TDM system, and realize clock signals and frame synchronization signals in the entire TDM system. Unity. The interface rate conversion unit 12 is configured to implement data conversion between the source HW data interface and the destination HW data interface. The data transmitting unit 13 is configured to send the converted data of the interface rate converting unit. The data transmitting unit 13 according to the embodiment of the present invention supports data transmission of a high-bandwidth HW interface and low-speed HW interface data transmission on a relay board. Since the HW data interface of the TDM system is in the duplex mode, the data transmitting unit 13 according to the embodiment of the present invention logically supports data transmission of the HW interface. It will be understood by those skilled in the art that the above various units of the present invention can realize their respective functions through corresponding logic circuits, and can also realize their respective functions by using programmable devices in combination with control software or control logic. 2 is a schematic structural diagram of an interface rate conversion unit according to an embodiment of the present invention. As shown in FIG. 2, the interface rate conversion unit 12 includes a data interaction interface rate determination module 120, a source data interface data transparent transmission module 121, a source data interface data cache module 122, a destination data interface data reading module 123, and source data. The interface data out of synchronization adjustment module 124. The data interaction interface rate determining module 120 is configured to determine whether the source HW data interface rate is equal to the destination HW data interface rate, and trigger the source data interface data transparent transmission module 121 when equal to, and trigger the source data interface data cache module 122 when not equal to . It should be noted that since the HW data interface that accesses the TDM system is in the Han mode, the HW data interface supporting the high bandwidth or supporting the low bandwidth is both the source HW data interface and the destination HW data interface, specifically The direction in which the data is sent is determined. The data interaction interface rate determining module 120 is specifically located in the interface rate determining unit 10 The determined HW data interface determines whether the data rate supported by the source data interface and the destination HW data interface matches. The source data interface data transparent transmission module 121 is configured to transparently transmit the source data interface data to the destination data interface. When the source data interface data transparent transmission module 121 transparently transmits data, the data synchronization interface module 124 needs to be triggered to adjust the out-of-step data when the data is out of synchronization. The source data interface data out-of-step adjustment module 124 is configured to synchronously adjust the data to be transparently transmitted by the source data interface data transparent transmission module 121. In the present invention, especially when the HW data interface of the relay board is mapped to the HW data interface supporting the high bandwidth, that is, in the uplink direction of the data, due to factors such as the driver and the backplane, the data to be transmitted may have a timing delay. The data bit to be transmitted is shifted, and the data is delayed by the data transmission unit 13 to transmit the data. Of course, if the downlink data is out of synchronization, the source data interface data out-of-step adjustment module 124 needs to be triggered to adjust the out-of-step data. The source data interface data cache module 122 is configured to cache source data interface data. The data interface data reading block 123 is configured to read the buffered data according to the clock signal and the frame synchronization signal of the destination data interface during the buffering of the data by the source data interface data buffering module 122, and trigger the data sending unit 13 to send and read. The data. Considering the manner of data transmission between the HW data interfaces, and in order to improve the efficiency of data conversion between the HW data interfaces, the source data interface data cache module 122 according to the embodiment of the present invention is specifically implemented by using a dual port RAM, so that the source HW is During the data interface data buffering process, the destination data interface data reading module 123 reads both the cached source data interface data and triggers the data transmitting unit 13 to transmit. It is not necessary to wait until the source data interface data is stored before triggering the destination data interface data reading module 123 to read. When the HW data interface data supporting high bandwidth is mapped to the low-speed HW data interface of the relay board, complete synchronous smooth conversion can be realized. When the low-speed HW data interface data of the relay board is mapped to the HW data interface supporting high bandwidth, the above processing mechanism improves the conversion efficiency. When the data of the source HW data interface is buffered, the clock signal of the source HW data interface and the data frame time slot supported by the source HW data interface are stored, and the destination data interface data reading module 123 reads the buffer. When the source data interface data is read, the clock signal of the destination HW data interface and the data frame time slot supported by the destination HW data interface are read in units. In this way, data smooth conversion between HW data interfaces is realized. The TDM system bus interface data smoothing conversion device according to the embodiment of the present invention can support data conversion between different speed HW data interfaces of various relay boards and HW data interfaces supporting high bandwidth, thereby realizing the existing investment equipment. protection of. FIG. 3 is a schematic diagram showing the structure of a time division multiplexing system bus interface data smoothing conversion apparatus according to an embodiment of the present invention. As shown in Figure 3, multiple trunk boards and HW data connections supporting high bandwidth The ports are all connected to the interface rate conversion unit 12 through a backplane bus. The interface rate determining unit 10 and the clock and frame sync signal providing unit 11 are also connected to the interface rate converting unit 12 through a backplane bus. The clock and frame sync signal providing unit 11 supplies a clock signal and a frame sync signal to the relay board, the interface rate converting unit 12, the interface rate determining unit 10, and the HW data interface supporting the high bandwidth. The interface rate determining unit 10 is connected to each of the relay boards through a board type scan control bus. The HW data interface on the relay board and the HW data interface supporting high bandwidth can provide data transmission and reception, thereby constituting the data transmitting unit 13 according to an embodiment of the present invention. The high-capacity TDM switch chip can provide a backplane bus and a relay board connection slot according to an embodiment of the present invention, and a programmable device having an on-chip DPRAM resource can implement an interface rate conversion unit 12, and the interface rate determination unit 10 is controlled by a host CPU. Implementation, the clock and frame sync signal providing unit 11 can also be provided by a programming device. A method for data smoothing conversion between interfaces of a TDM system according to an embodiment of the present invention will be described below. 4 is a flow chart of a time division multiplexing system bus interface data smoothing conversion method according to an embodiment of the present invention. As shown in FIG. 4, the TDM system bus interface data smooth conversion method includes the following steps:

S402. Determine a data rate of each HW data interface of the access time division multiplexing system, and provide corresponding clock signals and frame synchronization signals for the HW data interfaces according to the determined HW data interface rates. Step S402 is a basic step of the data smoothing conversion method according to the embodiment of the present invention. It should be understood by those skilled in the art that since the TDM system includes the provided high bandwidth HW data interface and the accessed relay board HW data interface, the data rate supported by the TDM system is determined and the corresponding clock signal and frame are provided thereto. The sync signal is easy to implement. Since the HW data interface on the trunk board of the TDM system may be dynamically changed, it is necessary to periodically scan the HW data interface of the access time division multiplexing system and determine the data rate supported by the current HW data interface. For details, refer to the foregoing description of the data smoothing conversion device portion according to an embodiment of the present invention. S404. Determine whether the source data interface rate is equal to the destination data interface rate. If yes, go to step S406, otherwise go to step S408. Step S404 is to determine which HW data interfaces need to perform data interaction, and determine whether the rate between the HW data interfaces supports the rate according to the rate of the HW data interface supported in step S402, and directly transmit the data to be transmitted when the matching is performed. These data need to be smoothly converted when they do not match. S406. Pass the source data interface data to the destination data interface and end the current processing. When the source data interface data is transparently transmitted, it needs to be judged whether it is out of step or not. Number of source data interfaces to be transparently transmitted Synchronous adjustments are made when out of step. Especially in the data uplink direction, due to factors such as the driver and the backplane, the data to be transmitted may have a timing delay, which causes the data bits to be transmitted to be offset. In this case, the data needs to be delayed and then transmitted. For details, refer to the foregoing description of the data smoothing conversion device portion according to an embodiment of the present invention. S4078: Cache source data interface data, and the destination data interface reads the buffered data and sends the data according to the clock signal and the frame synchronization signal in the cache process. The cache source data interface data can use dual-port RAM. In the process of data buffering of the source HW data interface, the destination data interface data reads the cached data and sends it. When buffering, the clock signal of the source HW data interface and the data frame time slot supported by the source data interface are stored in units of clocks, and the clock signal of the destination HW data interface and the target HW data interface are supported. The data frame time slot is read in units. For a specific implementation, reference may be made to the foregoing description of the data smoothing conversion device according to the embodiment of the present invention, and details are not described herein again. The data smoothing conversion method between interfaces in the time division multiplexing system according to the embodiment of the present invention can support data conversion between different speed HW data interfaces of various relay boards and HW data interfaces supporting high bandwidth, thereby realizing the present There is protection for investment equipment. The above is only the embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the appended claims.

Claims

A method for data smoothing conversion of a time division multiplexing system bus interface, characterized in that: determining a data rate of each interface of the access time division multiplexing system, and providing a corresponding clock signal and a frame synchronization signal for each interface according to the determined rate, The method includes the following steps:

A, determining whether the source data interface rate is equal to the destination data interface rate, if yes, proceed to step B, otherwise proceed to step C;

B. Transparently transmitting the source data interface data to the destination data interface and ending the current processing;

C. Cache source data interface data, the destination data interface reads the cached data and sends the data according to the clock signal and the frame synchronization signal in the cache process.

2. The method according to claim 1, wherein the step B further comprises: r:

When the data of the transparent source data interface is out of synchronization, it is synchronously adjusted.

The method for smooth data conversion of a time division multiplexing system bus interface according to claim 1 or 2, wherein determining the data rate of each interface comprises:

Periodically scan the interfaces of the access time division multiplexing system and determine the data rate supported by the interface according to the interface type.

A device for time-division multiplexing system bus interface data smooth conversion, characterized in that the device comprises:

An interface rate determining unit, configured to determine a data rate of each interface of the access time division multiplexing system;

a clock and frame synchronization signal providing unit, configured to provide a corresponding clock signal and a frame synchronization signal for each interface according to the rate determined by the interface rate determining unit;

An interface rate conversion unit, configured to implement data conversion between a source data interface and a destination data interface;

And a data sending unit, configured to send the converted data of the interface rate conversion unit. The device of the time division multiplexing system bus interface data smoothing conversion according to claim 4, wherein the interface rate conversion unit comprises: The data interaction interface rate judging module is configured to determine whether the source data interface rate is equal to the destination data interface rate, and trigger the source data interface data transparent transmission module when equal to, and trigger the source data interface data caching module when not equal to;

The source data interface data transparent transmission module is configured to transparently transmit the source data interface data to the destination data interface;

a source data interface data cache module, configured to cache source data interface data; a destination data interface data reading module, configured to read according to a clock signal and a frame synchronization signal of the destination data interface in the process of buffering data by the source data interface data cache module Take the cached data and trigger the data sending unit.

The device of the time division multiplexing system bus interface data smoothing conversion according to claim 4, wherein the interface rate conversion unit further comprises: a source data interface data out-of-step adjustment module, configured to use the source data The interface data transparent transmission module synchronizes the data to be transparently transmitted when it is out of synchronization.