WO2008102285A1

WO2008102285A1 - Electrostatic discharge protection circuit and protected device, and a protection method

Info

Publication number: WO2008102285A1
Application number: PCT/IB2008/050523
Authority: WO
Inventors: Olivier Quittard
Original assignee: Nxp B.V.
Priority date: 2007-02-20
Filing date: 2008-02-13
Publication date: 2008-08-28

Abstract

An ESD protection circuit has an SCR provided between first and second voltage supply terminals. A transistor circuit controls the triggering of the SCR, and is adapted to turn the SCR on in response to a voltage surge on the first voltage supply terminal. An RC control circuit is adapted to control the transistor circuit to turn the SCR off after a delay following the voltage surge.

Description

DESCRIPTION

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND PROTECTED DEVICE, AND A PROTECTION METHOD

The invention relates to an electrostatic protection circuit, to a device protected against electrostatic discharge and a method of protecting the device.

Protection against electrostatic discharge (ESD) may be integrated onto a chip, especially an integrated circuit, by providing a defined low impedance channel to prevent thermal damage in silicon. Alternatively, an ESD voltage pulse may be clamped to a safe level.

Providing ESD protection is a particular difficulty for mixed-voltage technologies, which are being extensively used for consumer electronic products. One example is display drivers ICs where a low-voltage digital part controls high-voltage analogue outputs.

Various ESD protection strategies have been proposed, including voltage-triggered active clamps and RC-triggered high voltage transistors. One class of solutions involves the use of a semiconductor controlled rectifier (SCR, otherwise known as a thyhstor), which can be integrated onto the substrate of the integrated circuit. SCRs are known to provide excellent ESD protection, but these devices can be slow to react to ESD pulses on the pins of the integrated circuit device. Latch-up is a major concern in integrated circuits, in particular when

SCRs are used. Latch-up is a condition in which the SCR has stabilized in the on-state, and thereby provides an undesired low impedance path between the voltage supply rails, possibly draining a connected battery, or causing damage to the circuit. The SCR device is particularly susceptible to latch-up, because of its very low holding voltage, which is typically below the supply voltage. Avoiding latch-up when using SCRs requires a major engineering effort to tune all of the layout parameters, which has to be repeated for each new technology. Moreover, SCRs still present some risk for ESD-induced latch-up (during system-level ESD testing or voltage spikes during normal operation mode, for example) because of their low holding voltage.

There are also different options for the triggering mechanism for ESD protection, and there have been studies of how best to trigger an ESD event. One approach is to detect a voltage level using for example a Zener diode or a series of diodes in a cascaded arrangement to detect the voltage pulse. An alternative approach is to detect a rapidly changing voltage using a resistor - capacitor (RC) circuit as a trigger. A further alternative is to use detection of a current flow as a trigger event. More complex circuits have also been proposed to generate a signal when an ESD event is detected. However, there remains a need for rapid triggering of ESD protection.

This invention relates specifically to SCR ESD protection solutions, and aims to provide a low area solution, with improved latch-up immunity, because it can be switched off during normal operation of the IC, and with rapid active triggering during an ESD pulse (or during other voltage spikes on supply buses).

According to the invention, there is provided an ESD protection circuit, comprising: a semiconductor controlled rectifier (hereinafter "SCR") provided between first and second voltage supply terminals; a transistor circuit for controlling the triggering of the SCR, and which is adapted to turn the SCR on in response to a voltage surge on the first voltage supply terminal; an RC control circuit which is adapted to control the transistor circuit to turn the SCR off after a delay following the voltage surge.

The invention uses a transistor controlled SCR to provide ESD protection (for example a MOSFET controlled SCR). The SCR is controlled actively both for switch on and switch off. This provides an arrangement that is immune to latch-up. The design can be robust to process variations, and can quickly and easily be adapted for different high voltage supply requirements. The SCR is used as a power device to give a high current capability.

The RC control circuit preferably comprises a resistor and capacitor in series between the first and second voltage supply lines, and wherein the junction between the resistor and capacitor provides a switch off control signal.

This switch off signal then decays in a predictable way after a voltage surge so that the predetermined delay is defined.

A drive circuit and/or an inverter may be provided, for processing the switch off control signal provided by the RC control circuit. This provides a more accurately defined (sharp) control signal for the transistor circuit.

The SCR preferably comprises has an equivalent circuit of: a first bipolar transistor between the first voltage supply terminal and the base of a second bipolar transistor, with the second bipolar transistor between the base of the first bipolar transistor and the second voltage supply terminal. The transistor circuit can then comprise a first transistor for actively turning the SCR off by shorting the base and emitter of one of the bipolar transistors. The transistor circuit can comprise a second transistor for actively turning the SCR on by shorting the collector and emitter of one of the bipolar transistors. The transistor circuit preferably comprises a MOSFET circuit. The invention also provides an ESD protected device comprising: an input pad; at least one device to be protected having a first terminal connected to the input pad; and an ESD protection circuit of the invention. The invention also provides a method of providing ESD protection, comprising: controlling the triggering of a semiconductor controlled rectifier (hereinafter "SCR") provided between first and second voltage supply terminals, such that: the SCR is turned on in response to a voltage surge on a first voltage supply terminal; and the SCR is turned off by an RC control circuit after a delay following the voltage surge.

For a better understanding of the invention, an embodiment will now be described, purely by way of example, with reference to the accompanying drawings in which:

Figure 1 shows a known MOSFET controlled SCR; Figure 2 shows an ESD protection circuit of the invention; and Figure 3 shows an ESD protected device of the invention. The drawings are purely schematic and not to scale. Like components are given the same reference numerals in different figures.

The invention provides an ESD protection circuit which uses an actively controlled semiconductor controlled rectifier ("SCR"). A transistor circuit (preferably a MOSFET circuit) provides the SCR control. Latch-up is prevented by an RC control circuit (labeled "RC trigger circuit" in Figure 2), which is adapted to control the transistor circuit to turn the SCR off after a predetermined delay following a detected voltage surge.

Figure 1 shows a known MOSFET controlled SCR circuit, and which forms the main building block of the ESD protection circuit of the invention.

The circuit is represented by a first PNP bipolar transistor 10 between a first voltage supply terminal 12 (the anode) and the base of a second, NPN, bipolar transistor 14. The second bipolar transistor 14 is between the base of the first bipolar transistor 10 and a second voltage supply terminal 16 (the cathode). In practice, the two bipolar devices are integrated together, with the base of the PNP device functioning as the collector of the NPN device, and vice versa.

These two transistors together define a conventional SCR (thyhstor).

The SCR is controlled by a MOSFET transistor circuit, which comprises a first n-type transistor 18 for actively turning the SCR off by shorting the base and emitter of the bipolar transistor 10. A second, p-type, transistor 20 is for actively turning the SCR on, by shorting the collector and emitter of the bipolar transistor 10. The SCR may alternatively be turned on by shorting the collector and base of the bipolar transistor 14.

The MOSFET-controlled SCR shown in Figure 1 is conventionally used as a power switching device. The emitters of the PNP and NPN bipolar transistors form the anode and cathode contacts, respectively, and the two control transistors have a common gate contact which forms the gate node 22 of the controllable SCR circuit.

Assuming the anode is biased positively (VDD) and cathode is tied to ground (VSS), the circuit functions in the following way:

When the gate node is tied to ground (VSS), the circuit operates with the SCR turned on, and thereby providing an ESD discharge path. The circuit remains turned on until a current flow between the anode and cathode drops below a threshold level. In particular, transistor 18 is off and transistor 20 is turned on. This means the drain voltage of the transistor 20 is pulled high, giving a high base voltage for the bipolar transistor 14. This turns the bipolar transistor 14 on, which in turn pulls the base voltage of the PNP bipolar transistor low, which turns transistor 10 on. The two bipolar transistors are thus turned on, and the SCR is in an on state. The SCR is kept on until the current flow drops below the so-called holding current.

When the gate node is tied to a high voltage (VDD), the circuit is actively switched off. In particular, the transistor 18 is turned on and the transistor 20 is turned off. The base-to-emitter voltage of the PNP bipolar transistor is thus set at VSS (e.g. OV), and this turns off the PNP transistor 18, which in turn switches off the NPN transistor 10, so that the SCR is turned off.

The MOSFET-controlled SCR can be both turned on and turned off using the gate node. Fast turn-on and turn-off behaviour can be obtained due to the MOSFET switching devices, and high current capability is possible due to the bipolar SCR device. The invention is based on the recognition that this type of circuit can be controlled to provide actively triggered ESD protection using an RC control circuit, to provide latch-up immunity, and high current capability. Figure 2 shows an ESD protection circuit of the invention, and comprises a MOSFET controlled SCR 30 which functions as described with reference to Figure 1 , an RC control circuit 32, a pre-dhver circuit 34 and an inverter circuit 36. The resistors R2 and R3 represent the inherent well resistance of both p-well and n-well devices.

The RC control circuit 32 is adapted to control circuit 30 to turn the SCR off after a predetermined delay following a voltage surge.

The RC control circuit comprises a resistor RO and capacitor CO in series between the anode 12 and cathode 16. The junction 38 between the resistor and capacitor provides a switch off control signal. This switch off signal then ramps up in a predictable way after a voltage surge so that a predetermined delay is defined.

The RC decay signal is provided to a pre-dhver circuit 34 which provides a signal with a sharp transition. In the example shown, the pre-dhver circuit comprises a PMOS transistor 40 which drives a resistive load R1.

In a steady state DC condition, there is no current flowing through the capacitor CO, and the gate of p-type transistor 40 has been charged to a high level, so that the transistor 40 is turned off. The drain of the transistor 40 is tied to ground (VSS).

The steady state condition is thus a low signal on line 42. This is converted to a high signal by the inverter 36, which has transistor MP1 on. This high output signal on the gate line 44 turns off the SCR as explained above. When a positive stress (an ESD pulse) is applied to the anode (at VDD) compared to the cathode (at VSS), the circuit operates as follows.

The ESD pulse raises the voltage on VDD, which pulls up the source voltage of the p-type transistor 40. The gate voltage of transistor 40 is initially held low by the capacitor CO which cannot change voltage instantaneously. As a result, the transistor 40 is initially turned on. The voltage on the drain of the transistor 40 rises and turns on the inverter n-type transistor MN1 , so that the voltage on the gate line 44 is pulled down to the voltage VSS.

As described above, this turns on the SCR to provide an ESD protection discharge path.

The gate voltage of the transistor 40 will vary as the capacitor CO charges in response to the change in the voltage VDD. The gate voltage will reach a voltage which turns the transistor 40 back off after a time delay which depends on the RC time constant. However, the transistor 40 should remain turned on for the duration of the ESD event. After the ESD event, the voltage VDD will return to its previous levels, and the steady state condition will again be reached.

The control circuit RC time constant must therefore be large enough to keep the SCR on throughout the duration of the ESD pulse. On the other hand, it has to be small enough to switch off the SCR after the supply voltage has stabilized to the normal circuit operating state. With a resistor value of 250kΩ and a capacitance value of 4.OpF, an RC time constant of 1 μs is obtained.

The invention uses a controlled SCR to provide ESD protection. The

SCR is controlled actively both for switch-on and switch-off. This provides an arrangement that is immune to latch-up. The design can be robust to process variations, and can quickly and easily be adapted for different high voltage supply requirements. The SCR is used as a power device to give a high current capability. The SCR device is turned on during an ESD pulse or a voltage spike on VDD. The structure of the MOSFET-controlled SCR enables the circuit to be automatically turned off once the overstress is finished (for example after a defined RC delay).

When a negative stress is applied on the anode compared to the cathode VSS, the current can flow through the intrinsic parasitic diode of the SCR. In the circuit described above, the RC control circuit turns on the SCR on the rising edge of the ESD pulse (and not only on the peak voltage reached). This widens the design window compared to the more conventional clamp arrangement, in which the clamp is allowed to turn on only after the ESD pulse voltage has exceeded the supply voltage.

The use of an SCR as power device enables a high current capability (~40mA/μm) compared to conventional voltage clamps (typically about 10 mA/μm).

The invention can enable a significant decrease in area consumption, directly dependent on the currently capability.

The active control of the switch on and off of the SCR circuit gives latch- up immunity, both for DC latch-up and ESD induced latch-up. The invention is of particular interest for all CMOS technologies, including Advanced CMOS. Ranges of application of the invention include small and large display drivers, SMART power technologies, and automotive technologies.

Figure 3 shows an ESD protected device comprising input pads 54,56, in which a device to be protected 50 has a first terminal connected to the first input pad 54 and a second terminal connected the second input pad 56. An

ESD protection circuit 52 of the invention provides a discharge path between the input pads.

The detailed design of the SCR circuit has not been described, as this will be routine to those skilled in the art. In particular, the timing of the start of the ESD protection period is dependent on the risetime of a pulse at terminal

VDD. If it is significantly shorter than the RC time determined by RO and CO, the SCR will be triggered. The timing of the end of the ESD protection period is determined by the RC time. After a time longer than the RC time, the control circuit will return to its original (off) state, thus switching the SCR off.

Therefore, the SCR can only be active during pulses shorter than the RC time, which provides perfect immunity against DC latch-up.

The holding voltage does not need to be higher than the nominal voltage swings, in order to prevent accidental latch-up issues, as would be required for conventional SCRs, used as ESD protection devices. The triggering voltage has to be lower than the minimum failure voltage of the circuit being protected, to ensure that these circuits do not suffer any damage.

Only one example of RC control circuit has been shown, but it will be apparent to those skilled in the art that other circuits are possible. Similarly, different circuit designs for the MOSFET controlled SCR are possible.

The inverter may not be required. For example, in a different circuit configuration, the PMOS and NMOS transistors may be swapped and the inverter removed. The pre-dhve circuit functions as an inverter, and its resistor could be replaced by an NMOS transistor, so that the pre-drive circuit can combine pre- dhve and inverter functions, further reducing the area and power consumption.

The pre-drive circuit is also optional, and the inverter circuit can implement the waveform shaping function of the pre-driver circuit. Indeed, both the inverter and pre-drive circuits are not essential to the invention, and the RC circuit may directly supply a control signal to a suitable MOSFET controlled SCR.

Various other modifications will be apparent to those skilled in the art.

Claims

1. An ESD protection circuit, comprising: a semiconductor controlled rectifier (30) (hereinafter "SCR") provided between first (12) and second (16) voltage supply terminals; a transistor circuit (MN2,MP2) for controlling the triggering of the SCR, and which is adapted to turn the SCR on in response to a voltage surge on the first voltage supply terminal (12); an RC control circuit (32) which is adapted to control the transistor circuit to turn the SCR off after a delay following the voltage surge.

2. A circuit as claimed in claim 1 , wherein the RC control circuit (32) comprises a resistor (RO) and capacitor (CO) in series between the first and second voltage supply lines (12,16), and wherein the junction (30) between the resistor and capacitor provides a switch off control signal.

3. A circuit as claimed in any preceding claim, further comprising a driver circuit (34) for providing a sharpened switch off control signal from the switch off control signal provided by the RC control circuit (32).

4. A circuit as claimed in any preceding claim, further comprising an inverter circuit (36), for inverting a switch off control signal provided by the RC control circuit.

5. A circuit as claimed in any preceding claim, wherein the SCR has an equivalent circuit of: a first bipolar transistor (10) between the first voltage supply terminal (12) and the base of a second bipolar transistor (14), with the second bipolar transistor (14) between the base of the first bipolar transistor (10) and the second voltage supply terminal (16).

6. A circuit as claimed in claim 5, wherein the transistor circuit comprises a first transistor (MN2,18) for actively turning the SCR off by shorting the base and emitter of one (10) of the bipolar transistors.

7. A circuit as claimed in claim 6, wherein the transistor circuit comprises a second transistor (MP2,20) for actively turning the SCR on by shorting the collector and emitter of one (10) of the bipolar transistors.

8. A circuit as claimed in claim 5, 6 or 7, wherein the transistor circuit comprises a MOSFET circuit.

9. An ESD protected device comprising: an input pad (54); at least one device (50) to be protected having a first terminal connected to the input pad(54); and an ESD protection circuit (52) as claimed in any preceding claim.

10. A method of providing ESD protection, comprising: controlling the triggering of a semiconductor controlled rectifier (30) (hereinafter "SCR") provided between first and second voltage supply terminals (12,16), such that: the SCR is turned on in response to a voltage surge on a first voltage supply terminal (12); and the SCR is turned off by an RC control circuit (32) after a delay following the voltage surge.