WO2008095390A1

WO2008095390A1 - An equipment for detecting the line fault of the pseudo wire emulation and a method thereof

Info

Publication number: WO2008095390A1
Application number: PCT/CN2007/070816
Authority: WO
Inventors: Huanhao Zou; Fei Guo; Jun Cai; Bing Liang
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2007-02-07
Filing date: 2007-09-28
Publication date: 2008-08-14
Also published as: CN101013928A; CN101013928B

Abstract

An equipment for detecting the line fault of the pseudo wire emulation includes a jitter buffer (41), a jitter buffer write and read pointer control circuit (42), a jitter buffer state judge circuit (43), a sequence number validity analyze circuit (44). A method for detecting the line fault of the pseudo wire emulation is also provided, including: a jitter buffer (41) which is used for buffering the received data packets is arranged in the network output side of the pseudo wire; the memory capacity of the data packets in the jitter buffer (41) is obtained, and it is judged that the fault is occurred when the memory capacity is below the predetermined threshold. Another method for detecting the line fault of the pseudo wire emulation is also provided in the present invention examples. The time for detecting the fault is reduced, the speed of the fault recovery is improved, the service interruption in the communication link is shortened and the load of the CPU is reduced by using the present invention.

Description

Device and method for realizing pseudowire simulation line fault detection

The present invention relates to a link failure detection technique, and more particularly to an apparatus and method for implementing a pseudowire simulation line fault detection. Background of the invention

The traditional quasi-synchronous digital series primary base group provided by traditional telecom operators for users

(E1) or the North American and Japanese quasi-synchronous digital series primary group (T1) leased line service is a typical Time Division Multiplexing (TDM) leased line service. The approximate business application model is shown in Figure 1. The ADM (Add Drop Multiplexer) in the figure is an add/drop digital multiplexer. The user accesses the Synchronous Optical Network (SONET/Synchronous Digital Hierarchy) through the ADM through the TDM line. SDH) In the synchronous transmission network, the SONET/SDH carries TDM private line service data from different users.

New operators are entering the field, and they are experimenting with new network technologies to provide similar business functions to compete with traditional operators. Among them, PseudoWire Emulation Edge to Edge (PWE3) technology can provide Frame Relay and Asynchronous Transfer Mode (Synchronous Transfer Mode) on the Packet Switch Network (PSN). ATM), Ethernet and other services. As a kind of packet switching network, Metro Ethernet is a metropolitan area network technology developed from Ethernet technology. New operators are trying to provide traditional telecom operators on Metro Ethernet through PWE3 pseudowire emulation technology. Provides business functions such as Frame Relay, ATM, TDM leased line.

TDM pseudowire emulation technology is such a technology to replace the traditional SDH/PDH service. It enables new operators to provide TDM leased line services based on their Metro Ethernet. That is, the backbone network carrying TDM leased line services is no longer a traditional SONET/SDH synchronous transmission network, but a metro Ethernet network. The function diagram of the TDM pseudowire emulation mode for transmitting TDM private line service data is shown in FIG. 2. In the metropolitan area network, the TDM private line service data is transmitted by establishing a TDM pseudowire inside the PSN tunnel, so that different TDM private lines are provided. The users can also realize interconnection and intercommunication through the packet switching network, and replace the TDM service transmission function of the original SONET/SDH network through the pseudowire technology of the packet switching network.

In the service communication process of the TDM pseudowire emulation technology, when the TDM pseudowire (PW) fails, the communication service will be interrupted and the communication data will be lost. Therefore, real-time monitoring of the operating state of the TDM pseudowire to obtain a fast fault perception can facilitate the communication system to detect problems and make corresponding remedial measures in the event of a line fault.

The existing TDM pseudowire fault detection methods are as follows: Multiprotocol Label Switching - Label Switched Path (MPLS LSP, MPLS LSP) Ping mode detection, Bidirectional Forwarding Detection (Bidirectional Forwarding Detection, BFD) and Multi Protocol Label Switching - Operations and Management (MPLS-OAM) mode monitoring. The principle of the detection method is that the device at one end of the TDM pseudowire periodically sends some data packets with a special identifier to the peer device, and may also need the peer device to reply to a specific response message when necessary. Periodically test and inspect the connectivity and fault conditions of TDM pseudowires. When the device at one end of the TDM pseudowire does not receive the TDM pseudowire link state check packet from the peer device within the specified time period of the protocol or does not receive the expected response packet, the link state is considered to be faulty. .

However, all of the above pseudowire fault detection techniques have a common disadvantage in that the fault perception speed is slow. The above pseudowire fault detection technology is constructed by constructing a link state control detection protocol. The message is periodically sent from the device at one end of the TDM pseudowire to the other end, and the received control is detected at the other end to perform timestamp and address analysis to complete the pseudowire fault perception. Since the task of constructing and analyzing the link state control detection protocol message is completed by the processor (CPU) in the device, if the failure detection time is attempted, the periodic detection message transmission speed must be increased, which will greatly increase. The burden of the processor is such that the periodic detection packets cannot be sent too frequently, and the fault perception speed is slow. Therefore, the fault sensing speed of the TDM pseudowire simulation technology is usually in the order of seconds, and the fault sensing speed is slow. Summary of the invention

Embodiments of the present invention provide a method and apparatus for implementing fault detection of a pseudowire line fault, which are used to implement fast detection of a pseudowire fault.

A device for implementing fault detection of pseudowire line faults, comprising:

a jitter buffer memory connected to the network exit side of the pseudowire for storing the received data packet;

And a jitter buffer state decision circuit, configured to acquire a storage capacity of the data packet in the jitter buffer memory, and determine that a pseudowire fault occurs when the storage capacity is lower than a predetermined threshold.

A method for implementing fault detection of pseudowire line faults, comprising:

Setting a jitter buffer memory for storing the received data packet on the network exit side of the pseudowire;

The storage capacity of the data packet in the jitter buffer memory is obtained, and a pseudowire failure is determined to occur when the storage capacity is below a predetermined threshold.

A method for implementing fault detection of a pseudowire emulation line includes: setting a jitter buffer memory for storing a received data packet on a network egress side of the pseudowire;

The sequence number of the data packet received by the jitter buffer memory is detected. When the sequence number is discontinuous, the pseudowire is determined to be faulty. The discontinuity of the sequence number specifically includes: the sequence number is hopped or disordered. An apparatus for implementing fault detection of a pseudowire line fault, comprising: a jitter buffer memory connected to a network exit side of a pseudowire for storing a received data packet;

The packet sequence number detecting unit is configured to detect a sequence number of the data packet received by the jitter buffer memory, and determine that the pseudowire fails when the sequence number is discontinuous.

The embodiment of the present invention sets a jitter buffer memory on the egress side of the packet switching network of the TDM pseudowire to buffer the data packet received from the network side, when the reception of the data packet is interrupted, or the serial number of the data packet occurs. The hopping indicates that the link of the TDM pseudowire is faulty, so that the line fault can be quickly detected and reported to the system for processing. The system can quickly recover the interrupted service through link switching. With the fault detection method of the embodiment of the present invention, the detection time is usually in the order of milliseconds, and the fault detection time is greatly shortened compared with the prior art, thereby improving the fault repair speed and shortening the service interruption time of the communication link. BRIEF DESCRIPTION OF THE DRAWINGS

1 is a schematic diagram of a service application model of a TDM private line service in the prior art;

3 is a schematic diagram of an implementation of an embodiment of the present invention;

4 is a structural diagram of a device for implementing pseudowire simulation line fault detection in an embodiment of the present invention; FIG. Mode for carrying out the invention

The present invention will be further described in detail below with reference to the accompanying drawings.

The embodiment of the present invention is configured to set a jitter buffer memory on the egress side of the packet switching network of the pseudowire for buffering data packets received from the network side, when the reception of the data packet is interrupted, or the sequence number of the data packet is hopped. The change indicates that the link of the pseudowire is faulty, so that the line fault can be quickly detected and reported to the system for processing. The system can quickly recover the interrupted service through link switching. According to the fault detection method of the embodiment of the present invention, the detection time is usually in the order of milliseconds, and the fault detection time is greatly shortened compared with the prior art, and the method does not require the CPU to separately construct the detection protocol packet, thereby reducing the work of the CPU. burden.

It can be appreciated that the embodiment of the present invention is not limited to the TDM service, and any service pseudowire state detection with a fixed BIT rate can be applied to the embodiment of the present invention. For convenience of description, the embodiments of the present invention are described in detail below by taking the TDM service as an example. However, those skilled in the art will appreciate that the following description is merely exemplary and is not intended to limit the scope of the invention.

The principle of the embodiment of the present invention is as follows: As shown in the pseudo-line service model of FIG. 3, the network is divided into two parts: a user network and an operator network, and the operator connects the network with the user equipment to provide the user with the network. Internet service. The carrier edge ( Provider Edge , ΡΕ ) connects the carrier network part and the user network part. PE_a is the device A at the edge of the carrier network, usually belongs to the operator, and PE_b is the device B at the edge of the carrier network, usually belonging to the operator.

In the network model shown in FIG. 3, when the TDM subscriber dedicated line service operates normally, there is always an uninterrupted constant rate bit stream existing on the TDM dedicated line leased by the user. The TDM pseudowire emulation technology uses a packet switching network to replace the traditional SONET/SDH transport network, providing TDM dedicated services for User A and User B. Between user A and PE_a and user B and The TDM subscriber line between PE_b has a constant bit TDM data stream, which is consistent with the use of SONET/SDH networks. However, on a packet switched network connecting PE_a and PE_b, there is no uninterrupted constant bit stream. The data will be encapsulated in a single data packet for delivery, each data packet has a corresponding serial number, so that the data packet is reconstructed according to the serial number at the receiving end, and the TDM constant bit stream is reconstructed according to the data packet, in different data. There is a delivery interval between packets, which is a transmission feature of the packet switching network.

In Figure 3, in the normal operation of the TDM leased line service, the process of sending data from user A to user B is as follows: User A sends a data stream to PE_a through the TDM subscriber line at a constant bit rate without interruption, and the data flow reaches PE_a. The time is encapsulated in a fixed-length data packet, and the data packet is delivered to PE_b according to the corresponding packet switching path through the packet switching network PE_a. Since the packet switched network is gearless, that is, a packet with the same address and receiving address, the transmission path may be different because the network node is routing for a single packet. This results in different data packets arriving at PE_b after they arrive at PE_b, which should be roughly equal. However, due to the processing delay of the intermediate nodes of the packet switching network or the length of the transmission path, and the network redundancy, This interval will also vary slightly. A small change in the arrival time interval of such a packet is called packet jitter. Sometimes, packets sent later may even arrive at the receiving end first. After the packet arrives at PE_b, it will be restored to a constant bit of TDM data stream, and then sent to user B through PE_b through the TDM subscriber line without interruption.

Since PE_a continuously receives the data stream sent by user A at a constant rate, PE_a can also send fixed-length data packets to PE_b at a constant speed, but these data packets may have a small time interval when transmitted in the packet-switched network. difference. These packets are transmitted to PE_b, which in turn arranges the packets in their sequence number sequence and restores them to a constant bit stream. When the packet switching network between PE_a and PE_b fails and the data packet cannot be correctly transmitted, the device in the PE_b position will be in a short time after the failure occurs. Because the correct data packet cannot be received and the existence of such a line fault is perceived, the time interval is on the order of milliseconds, which is far lower than the time when the prior art detects the line fault, and the embodiment of the present invention implements the fast fault based on this principle. Perceived.

Because the TDM private line service itself is an uninterrupted constant bit data stream service, regardless of whether the user A as the source sends information to the user B, the TDM user line always maintains a constant bit stream, so the PE_a is normally under normal conditions. The data packet is periodically sent to PE_b, and the fault state that the link may exist can be determined as long as PE_b senses the state that the expected data packet is not received by some device.

FIG. 4 is a structural diagram of an apparatus for implementing fault detection of a pseudowire emulation line in an embodiment of the present invention. The apparatus may be disposed in a device on the exit side of a packet switching network of a TDM pseudowire, for example, in FIG. 3, _& When the data is sent to PE_b, the device is set in PE_b, otherwise the PE_a is set. The device specifically includes:

The jitter buffer memory 41 is configured to store the received data packet. The memory is a core component of the detecting device shown in Fig. 4, and the line fault is detected based on the aforementioned implementation principle. On the one hand, it buffers the received data packet and receives the data packet sent by the backbone network on one side and saves it. Due to the inherent characteristics of the packet switching network, the delay of each packet passing through the packet switched network may be unstable, and the speed of reaching the jitter buffer 41 may also be slow. The jitter buffer memory 41 functions like a reservoir, receiving the data packets arriving at these shifts on one side, and on the other side, the packet data conversion module 48 reads the data packets from the jitter buffer memory 41 uniformly, in other words, The jitter buffer memory 41 acts as a reservoir, shifts the data packet, and transmits the received data packet at a uniform speed. On the other hand, when the packet switching network has a transmission failure, the packet delay is large, and the jitter buffer memory 41 is The packet is not received for a period of time, and since the packet data conversion module 48 continuously picks up the packet from the jitter buffer 41 at a constant speed, the packet in the jitter buffer 41 is less and less, when jitter occurs. The storage capacity of the buffer memory 41 is less than a critical value A value indicates that the network link has failed. The setting of the threshold is based on different network environments and application scenarios. In this embodiment, it can be set to 1/4 full or empty, that is, when the jitter buffer memory 41 reaches 1/4 full or empty, it can be asserted that the network link has failed.

In addition, in the embodiment of the present invention, there are two methods for obtaining the storage capacity of the jitter buffer memory 41. One is to subtract the write pointer from the read pointer according to the position of the read/write pointer of the jitter buffer memory 41, thereby storing The number of data packets, that is, the storage capacity of the jitter buffer memory 41; another way is to set a flag bit register in the jitter buffer memory 41, specifically for storing the storage state of the jitter buffer memory 41, such as 1/4 full, 1 /2 is full, or is empty, etc. According to the storage state, the storage capacity of the jitter buffer memory 41 can also be obtained.

a jitter buffer read/write pointer control circuit 42 configured to control a position offset of a read pointer and a write pointer of the jitter buffer memory 41, and send a positional parameter of the read pointer and the write pointer and a storage state of the jitter buffer memory 41 to the The jitter buffer state decision circuit 43. The jitter buffer memory 41 is implemented in the form of a queue, and its storage characteristic is first in, first out, that is, the data packet that is first stored is read first. After entering the jitter buffer memory 41, the data packet is stored in the form of a linked list, the read pointer points to the data packet currently waiting to be read, and the write pointer points to the storage unit that can store the new incoming data packet. The jitter buffer read/write pointer control circuit 42 implements position control of the read pointer and the write pointer. When a new data packet is stored in the jitter buffer memory 41, the jitter buffer read/write pointer control circuit 42 controls the write pointer to move a memory. The unit, pointing to the next empty memory unit, when a data packet is read, the jitter buffer read/write pointer control circuit 42 controls the read pointer to move a memory unit to point to the next data packet to be read.

The jitter buffer state decision circuit 43 is configured to obtain, by the jitter buffer read/write pointer control circuit 42, the position parameters of the read pointer and the write pointer and the storage state of the jitter buffer memory, and determine whether a line fault occurs according to the storage state. . By reading the positional parameters of the pointer and the write pointer, the storage capacity of the jitter buffer memory 41 can be known, and how many memory lists are available. The element has been occupied, and how many memory cells are empty, and the division ratio of the memory cells of the jitter buffer memory 41 can be obtained by dividing the cell. When the ratio reaches the threshold value, the external processor 45 in FIG. 4 transmits an interrupt signal. For example, when the threshold value is set to 1/4 full, if the jitter buffer state decision circuit 43 detects that the occupancy ratio reaches 1/4, an interrupt signal is sent to the central processor; when the threshold is When the value is set to null, if the jitter buffer state decision circuit 43 detects that the read pointer and the write pointer coincide, an interrupt signal is transmitted. Alternatively, the storage state in the register can be read by the flag bit register in the jitter buffer memory 41, and the storage capacity of the jitter buffer memory 41 can be directly obtained, such as 1/4 full or empty.

The sequence number legality analysis circuit 44 is configured to determine whether a line fault has occurred based on the legitimacy of the sequence number of the data packet stored in the jitter buffer memory 41. The component uses the method of detecting the serial number of the data packet to perform fault detection, because it can be known through the foregoing principle analysis that when the packet switching network fails, the data packet is sometimes lost, or some data packets have a large delay, which causes As a result, the packet arriving at the jitter buffer memory 41 sometimes hops because the lost packet cannot be received, or the order of the received packet is confusing, unlike the order in which the packet is sent, because some packets are delayed. Large time, delayed reception. These problems can be detected by the serial number, because at the transmitting end, the data packets are consecutively numbered, and if the serial number jumps or confuses at the receiving end, it indicates that the link is faulty.

The serial number legality analysis circuit 44 can extract the serial number of each data packet stored in the jitter buffer memory 41 for detection, and if it detects an illegal situation, it reports to the central processing unit and transmits an interrupt signal thereto. In some application scenarios, the fault can be reported only in the event of a sequence number hop, and the packets with spoofed sequence numbers are reordered in the jitter buffer 41, which can reduce the number of interruptions of the central processor. In addition, for further To reduce the load on the central processor, in some applications, you can also set a tolerance for the serial number error, such as 1 minute, no interrupt is sent within 1 minute of detecting the serial number error, if the serial number is still detected after 1 minute. The error was reported to the central processor.

Preferably, the apparatus may further include a central processing unit 45, which may also be referred to as an external processor, for reading the status of the read pointer and the write pointer of the jitter buffer memory and receiving the result.

The processor management interface 46, the external processor 45 accesses the jitter buffer read/write pointer control circuit, the jitter buffer state decision circuit or the serial number legality analysis circuit through the processor management interface, where the processor management interface is used for maintaining channel selection Pass the data transfer direction.

The central processing unit 45 and the processor management interface 46 may be disposed in the apparatus shown in FIG. 4 or may be separately configured to perform other processing functions.

Further, the device may further include:

The packet front end processing module 47 is configured to receive the data packet sent by the packet switching network, analyze the validity of the data packet, and forward the legal data packet to the jitter buffer memory. The legality analysis includes calculating a checksum of the data packet, discarding the retransmission if the checksum is in error, and checking whether the length of the data packet is legal. In Ethernet, the packet length is between 64k and 1500k, exceeding This range is generally discarded.

The packet data transformation module 48 is configured to restore the data packet read from the jitter buffer memory to a TDM data stream.

The packet front end processing module 47 and the packet data conversion module 48 can also be separately provided without being integrated in the apparatus of FIG. For example, a plurality of status bits are set in the jitter buffer memory 41, and each bit represents a buffer status, such as a buffer empty, 1/4 full, half full, and a buffer full, etc., when the jitter buffer When the memory 41 reaches a certain state, the corresponding state position is set to 1. The jitter buffer state decision circuit 43 learns the state of the buffer by periodically detecting the corresponding status bit, thereby selecting to send an interrupt signal to the central processing unit according to a setting of a threshold value.

The device shown in Figure 4 can reduce the fault detection time of the TDM pseudowire emulation line to tens of milliseconds, realizing the fast perception of the fault, and thus improving the protection switching speed of the fault. In the application environment of FIG. 3, the device can be set in both PE_a and PE_b to implement bidirectional link fault sensing. The diagram includes the following steps:

Step 501: Pre-set a threshold value, which is 1/4 full or empty in this embodiment. Step 502: The jitter buffer memory receives the data packet sent by the packet switching network and stores the data unit pointed to by the write pointer, and the jitter buffer read/write pointer control circuit controls the write pointer to point to the next empty storage unit; the packet data transformation module reads the jitter. The data buffer pointed to by the read pointer in the buffer memory, the jitter buffer read/write pointer control circuit controls the read pointer to point to the next data packet to be sent to the user.

Step 503: The jitter buffer state decision circuit checks the storage capacity of the jitter buffer memory, determines whether the storage capacity reaches the threshold set in step 501, and if yes, indicates that a link failure occurs, and the jitter buffer state decision circuit is sent to the central processor. Send an interrupt signal.

Step 504: After receiving the interrupt signal, the central processing unit interrupts the current ongoing operation, and then performs a fault processing operation to switch the service to the standby link. The flow chart includes the following steps:

Step 601: The jitter buffer memory receives the data packet sent by the packet switching network and stores the data packet. Step 602: The sequence number legality analysis circuit extracts a sequence number of the data packet in the jitter buffer memory, and determines whether the sequence number occurs or is disordered in sequence. If yes, That indicates that there is a link Step 603: After receiving the interrupt signal, the central processing unit interrupts the current ongoing operation, and then performs a fault processing operation to switch the service to the standby link.

In addition to the above two methods, using the apparatus of Figure 4, the following two complementary schemes can also be used to detect link failure.

First, in the case that the primary and backup links of the TDM pseudowire exist at the same time, the fault of the primary link is detected by using the jitter buffer state and the sequence number legality method; and the manner of detecting the protocol packet is controlled by the existing constructed link state, For example, the MPLS LSP ping mode detects the status of the standby link. When the primary link detects a failure, it immediately switches to the alternate link if the alternate link is available. Because the jitter buffer detection method described in the schemes of FIG. 5 and FIG. 6 cannot detect the fault of the standby link, the composite detection method can simultaneously detect both the primary and backup links, and sweep out the detected blind spots. Improve the failure detection rate.

Second, in TDM pseudowire emulation applications, in some cases, the use of jitter buffer state detection may have certain limitations. When the link status is fast flashing, for example, during a thunderstorm, the strong lightning will cause the link to be interrupted for a short period of time. After a while, the link will return to normal, and the next lightning will cause an interruption. As a result, the cache empty state is frequently alternated, and the link state becomes very unstable at this time. In this case, the link state can be detected by using the existing transmit link detection protocol packet, and the link state detection packet can be sent back to the sender at the receiving end, and the sender can also be notified. The state of its link is unstable. The jitter buffer method is used as a trigger condition to trigger the link state detection message, which can reduce the burden on the processor. The processor does not need to periodically construct the detection packet for transmission, and only needs to send the detection packet detecting the link state after being triggered, which can greatly reduce the processing load of the processor.

According to the fault detection method described in the embodiment of the present invention, the detection time is usually in the order of milliseconds, which shortens the fault detection time, thereby improving the fault repair speed and shortening the communication link industry. The interrupt time is; and the method does not require the CPU to additionally construct a detection protocol message, thereby reducing the workload of the CPU.

In summary, the above description is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

Claim

What is claimed is: 1. A device for implementing fault detection of a pseudowire line fault, comprising: a jitter buffer memory connected to a network exit side of a pseudowire for storing a received data packet;

2. The apparatus for implementing a pseudowire emulation line fault detection apparatus according to claim 1, wherein the apparatus further comprises:

The sequence number legality analysis circuit is configured to determine whether a pseudowire fault occurs according to the validity of the sequence number of the data packet in the jitter buffer memory.

3. The apparatus for implementing pseudowire emulation line fault detection according to claim 1, wherein the jitter buffer memory includes a flag bit register for storing a storage state of the jitter buffer memory;

The jitter buffer state decision circuit is configured to acquire a storage capacity of the data packet in the jitter buffer memory according to a storage state of the jitter buffer memory.

The apparatus for implementing fault detection of a pseudowire emulation line according to claim 1 or 2, wherein the apparatus further comprises a jitter buffer read/write pointer control circuit,

The jitter buffer read/write pointer control circuit is configured to control a position offset of a read pointer and a write pointer of the jitter buffer memory, and send a position parameter of the read pointer and the write pointer to the jitter buffer state decision circuit ;

And a jitter buffer state decision circuit, configured to acquire a storage capacity of the data packet in the jitter buffer memory according to the position parameters of the read pointer and the write pointer.

The apparatus for implementing fault detection of a pseudowire line fault according to claim 4, wherein the apparatus further comprises:

An external processor, configured to read a read pointer and a write pointer of the jitter buffer memory And receiving a decision result of the jitter buffer state decision circuit on the line fault.

The apparatus for implementing fault detection of a pseudowire emulation line according to claim 5, wherein the external processor is further configured to receive a decision result of the serial number legality analysis circuit for a line fault.

The apparatus for implementing fault detection of a pseudowire emulation line according to claim 6, wherein the external processor accesses the jitter buffer read/write pointer control circuit, the jitter buffer status decision circuit, or the processor management interface. The serial number legality analysis circuit is configured to maintain channel gating and data transmission direction.

8. The apparatus for implementing fault detection of a pseudowire line fault according to claim 7, wherein the apparatus further comprises:

a packet front end processing module, configured to receive a data packet sent by the packet switching network, analyze the legality of the data packet, and forward the legal data packet to the jitter buffer memory; the packet data transformation module, The data packet read in the jitter buffer memory is restored to a data stream.

The apparatus for implementing pseudowire emulation line fault detection according to any one of claims 1-3, or 5-8, wherein the data packet is a TDM data packet.

A method for implementing fault detection of a pseudowire emulation line, comprising: setting, on a network exit side of the pseudowire, a jitter buffer memory for storing the received data packet;

The method for detecting a fault of a pseudowire line fault according to claim 10, wherein the determining that a pseudowire fault occurs when the storage capacity is lower than a predetermined threshold comprises:

When the storage capacity of the data packet in the jitter buffer memory reaches or is less than 1/4 full, it is determined that a pseudo line failure has occurred.

The method for detecting a fault of a pseudowire line fault according to claim 11, wherein the determining that a pseudowire fault occurs when the storage capacity is lower than a predetermined threshold comprises:

When the read pointer of the jitter buffer is equal to the write pointer, it is determined that a pseudo line failure has occurred.

The method for detecting a fault of a pseudo-wire emulation line according to claim 10, 11 or 12, wherein, when the pseudo-line emulation line fault detection method is used for the main link of the pseudo-wire, the method further includes:

For the standby link of the pseudowire, the link state control detection protocol packet is sent to detect the fault.

The pseudowire emulation line fault detection method according to claim 10, 11 or 12, wherein the method further comprises: when the storage capacity of the data packet in the jitter buffer memory is less than or equal to a first predetermined value and greater than The case where the second predetermined value occurs alternately, and when the number of times of alternating occurrence in the unit time reaches or exceeds the third predetermined value, the method of detecting the protocol using the transmission link state control detection protocol is triggered to perform fault detection.

A method for implementing fault detection of a pseudowire emulation line, comprising: setting a jitter buffer memory for storing a received data packet on a network exit side of the pseudowire; and detecting a data packet received by the jitter buffer memory The serial number, when the serial number is not continuous, determines that the pseudowire has failed.

The pseudowire emulation line fault detection method according to claim 15, wherein the sequence number discontinuity specifically comprises: the sequence number is hopping or disordered.

A device for implementing fault detection of a pseudowire line fault, comprising: a jitter buffer memory connected to a network exit side of the pseudowire for storing the received data packet;