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WO2008056614A1 - Reflow method, pattern-forming method, and method for manufacturing tft - Google Patents

Reflow method, pattern-forming method, and method for manufacturing tft Download PDF

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Publication number
WO2008056614A1
WO2008056614A1 PCT/JP2007/071416 JP2007071416W WO2008056614A1 WO 2008056614 A1 WO2008056614 A1 WO 2008056614A1 JP 2007071416 W JP2007071416 W JP 2007071416W WO 2008056614 A1 WO2008056614 A1 WO 2008056614A1
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WO
WIPO (PCT)
Prior art keywords
film
resist
reflow
surface modification
exposed
Prior art date
Application number
PCT/JP2007/071416
Other languages
French (fr)
Japanese (ja)
Inventor
Yutaka Asou
Tsutae Omori
Original Assignee
Tokyo Electron Limited
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Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Publication of WO2008056614A1 publication Critical patent/WO2008056614A1/en

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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/40Treatment after imagewise removal, e.g. baking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67109Apparatus for thermal treatment mainly by convection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67236Apparatus for manufacturing or treating in a plurality of work-stations the substrates being processed being not semiconductor wafers, e.g. leadframes or chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0231Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to a resist reflow method that can be applied in the manufacturing process of, for example, a thin film transistor (TFT), a pattern forming method using the resist, and a TFT manufacturing method.
  • TFT thin film transistor
  • An active matrix liquid crystal display device holds a liquid crystal sandwiched between a TFT substrate on which a thin film transistor (TFT) is formed and a counter substrate on which a color filter is formed, and applies a voltage selectively to each pixel. It is configured to be able to.
  • TFT substrate on which a thin film transistor (TFT) is formed
  • counter substrate on which a color filter is formed
  • a voltage selectively to each pixel It is configured to be able to.
  • a pattern of a photosensitive material such as a photoresist is repeatedly performed by a photolithography process, and thus a mask pattern is required for each photolithography process.
  • An example of a manufacturing procedure of a TFT substrate using such a half exposure technique is as follows. For example, an insulating film, an amorphous silicon film, an ohmic contour outer film, and a metal film are stacked so as to cover the gate electrode formed on the glass substrate. Thereafter, a pattern is formed by a half exposure process so that the resist film corresponding to the channel region is thin, and metal film etching and silicon etching (etching of the ohmic contact film and amorphous silicon film) are performed.
  • ashing re-development processing is carried out to reduce the resist film thickness as a whole As a result, the thin film portion of the resist is removed, and the metal film corresponding to the channel region is exposed. Then, the exposed metal film is etched to form a source electrode and a drain electrode, and the ohmic contact film is further etched to expose the semiconductor film in the channel region to form a TFT element. Then, after removing the resist, an organic film made of a photosensitive material is deposited on the TFT element, and a pattern is formed by photolithography to form a contact hole.
  • a conductive film such as indium tin oxide (ITO) is formed on the organic film, and the conductive film is etched using a resist patterned by a photolithography technique as a mask to form a transparent electrode.
  • ITO indium tin oxide
  • the TFT substrate is formed by the series of steps described above.
  • a silicon etching mask and an etching mask for forming the source electrode and the drain electrode can be formed in one photolithography process. . Therefore, the number of resist film formations can be reduced, and the amount of resist used can be reduced.
  • An object of the present invention is to provide a reflow method, a mask pattern forming method, and a mask pattern which can reduce the number of processes and the total process time while ensuring the accuracy of the mask pattern on the workpiece. It is to provide a manufacturing method of TFT.
  • the lower layer film is exposed to a lower layer film and an upper layer than the lower layer film.
  • Preparing an object to be processed having a resist film patterned so as to form an exposed region and a covering region coated with the lower layer film, and the lower layer film with respect to the object to be processed The exposed region of the substrate is subjected to surface modification treatment so that resist flow is suppressed, and after the surface modification treatment, the resist of the resist film is softened and flowed to partially cover the exposed region. And a reflow method is provided.
  • a resist film is formed in an upper layer than an etching target film of an object to be processed, the resist film is exposed, and the exposed resist film is formed.
  • Forming a resist pattern by developing, performing a surface modification process on the exposed region of the film to be etched where the resist is not formed, so as to suppress resist flow, and the surface modification
  • the resist of the resist film is softened and reflowed, and a reflow process for covering the target region of the film to be etched with the deformed resist is performed, and the deformed resist is used as a mask.
  • the first etching is performed on the exposed region of the etching film, the resist after the deformation is removed, and the resist after the deformation is removed. It said re-exposed by being includes performing the second etching with respect to the target region of the Etsu quenching film, a pattern forming method is provided.
  • a gate electrode is formed on a substrate, a gate insulating film covering the gate electrode is formed, and on the gate insulating film, a — Deposit Si film, Si film for ohmic contact and source / drain metal film, form a resist film on the source / drain metal film, and apply the resist film to a predetermined exposure mask.
  • the resist film subjected to the exposure treatment is developed to form a pattern to form a resist mask for the source electrode and a resist mask for the drain electrode, and the resist mask for the source electrode and the Etching the source / drain metal film using the drain electrode resist mask as a mask to form a source electrode and a drain electrode;
  • the exposed region of the Si film for ohmic contact that is not covered with the source electrode and the drain electrode is surface-modified so that the resist flow is suppressed, and the resist mask for the source electrode and By allowing an organic solvent to act on the resist mask for the drain electrode, softening the resist, and reflowing, Applying a reflow process for covering at least the Si film for ohmic contact in the recess for the channel region between the source electrode and the drain electrode with a resist deformed by reflow; and the resist and the source after deformation Etching the lower layer of the ohmic contact Si film and the a-Si film using the electrode and the drain electrode as a mask, removing the resist
  • a storage medium that operates on a computer and stores a program for controlling a reflow processing system, the program comprising: a lower layer film; and the lower layer film Preparing an object to be processed having a resist film patterned to form an exposed region where the lower layer film is exposed on the upper layer and a covered region covered with the lower layer film; A surface modification process is performed on the exposed body of the lower layer film so that resist flow is suppressed, and after the surface modification process, the resist film resist is softened and flowed.
  • a storage medium is provided for controlling the reflow processing system such that a reflow method including: partially covering the exposed area is performed.
  • a surface modification processing unit for performing a surface modification treatment on an object to be treated, and a resist on the object to be treated after the surface modification treatment in a solvent atmosphere.
  • a pattern is formed so as to form a reflow processing unit that is softened and fluidized, a lower layer film, an exposed region in which the lower layer film is exposed above the lower layer film, and a covered region that is covered with the lower layer film.
  • a reflow processing system comprising: a control unit that controls to partially cover the exposed region by softening and flowing the resist.
  • the exposed surface of the lower layer film is subjected to a surface modification process in advance so that the flow of the softened resist is suppressed. Can effectively suppress the spread of the gap. This makes it possible to adjust the area of the base film that is fluidized by the reflow process and is covered with the deformed resist.
  • the reflow method of the present invention to the manufacture of a semiconductor device such as a TFT element in which an etching process using a resist as a mask is repeatedly performed, high etching accuracy can be ensured, and the high performance of the semiconductor device can be ensured. It is possible to cope with integration and miniaturization. In addition, it is possible to reduce the number of resists and reduce the number of photolithography processes without requiring half exposure processing or re-development processing.
  • FIG. 1 is a schematic diagram showing a reflow processing system in which a reflow method of the present invention is implemented.
  • FIG. 2 is a cross-sectional view showing a schematic configuration of an adhesion unit (AD) mounted on the reflow system of FIG.
  • AD adhesion unit
  • FIG. 3 is a sectional view showing a schematic configuration of a reflow processing unit (REFLW) mounted on the reflow processing system of FIG.
  • REFLW reflow processing unit
  • FIG. 5B is a process cross-sectional view for explaining the reflow method of the present invention.
  • FIG. 5C is a process cross-sectional view for explaining a process of the reflow method of the present invention.
  • FIG. 7A is a cross-sectional view illustrating the principle of resist flow to a channel region in reflow processing.
  • FIG. 7B is a cross-sectional view for explaining the principle of resist flow to the channel region in the reflow process.
  • FIG. 8 is a flowchart showing an example of a manufacturing method of a TFT element for a liquid crystal display device to which the reflow method of the present invention is applied.
  • a process cross-sectional view for explaining a manufacturing method of the TFT element of FIG. 9B is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.
  • FIG. 9C is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • 9D is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.
  • FIG. 9E is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 9F is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 9G is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 9H is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 91 is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.
  • 9J is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.
  • FIG. 9K is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 9L is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.
  • FIG. 1 is a schematic plan view showing an entire reflow processing system that can be suitably used in the reflow method of the present invention.
  • the resist film formed on the surface of the glass substrate for LCD (hereinafter simply referred to as “substrate”) G is softened and deformed after development, and reused as an etching mask when etching the underlying film
  • a reflow processing system that includes a reflow processing unit that performs a reflow process for performing the reflow process and an adhesion unit that performs a surface modification process prior to the reflow process will be described as an example.
  • the reflow processing system 100 is configured so that the substrate G can be transferred to and from an external resist coating and developing processing system, exposure device, etching device, ashing device, etc. via a substrate transfer line (not shown). Has been.
  • the reflow processing system 100 includes a cassette station (loading / unloading unit) 1 on which a cassette C that accommodates a plurality of substrates G is placed, and a substrate G with a reflow process and a surface modification process performed prior to the reflow process.
  • a processing station (processing unit) 2 including a plurality of processing units for performing a series of processing including the above, and a control unit 3 that controls each component of the reflow processing system 100 are provided.
  • the longitudinal direction of the reflow processing system 100 is the X direction
  • the direction orthogonal to the X direction on the horizontal plane is the Y direction.
  • the cassette station 1 is disposed adjacent to one end of the processing station 2.
  • This cassette station 1 is provided with a transfer device 11 for loading and unloading the substrate G between the cassette C and the processing station 2, and the cassette station 1 is loaded into and out of the cassette C from the outside. Is done.
  • the transport device 11 has a transport arm 11a that can move on a transport path 10 provided along the Y direction that is the arrangement direction of the cassettes C.
  • the transfer arm 11a is provided so as to be able to advance and retract and rotate in the X direction, and is configured to transfer the substrate G between the cassette C and the processing station 2.
  • the processing station 2 includes a plurality of processing units for performing a resist reflow process on the substrate G and a surface modification process as a pre-process. In each of these processing units, one substrate G is processed.
  • the processing station 2 basically has a central transport path 20 for transporting a substrate G extending in the X direction. Each processing unit is placed on both sides of the central transport path 20 with the central transport path 20 interposed therebetween. It is arranged to face 20th.
  • the central transport path 20 is provided with a transport device 21 for loading and unloading the substrate G to and from each processing unit, and is movable in the X direction, which is the arrangement direction of the processing units. It has a transport arm 21a. Furthermore, the transfer arm 21a is provided so as to be advanced and retracted in the Y direction, reciprocated in the vertical direction, and rotated, and is configured so that the substrate G can be transferred into and out of each processing unit. Yes.
  • Adhesion unit (AD) 30 is a representative of silylating agents such as HMDS (hexamethyldisilazane) and TMSDEA (N-trimethylsilyljetylamine) for substrate G prior to reflow treatment.
  • HMDS hexamethyldisilazane
  • TMSDEA N-trimethylsilyljetylamine
  • adhesion unit (AD) 30 will be described with reference to FIG.
  • the adhesion unit (AD) 30 has a rectangular parallelepiped frame (not shown), and has a fixed chamber main body 31 and a lid 33 that can be raised and lowered inside the frame.
  • the chamber body 31 is configured as a flat, rectangular parallelepiped lower container having an upper surface that is slightly larger in size than the substrate G.
  • the lid 33 is configured as an upper container of a flat rectangular parallelepiped opening on the lower surface of substantially the same size (area) as the chamber body 31, and an HMDS supply source for storing HMDS used for surface modification as described later Connected to 35.
  • the lid 33 is fixed to a plurality of horizontal support members 37 extending in the horizontal direction (X direction and Y direction), and each horizontal support member 37 is provided with an elevating drive mechanism (not shown) such as a plurality of air. It is connected to the piston rod of the cylinder. Therefore, when the piston rods of these air cylinders are advanced vertically upward, the lid 33 moves (rises) integrally with the horizontal support member 37, and the chamber is opened. When the piston rod is retracted vertically downward, the lid 33 moves (lowers) together with the horizontal support member 37 vertically (!).
  • a rectangular heating plate 41 having a size substantially corresponding to the substrate G is horizontally disposed and fixed by a fixture 42.
  • the heating plate 41 is made of a metal having a high thermal conductivity, such as aluminum, and a heater (not shown) made of, for example, a resistance heating element is provided on the inside or the lower surface thereof.
  • the heating plate 41 is formed with a plurality of through holes 43, and each through hole 43 is provided with a lifter pin 44, and a substrate lifting mechanism 45 that lifts and lowers the substrate G up and down. Is provided. These lifter pins 44 project from the surface of the heating plate 41 between the transfer arm 21a (see FIG. 1) of the external transfer device 21 so that the substrate G can be delivered.
  • the lifter pins 44 are connected to each other by a horizontal support plate 46 disposed under the heating plate 41, and are configured to be able to move up and down synchronously. It should be noted that a lifting drive unit force (not shown) for moving the horizontal support plate 46 up and down is disposed inside or outside the chamber body 31.
  • a seamless seal member 3 extending in the circumferential direction is formed on the upper end surface of the side wall of the chamber body 31. 2 is installed.
  • the sealing member 32 is interposed between the lower end surface of the side wall of the lid 33 and the upper end surface of the side wall of the chamber body 31 in a state in which the lid 33 is combined with the chamber body 31 so that the lid 33 can be closed tightly. .
  • an airtight processing chamber 47 is formed by the chamber body 31 and the lid 33.
  • An HMDS gas introduction port 48 is provided on one side surface of the lid 33, and an exhaust port 49 is provided on the other side surface facing the HMDS gas introduction port 48.
  • the HMDS gas introduction port 48 includes a plurality of through holes 50 formed at an arbitrary interval on one side surface of the lid 33, a terminal adapter 53 of the gas supply pipe 51 attached to each through hole 50 from the outside, and each And a buffer chamber 54 provided inside the through hole 50 and having a large number of gas discharge ports 55 formed at regular intervals.
  • the exhaust port 49 has a large number of air holes 56 formed at regular intervals on the side surface of the lid 33 facing the HMDS gas introduction port 48, and is provided outside the side wall of the lid 33. It has an exhaust duct chamber 57. An exhaust port 58 formed at the bottom of the exhaust duct chamber 57 is connected to an exhaust pump (not shown) through an exhaust pipe 59.
  • the transport arm 21a of the transport device 21 is brought up with the lifter pins 44 of the substrate lift mechanism 45 raised. Receives board G from Then, after the lifter pin 44 is lowered and the substrate G is placed on the calo heat plate 41, the lid 33 is vertically lowered from the retracted position and brought into contact with the chamber body 31 to seal the chamber.
  • the substrate G is heated by the heating plate 41 to a predetermined temperature, for example, 110 ° C. to 120 ° C.
  • the HMDS gas is supplied from the HMDS supply source 35 to the processing chamber 47 through the gas supply pipe 51 and the HMDS gas introduction port 48 while exhausting the inside of the processing chamber 47 by an exhaust pump (not shown).
  • an HMDS gas force S ejected from the gas discharge port 55 of the HMDS gas introduction port 48 and an air flow toward the exhaust port 49 are formed, and the surface of the substrate G (processed surface) in the middle To modify the surface.
  • the HMDS gas that has passed through the processing chamber 47 is sent from the vent hole 56 to the exhaust duct chamber 57 at the exhaust port 49 and is exhausted therefrom by the action of the exhaust pump.
  • supply of HMDS gas and exhaust pump After the prescribed treatment time has elapsed and the surface modification treatment is completed, supply of HMDS gas and exhaust pump Then, the lid 33 is pulled upward from the chamber main body 31 by the ascending drive of a lifting drive mechanism (not shown) and lifted up to a predetermined retracted position as it is. Thereafter, the lifter pin 44 of the substrate lifting mechanism 45 is raised, the substrate G is lifted above the heating plate 41, and transferred to the transfer arm 21 a of the transfer device 21. Thereafter, the substrate G after the surface modification treatment is unloaded from the adhesion unit (AD) 30 by the transfer arm 21a.
  • AD adhesion unit
  • the substrate G after the surface modification treatment is then carried into the reflow treatment unit (REFLW) 60 of the treatment station 2 by the transfer arm 21a, and the resist formed on the substrate G is removed from the organic solvent such as a thinner atmosphere.
  • a reflow process is performed to soften and change the mask shape.
  • FIG. 3 is a schematic sectional view of the reflow processing unit (REFLW) 60.
  • the reflow processing unit (HREFLW) 60 has a chamber 61, and this chamber 61 is composed of a lower chamber 61a and an upper chamber 61b abutting on the upper portion of the lower chamber 61a.
  • the upper chamber 61b and the lower chamber 61a are configured to be opened and closed by an opening / closing mechanism (not shown), and the substrate G is loaded and unloaded by the transfer device 21 when the chamber is open.
  • a support table 62 that supports the substrate G horizontally is provided in the chamber 61.
  • the support table 62 is made of a material having excellent thermal conductivity such as aluminum!
  • the support table 62 is driven by a lift mechanism (not shown) and lifts and lowers the substrate G.
  • Three lift pins 63 (only two are shown in FIG. 3) 1S Provided so as to penetrate the support table 62 It has been.
  • the lift pins 63 lift the substrate G from the support table 62 and support the substrate G at a predetermined height position.
  • the tip of the support table 62 is held at the same height as the upper surface.
  • Exhaust ports 64a and 64b are formed at the bottom of the lower chamber 61a, and an exhaust system 64 is connected to the exhaust ports 64a and 64b. Then, the atmospheric gas in the chamber 61 is exhausted through the exhaust system 64.
  • a temperature control medium flow path 65 is provided inside the support table 62.
  • a temperature control medium such as temperature control cooling water is supplied to the temperature control medium introduction pipe 65a. And is discharged from the temperature control medium discharge pipe 65b and circulated, and its heat (for example, cold heat) is transferred to the substrate G through the support table 62, whereby the processing surface of the substrate G is changed. The desired temperature is controlled.
  • the ceiling wall portion of the chamber 61 is provided so as to face the shower head 66 force support table 62.
  • a large number of gas discharge holes 66b are provided on the lower surface 66a of the shower head 66.
  • a gas introduction part 67 is provided at the upper center of the shower head 66, and the gas introduction part 67 communicates with a space 68 formed in the shower head 66.
  • a pipe 69 is connected to the gas inlet 67.
  • the pipe 69 is connected to a bubbler tank 70 that vaporizes and supplies an organic solvent such as thinner, and an open / close valve 71 is provided in the middle thereof.
  • An N gas supply pipe 74 connected to an N gas supply source (not shown) is provided at the bottom of the bubbler tank 70 as a bubble generating means for vaporizing the thinner.
  • the N gas supply pipe 74 has a mass flow controller 72 and an opening / closing valve 73.
  • the bubbler tank 70 is provided with a temperature adjusting mechanism (not shown) for adjusting the temperature of the thinner stored therein to a predetermined temperature. Then, N gas is supplied from an N gas supply source (not shown) while the flow rate is controlled by the mass flow controller 72.
  • the thinner in the bubbler tank 70 By introducing it into the bottom of the blur tank 70, the thinner in the bubbler tank 70, the temperature of which has been adjusted to a predetermined temperature, can be vaporized and introduced into the chamber 61 via the pipe 69 and the gas inlet 67! /
  • each purge gas introduction portion 75 is filled with, for example, N gas as purge gas.
  • a purge gas supply pipe 76 for supplying the gas to the inside 61 is connected.
  • the purge gas supply pipe 76 is connected to a purge gas supply source (not shown), and an opening / closing valve 77 is provided in the middle thereof.
  • the reflow processing unit (REFLW) 60 having such a configuration, first, the upper channel 61b is released from the lower chamber 61a, and in this state, the transfer arm 21a of the transfer device 21 is opened. As a result, the substrate G having the resist that has already been patterned and subjected to the surface modification treatment is loaded and placed on the support table 62. Then, the upper chamber 61b and the lower chamber 61a are brought into contact with each other, and the chamber 61 is closed.
  • the flow rate of N gas is controlled by the mass flow controller 72 to control the vaporization amount of thinner.
  • the vaporized thinner is introduced into the space 68 of the shower head 66 from the bubbler tank 70 via the pipe 69 and the gas introduction part 67 and discharged from the gas discharge hole 66b.
  • the inside of the chamber 61 has a thinner atmosphere with a predetermined concentration.
  • a patterned resist is already provided on the substrate G placed on the support table 62 in the chamber 61, the resist is exposed to a thinner atmosphere. Penetrates the resist. As a result, the resist is softened and its fluidity is increased, and the resist is deformed and a predetermined region (target region) on the surface of the substrate G is covered with the deformed resist.
  • the temperature adjustment medium into the temperature adjustment medium flow path 65 provided inside the support table 62, the heat is transferred to the substrate G via the support table 62, thereby The processing surface of the substrate G is controlled to a desired temperature, for example, 20 ° C.
  • the gas containing thinner discharged from the head 66 toward the surface of the substrate G contacts the surface of the substrate G, then flows toward the exhaust ports 64a and 64b, and is exhausted from the chamber 61 to the exhaust system 64.
  • the upper chamber 61b is opened from the lower chamber 61a, and the substrate G after the reflow process is carried out from the reflow process unit (REFLW) 60 by the transfer arm 21a in the reverse procedure.
  • REFLW reflow process unit
  • Three heating and cooling processing units (HP / COU 80a, 80b, and 80c have a hot plate unit (HP) that heats the substrate G and a cooling plate that cools the substrate G, respectively.
  • Unit (COL) force Multi-stage for example, 2 stages are stacked in a total of 4 stages (not shown) .
  • This heating / cooling processing unit (HP / COU 80a, 80b, 8 In Oc, the substrate G after the surface modification treatment and the reflow treatment is subjected to heat treatment or cooling treatment as necessary.
  • each component of the reflow processing system 100 is configured to be connected to and controlled by a controller 90 having a CPU of the controller 3.
  • a user interface 91 consisting of a keyboard on which an operator inputs commands to manage the reflow processing system 100, a display that visualizes and displays the operating status of the reflow processing system 100, and the like. Has been.
  • the controller 90 stores a storage unit storing a recipe in which programs for executing various processes executed by the reflow processing system 100 under the control of the controller 90 and processing condition data are recorded. 92 is connected.
  • the reflow processing system 100 is controlled under the control of the controller 90 by calling an arbitrary recipe from the storage unit 92 according to an instruction from the user interface 91 and causing the controller 90 to execute it.
  • the desired processing at is performed.
  • the recipe may be stored in a computer-readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a flash memory, or may be dedicated from another device, for example. It is also possible to use it by transmitting it through the line at any time.
  • the cassette station 1 the cassette in which the transfer arm 11 a of the transfer apparatus 11 contains the substrate G on which a resist pattern has already been formed. Access C and take out one board G.
  • the substrate G is transferred from the transfer arm 11a of the transfer device 11 to the transfer arm 21a of the transfer device 21 in the central transfer path 20 of the processing station 2, and is transferred into the adhesion unit (AD) 30 by the transfer device 21.
  • the substrate G is taken out of the adhesion unit (AD) 30 by the transfer device 21, and is heated and cooled.
  • each heating / cooling processing unit (HP / COL) 80a, 80b, 80c is carried into the reflow processing unit (REF LW) 60, where the reflow process is performed.
  • the heating and cooling processing units (HP / COUs 80a, 80b, and 80c are subjected to predetermined heating and cooling processes as necessary.
  • Substrate G after such a series of processes has been completed. Is taken out from the reflow processing unit (REFLW) 60 by the transfer device 21, delivered to the transfer device 11 of the cassette station 1, and stored in an arbitrary cassette C.
  • FIG. 4A to 4C are process cross-sectional views for explaining a comparative reflow method.
  • a gate electrode 202 and a gate line are formed on an insulating substrate 201 made of a transparent substrate such as glass.
  • a gate insulating film 203 such as a silicon nitride film, a-Si (amorphous (Silicon) film 204, ⁇ + Si film 205 as an ohmic contact layer, source electrode 206a and drain electrode 206b, source electrode resist mask 210 and drain electrode resist mask 211 are laminated in this order.
  • the source electrode 206a and the drain electrode 206b are etched using the source electrode resist mask 210 and the drain electrode resist mask 211 as a mask, and the surface of the n + Si film 205 as the base film is exposed.
  • the object to be processed having such a laminated structure is subjected to a reflow process in a solvent atmosphere such as thinner in the reflow process unit (REFLW) 60 of the reflow process system 100.
  • a reflow process in a solvent atmosphere such as thinner in the reflow process unit (REFLW) 60 of the reflow process system 100.
  • the resist constituting the source electrode resist mask 210 and the drain electrode resist mask 211 is softened and has fluidity.
  • the surface of the n + Si film 205 in the recess 220 (channel formation region) between the source electrode 206a and the drain electrode 206b is covered with the fluidized deformation resist 212.
  • This process is the purpose of preventing the n + Si layer 205 and the a- Si film 204 in the next step when etched ring, n + Si layer 205 and the a- Si film 204 of the channel formation region is etched Done in
  • the photolithography process can be omitted by reflowing the resist constituting the resist mask for source electrode 210 and the resist mask for drain electrode 211 and reusing the resist mask.
  • the surface of the base n + Si film 205 may extend beyond the area of the electrode 206a and the drain electrode 206b. That is, the deformed resist 212 that serves as a mask when etching the n + Si film 205 and the a-Si film 204 in the next process protrudes beyond the area of the lower source electrode 206a and drain electrode 206b, and covers it. The area will spread. If the n + Si film 205 and the a-Si film 204 are etched in this state, there arises a problem that the etching accuracy is lowered. That is, as shown in FIG.
  • the side surfaces of the n + Si film 205 and the a-Si film 204 after etching and the side surfaces of the source electrode 206a or the drain electrode 206b are not flush with each other, resulting in a step.
  • the TFT is manufactured by performing the following steps with the n + Si film 205 and the a-Si film 204 as a base protruding in the lateral direction with respect to the source electrode 206a or the drain electrode 206b.
  • the aperture ratio which represents the rate of light passing through, decreases, and photocurrent is generated by light striking the a-Si film 204 at this protruding part, increasing electrical noise and generating leakage current. There is concern that it will cause adverse effects.
  • FIGS. 5A to 5D are process cross-sectional views for explaining the reflow method of the present invention.
  • the laminated structure shown in FIG. 5A is the same as that in FIG.
  • the surface modification process is performed on the workpiece having such a laminated structure by the adhesion unit (AD) 30 of the reflow processing system 100.
  • the surface modification treatment By the surface modification treatment, the exposed surface of the n + Si film 205 not covered with the source electrode 206a and the drain electrode 206b (the source electrode resist mask 210 and the drain electrode resist mask 211) is surface-modified.
  • reflow treatment is performed in a reflow treatment unit (REFLW) 60 in a solvent atmosphere such as thinner.
  • REFLW reflow treatment unit
  • the resist constituting the source electrode resist mask 210 and the drain electrode resist mask 211 is softened and has fluidity.
  • FIG. 5C the surface of the n + Si film 205 in the recess 220 (channel formation region) between the source electrode 206a and the drain electrode 206b is fluidized. Covered with deformation resist 212.
  • the fluidized resist is deformed, and the force that tries to spread over the surface of the underlying ⁇ + Si film 205 beyond the area of the source electrode 206 a and the drain electrode 206 b is already on the surface of the ⁇ + Si film 205. Since the modified surface 205a is formed by the modification, the flow of the softened resist is suppressed and the surface of the n + Si film 205 is difficult to spread.
  • the deformed resist 212 after reflow is formed as a source electrode in the lower layer.
  • the ⁇ + Si film 205 and the a-Si film 204 are etched using the deformed resist 212 as a mask, and after the deformed resist 212 is further removed, as shown in FIG.
  • the side surfaces of the film 205 and the a-Si film 204 and the side surfaces of the source electrode 206a or the drain electrode 206b can be formed substantially flush with each other. Therefore, the problems in the comparative reflow method, such as a decrease in aperture ratio due to the formation of the a-Si film 204 extending laterally from the source / drain wiring, an increase in electrical noise due to the generation of photocurrent, and the occurrence of leakage current, are addressed. Solve with power S.
  • Fig. 6 is a graph showing the test results of examining the effect of surface modification treatment on CD (Critical Dimension).
  • the vertical axis of the graph represents the amount of change ( ⁇ CD) between the resist pattern CD and the etched pattern CD, and the horizontal axis represents the time of the reflow process.
  • the surface modification treatment was performed using HMDS at a treatment temperature of 110 ° C for 120 seconds.
  • a light ashing process is performed on the deformed resist 212 to further reduce the area covered by the deformed resist 212, and the source electrode It becomes possible to make it closer to the area of 206a and the drain electrode 206b.
  • the ashing process uses, for example, a parallel plate type plasma processing apparatus, and an acid such as O.
  • This light ashing process which can be carried out under the conditions of a chamber gas pressure of about 13 Pa and a processing time of about 100 seconds, is performed by the plasma of the gas containing elemental gas.
  • This part of the deformed resist 212 protrudes from the source electrode 206a and the drain electrode 206b. Therefore, the effect on the etching accuracy is almost a problem in a short time, for example, about two-thirds of the time required for etching, which is usually performed for the purpose of removing the resist thin film with half exposure technology. It will not be.
  • the ⁇ + Si film 205 and the a-Si film 204 are etched using the deformed resist 212 as a mask, the ⁇ + Si film 205 and the a-Si film 204 are isotropically etched.
  • the etching under such conditions as to proceed, it is possible to further suppress the phenomenon that the n + Si film 205 and the a-Si film 204 protrude laterally from the source electrode 206a and the drain electrode 206b after the etching.
  • a plasma processing apparatus such as a parallel plate method is used, and as an etching gas type, for example, SF, C1 gas, etc.
  • Fig. 7A is a diagram showing a modeled state of resist flow during reflow processing without surface modification treatment
  • Fig. 7B shows resist flow during reflow processing with surface modification processing. It is a figure which models and shows a state. In these figures, the velocity of viscous flow during reflow and the velocity of flow due to surface tension are indicated by the size of the arrows.
  • the reflow speed is determined by the viscous flow of the softened resists 210a and 21 la and the surface tension of the resists 210a and 211a fused in the recess 220. As shown in FIG. 7A, when the surface modification treatment is not performed, the resists 210a and 211a softened quickly by the viscous flow and the flow due to the surface tension are formed in the recesses between the source electrode 206a and the drain electrode 206b. The resists 210a and 21la softened by the viscous flow spread to the outer regions of the flowing-in source electrode 206a and the drain electrode 206b.
  • the surface modification treatment is performed on the entire surface of the ⁇ + Si film 205 that is not covered by the source electrode 206a and the drain electrode 206b, so that the outside of the source electrode 206a and the drain electrode 206b.
  • the surface of the n + Si film 205 in the recess 220 exposed between the source electrode 206a and the drain electrode 206b is also surface-modified to form a surface-modified surface 205a. The speed of the viscous flow in that portion is also suppressed.
  • the inflow speed of the resists 210a and 21 la into the recesses 220 is mutually changed into the recesses 220 formed only by the viscous flow of the resists 210a and 21 la softened by the reflow process.
  • it is also affected by the flow promotion effect due to surface tension when resists 210a and 21 la that flowed in from the opposite direction come into contact.
  • the resist 210a, 211a smoothly flows in due to the surface tension after the resist 210a, 211a comes into contact with the directional force into the recess 220. Then, as shown in FIG. 7B, the directional force and flow to the surface modification surface 205a outside the recess 220 (outside the source electrode 206a and the drain electrode 206b) are suppressed, while the resist in the recess 220 is suppressed.
  • the inflow of 210a and 211a proceeds rapidly due to surface tension. With such a mechanism, even after the surface modification treatment, the flow rates of the resists 210a and 21la inside and outside the recess can be made to have a difference.
  • FIG. 8 is a flowchart showing an example of a manufacturing method of a TFT element for a liquid crystal display device to which the reflow method of the present invention is applied
  • FIGS. 9A to 9L are cross-sectional views for explaining the manufacturing method.
  • a gate electrode 202 and a gate line are formed on an insulating substrate 201 made of a transparent substrate such as glass, and a gate insulating film 203 such as a silicon nitride film, a-Si (amorphous (Silicon) film 204, ⁇ + Si film 205 as ohmic contact layer, and metal film 206 for electrodes such as A1 alloy and Mo alloy are stacked in this order (step)
  • a resist 207 is formed on the electrode metal film 206 (step
  • the resist 207 is exposed (step S3).
  • the exposure mask 300 is configured so that the resist 207 can be exposed in a predetermined pattern. By exposing the resist 207 in this manner, an exposed resist portion 208 and an unexposed resist portion 209 are formed as shown in FIG. 9D.
  • the exposed resist portion 208 is removed and the unexposed resist portion 209 can remain on the electrode metal film 206 as shown in FIG. 9E. Yes (step S4).
  • the unexposed resist portion 209 is separated into a source electrode resist mask 210 and a drain electrode resist mask 211 and is patterned.
  • the electrode metal film 206 is etched, and as shown in FIG. 9F, a recess 220 is formed in a portion that later becomes a channel region. Form (step S5).
  • the source electrode 206a and the drain electrode 206b are formed, and the surface of the n + Si film 205 can be exposed in the recess 220 between them.
  • a surface modification process is performed on the exposed surface of the ⁇ + Si film 205 (step S6).
  • the surface of the ⁇ + Si film 205 is modified by the surface modification treatment using a silylating agent, etc., and as shown in FIG. 9G, the surface modification treated surface 205a having a contact angle with pure water of 50 degrees or more. Is formed. That is, a state in which the resist hardly flows is formed on the surface modification surface 205a of the ⁇ + Si film 205.
  • reflow processing is performed by the reflow processing unit (REFLW) 60 of FIG. 3 (step S 7).
  • a resist softened with an organic solvent such as a thinner is poured into a target recess 220 to be a channel region later.
  • the flow of the softened resist is suppressed on the surface modification surface 205a of the ⁇ + Si film 205.
  • the inflow of the softening resist is accelerated by the action of the surface tension in the recess 220 which will later become the channel region, and the recess 220 can be reliably covered.
  • FIG. 9H shows a state where the recess 220 is covered with the deformation resist 212.
  • the deformed resist 212 extends to, for example, the periphery of the source electrode 206a and the drain electrode 206b (on the side opposite to the recess 220), for example, an n + Si film 205 as an ohmic contact layer 205
  • the coated portion is not etched in the next silicon etching process, resulting in a problem that the etching accuracy is deteriorated and the TFT element is defective and the yield is lowered.
  • the area covered with the deformed resist 212 is designed to be estimated in advance, the area (dot area) required to manufacture one TFT element will increase, and the integration and miniaturization of TFT elements will increase. When it became difficult to respond to the problem, there was a problem!
  • the flow of the softened resist to the surface of the n + Si film 205 other than the recess 220 that becomes the channel region is suppressed by the surface modification treatment, and as shown in FIG. 9H.
  • the area covered with the deformation resist 212 is substantially limited to the recess 220, which is the target area for the reflow process. Therefore, it is possible to ensure high etching accuracy and cope with high integration and miniaturization of TFTs.
  • step S8 a light ashing process is performed on the deformed resist after the reflow.
  • this ashing process the area covered by the deformed resist 212 can be further reduced as shown in FIG. Therefore, the accuracy of the etching performed in the next step S9 can be significantly improved.
  • this ashing process is an optional process, and this ashing process may be omitted if there is little protrusion outside the deformed resist 212 after reflow (around the source electrode 206a and the drain electrode 206b). Touch with force S.
  • the n + Si film 205 and the a-Si film 204 are etched using the source electrode 206a, the drain electrode 206b, and the deformed resist 212 as an etching mask (step S9).
  • the deformed resist 212 is removed by a method such as a wet process using a resist stripping solution (step S10), and the source electrode 206a and the drain electrode 206b are exposed as shown in FIG. 9K.
  • step Sl using the source electrode 206a and the drain electrode 206b as an etching mask, the n + Si film 205 exposed in the recess 220 is etched (step Sl 1). As a result, a channel region 221 is formed as shown in FIG. 9L.
  • the source electrode 206 a ( A contact hole connected to the drain electrode 206b) is formed by etching (step S13), and then a transparent electrode is formed by indium tin oxide (ITO) or the like (step S14).
  • ITO indium tin oxide
  • the process of etching the electrode metal film 206 of Step S 5, and the n + Si film 205 and the a-Si film 204 of Step S 9 can be performed by the resist formed by one photolithography process, that is, the resist mask 210 for the source electrode, the resist mask 211 for the drain electrode, and the deformation resist 212, so that the number of photolithography processes can be increased. Reduction and savings can be achieved.
  • the surface modification process in step S6 ensures high etching accuracy, and can cope with high integration and miniaturization of TFT elements.
  • the manufacture of TFT elements using a glass substrate for LCD was taken as an example, but reflow processing of resist formed on a substrate such as another flat panel display (FPD) substrate or a semiconductor substrate is performed.
  • FPD flat panel display
  • the present invention can also be applied when performing
  • the reflow method of the present invention can be applied to a TFT manufacturing process in which half exposure technology and re-development processing are performed.
  • the present invention can be suitably used in the manufacture of semiconductor devices such as TFT elements.

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Abstract

There is prepared an object to be processed which has a foundation layer film and a resist film pattern-formed above the foundation layer film in such a manner that there are an exposed region where the foundation layer film is exposed and a covered region where the foundation layer film is covered. Then, the object to be processed is subjected to a surface modification treatment so that the exposed region of the foundation layer film is surface-modified to suppress fluxion of the resist. After this surface modification treatment, resist of the resist film is softened and flowed to partially cover the exposed region, and then etching is performed by using the flowed resist as a mask, thereby forming a certain pattern.

Description

明 細 書  Specification

リフロー方法、パターン形成方法および TFTの製造方法  Reflow method, pattern forming method, and TFT manufacturing method

技術分野  Technical field

[0001] 本発明は、例えば薄膜トランジスタ (TFT)などの製造過程で適用可能なレジストの リフロー方法、ならびにそれを用いたパターン形成方法および TFTの製造方法に関 する。  The present invention relates to a resist reflow method that can be applied in the manufacturing process of, for example, a thin film transistor (TFT), a pattern forming method using the resist, and a TFT manufacturing method.

背景技術  Background art

[0002] アクティブ ·マトリックス型液晶表示装置は、薄膜トランジスタ (TFT)を形成した TFT 基板と、カラーフィルタを形成した対向基板との間に液晶を挟み込んで担持し、画素 毎に選択的に電圧を印加できるように構成されている。ここで用いられる TFT基板の 作製過程では、フォトリソグラフィー工程によるフォトレジスト等の感光性材料のパター ユングが繰り返し行なわれるため、フォトリソグラフィー工程毎に、マスクパターンが必 要である。  [0002] An active matrix liquid crystal display device holds a liquid crystal sandwiched between a TFT substrate on which a thin film transistor (TFT) is formed and a counter substrate on which a color filter is formed, and applies a voltage selectively to each pixel. It is configured to be able to. In the process of manufacturing the TFT substrate used here, a pattern of a photosensitive material such as a photoresist is repeatedly performed by a photolithography process, and thus a mask pattern is required for each photolithography process.

[0003] しかし、近年では液晶表示装置の高集積化と微細化の進展に伴い、その製造工程 が複雑化しており、製造コストが増加する傾向にある。そこで、製造コストを低減すベ ぐフォトリソグラフィ一のためのマスクパターンの形成工程を統合させて全体の工程 数を削減することが検討されている。たとえば、露光マスクとして、光の透過率に差を 設けたハーフトーンマスクを用い、所謂ハーフ露光処理を行なうことにより、 1回の露 光工程で異なる膜厚を持つレジストマスクをパターン形成する技術が提案されている [0003] However, in recent years, with the progress of high integration and miniaturization of liquid crystal display devices, the manufacturing process has become complicated, and the manufacturing cost tends to increase. Therefore, it has been studied to reduce the total number of processes by integrating the mask pattern formation process for photolithography, which should reduce the manufacturing cost. For example, using a halftone mask with a difference in light transmittance as an exposure mask and performing so-called half-exposure processing, a technique for patterning resist masks with different film thicknesses in a single exposure process is available. Proposed

(例えば、特開平 9— 80740号公報、特開 2005— 108904号公報)。 (For example, JP-A-9-80740, JP-A-2005-108904).

[0004] このようなハーフ露光技術を利用した TFT基板の製造手順の一例を示すと以下の とおりである。例えばガラス基板上に形成したゲート電極を覆うように絶縁膜、ァモル ファスシリコン膜、ォーミックコンタ外膜、金属膜を積層して成膜する。その後、ハー フ露光処理によりチャンネル領域に対応する部分のレジスト膜厚が薄くなるようにパ ターン形成し、金属膜エッチング、シリコンエッチング (ォーミックコンタクト膜およびァ モルファスシリコン膜のエッチング)を行なう。 [0004] An example of a manufacturing procedure of a TFT substrate using such a half exposure technique is as follows. For example, an insulating film, an amorphous silicon film, an ohmic contour outer film, and a metal film are stacked so as to cover the gate electrode formed on the glass substrate. Thereafter, a pattern is formed by a half exposure process so that the resist film corresponding to the channel region is thin, and metal film etching and silicon etching (etching of the ohmic contact film and amorphous silicon film) are performed.

[0005] その後、例えばアツシングゃ再現像処理を実施し、レジストの膜厚を全体的に減少 させることにより、レジストの薄膜部が除去されてチャンネル領域に対応する部分の金 属膜を露出させる。そして、露出した金属膜をエッチングしてソース電極およびドレイ ン電極を形成するとともに、さらにォーミックコンタクト膜をエッチングし、チャンネル領 域に半導体膜を露出させて TFT素子を形成する。そして、レジストを除去した後、 TF T素子の上に感光性材料からなる有機膜を堆積させ、フォトリソグラフィー技術によつ てパターン形成し、コンタクトホールを形成する。さらに有機膜の上にインジウム '錫 酸化物 (ITO)等の導電性膜を形成し、フォトリソグラフィー技術によってパターン形 成されたレジストをマスクとして該導電性膜をエッチングして透明電極を形成する。以 上の一連の工程により、 TFT基板が形成される。 [0005] After that, for example, ashing re-development processing is carried out to reduce the resist film thickness as a whole As a result, the thin film portion of the resist is removed, and the metal film corresponding to the channel region is exposed. Then, the exposed metal film is etched to form a source electrode and a drain electrode, and the ohmic contact film is further etched to expose the semiconductor film in the channel region to form a TFT element. Then, after removing the resist, an organic film made of a photosensitive material is deposited on the TFT element, and a pattern is formed by photolithography to form a contact hole. Furthermore, a conductive film such as indium tin oxide (ITO) is formed on the organic film, and the conductive film is etched using a resist patterned by a photolithography technique as a mask to form a transparent electrode. The TFT substrate is formed by the series of steps described above.

[0006] 以上の過程では、ハーフ露光技術を利用することによって、シリコンエッチングのマ スクと、ソース電極およびドレイン電極を形成する際のエッチングマスクを一回のフォ トリソグラフィー工程で形成することができる。したがって、レジスト膜の形成回数が減 り、レジスト使用量を削減することが可能になる。  [0006] In the above process, by using the half exposure technique, a silicon etching mask and an etching mask for forming the source electrode and the drain electrode can be formed in one photolithography process. . Therefore, the number of resist film formations can be reduced, and the amount of resist used can be reduced.

[0007] ところで、上述したハーフ露光処理を利用した TFT基板の製造では、省レジスト化 と、フォトリソグラフィー工程数の削減を図ることが可能である力 その一方で、ハーフ 露光技術を利用すると、レジストの膜厚を全体的に減少させて薄膜部を除去するアツ シング処理や再現像処理が必要になる。  [0007] By the way, in the manufacture of a TFT substrate using the above-described half-exposure process, it is possible to save resist and reduce the number of photolithography processes. An ashing process or a re-development process for removing the thin film portion by reducing the overall film thickness is required.

[0008] アツシング処理を行なってレジストの薄膜部を除去する場合には、基板面内のバタ ーンの精度の均一性を確保することが困難である。再現像処理の場合は、現像液の 塗布を伴う液処理であることから、現像処理と再現像処理という別々の液処理が繰り 返される点でプロセスフローが複雑化して装置コスト'ランニングコストの増加につな がる。また、再現像処理の精度を確保するためには事前にレジストの表面変質層を 除去する前処理が必要であり、工程数の削減に限界がある。  [0008] When the thin film portion of the resist is removed by performing an ashing process, it is difficult to ensure the uniformity of the pattern accuracy within the substrate surface. In the case of redevelopment processing, since it is a liquid process that involves the application of a developer, the process flow becomes complicated due to the repetition of separate liquid processes of development and redevelopment processing, resulting in increased equipment costs and running costs. Lead to In addition, in order to ensure the accuracy of the redevelopment process, a pre-process for removing the altered surface layer of the resist in advance is necessary, and there is a limit to the reduction in the number of processes.

発明の開示  Disclosure of the invention

[0009] 本発明の目的は、被処理体におけるマスクパターンの精度を確保しながら、省レジ スト化並びに工程数、総工程時間の削減を図ることが可能なリフロー方法、マスクパ ターンの形成方法および TFTの製造方法を提供することにある。  An object of the present invention is to provide a reflow method, a mask pattern forming method, and a mask pattern which can reduce the number of processes and the total process time while ensuring the accuracy of the mask pattern on the workpiece. It is to provide a manufacturing method of TFT.

[0010] 本発明の第 1の観点によれば、下層膜と、該下層膜よりも上層に前記下層膜が露 出した露出領域と前記下層膜が被覆された被覆領域とが形成されるようにパターン 形成されたレジスト膜とを有する被処理体を準備することと、前記被処理体に対して、 前記下層膜の前記露出領域をレジストの流動が抑制されるように表面改質処理する ことと、表面改質処理後、前記レジスト膜のレジストを軟化させて流動させることにより 、前記露出領域を部分的に被覆することと、を含むリフロー方法が提供される。 [0010] According to the first aspect of the present invention, the lower layer film is exposed to a lower layer film and an upper layer than the lower layer film. Preparing an object to be processed having a resist film patterned so as to form an exposed region and a covering region coated with the lower layer film, and the lower layer film with respect to the object to be processed The exposed region of the substrate is subjected to surface modification treatment so that resist flow is suppressed, and after the surface modification treatment, the resist of the resist film is softened and flowed to partially cover the exposed region. And a reflow method is provided.

[0011] 本発明の第 2の観点によれば、被処理体の被エッチング膜より上層にレジスト膜を 形成することと、前記レジスト膜を露光処理することと、前記露光処理されたレジスト 膜を現像処理してレジストパターンを形成することと、前記被エッチング膜のレジスト が形成されていない露出領域に対してレジストの流動を抑制するように表面改質処 理を施すことと、 前記表面改質処理後、前記レジスト膜のレジストを軟化させてリフ ローさせ、それによつて変形したレジストにより前記被エッチング膜のターゲット領域 を被覆するリフロー処理を行うことと、変形後の前記レジストをマスクとして前記被エツ チング膜の前記露出領域に対して第 1のエッチングを行うことと、変形後の前記レジ ストを除去することと、変形後のレジストが除去されることにより再露出した前記被エツ チング膜のターゲット領域に対して第 2のエッチングを行なうことと、を含む、パターン 形成方法が提供される。  [0011] According to a second aspect of the present invention, a resist film is formed in an upper layer than an etching target film of an object to be processed, the resist film is exposed, and the exposed resist film is formed. Forming a resist pattern by developing, performing a surface modification process on the exposed region of the film to be etched where the resist is not formed, so as to suppress resist flow, and the surface modification After the treatment, the resist of the resist film is softened and reflowed, and a reflow process for covering the target region of the film to be etched with the deformed resist is performed, and the deformed resist is used as a mask. The first etching is performed on the exposed region of the etching film, the resist after the deformation is removed, and the resist after the deformation is removed. It said re-exposed by being includes performing the second etching with respect to the target region of the Etsu quenching film, a pattern forming method is provided.

[0012] 本発明の第 3の観点によれば、基板上にゲート電極を形成することと、 前記ゲート 電極を覆うゲート絶縁膜を形成することと、前記ゲート絶縁膜上に、下から順に a— Si 膜、ォーミックコンタクト用 Si膜およびソース'ドレイン用金属膜を堆積させることと、前 記ソース'ドレイン用金属膜上にレジスト膜を形成することと、前記レジスト膜を所定の 露光マスクを用いて露光処理することと、露光処理された前記レジスト膜を現像処理 してパターン形成し、ソース電極用レジストマスクおよびドレイン電極用レジストマスク を形成することと、前記ソース電極用レジストマスクおよび前記ドレイン電極用レジスト マスクをマスクとして前記ソース'ドレイン用金属膜をエッチングし、ソース電極とドレイ ン電極とを形成することと、前記ソース電極および前記ドレイン電極で被覆されて!/、 ない前記ォーミックコンタクト用 Si膜の露出領域をレジストの流動が抑制されるように 表面改質処理することと、前記ソース電極用レジストマスクおよび前記ドレイン電極用 レジストマスクに有機溶媒を作用させてレジストを軟化させ、リフローさせることにより、 少なくとも前記ソース電極と前記ドレイン電極との間のチャンネル領域用凹部内の前 記ォーミックコンタクト用 Si膜をリフローにより変形したレジストにより覆うリフロー処理 を施すことと、変形後の前記レジストならびに前記ソース電極および前記ドレイン電極 をマスクとして、下層の前記ォーミックコンタクト用 Si膜および前記 a— Si膜をエツチン グすることと、変形後の前記レジストを除去して、前記ソース電極と前記ドレイン電極と の間のチャンネル領域用凹部内に前記ォーミックコンタクト用 Si膜を再び露出させる ことと、前記ソース電極と前記ドレイン電極とをマスクとして、これらの間の前記チャン ネル領域用凹部に露出した前記ォーミックコンタクト用 Si膜をエッチングすることと、 を含む、 TFTの製造方法が提供される。 [0012] According to a third aspect of the present invention, a gate electrode is formed on a substrate, a gate insulating film covering the gate electrode is formed, and on the gate insulating film, a — Deposit Si film, Si film for ohmic contact and source / drain metal film, form a resist film on the source / drain metal film, and apply the resist film to a predetermined exposure mask. The resist film subjected to the exposure treatment is developed to form a pattern to form a resist mask for the source electrode and a resist mask for the drain electrode, and the resist mask for the source electrode and the Etching the source / drain metal film using the drain electrode resist mask as a mask to form a source electrode and a drain electrode; The exposed region of the Si film for ohmic contact that is not covered with the source electrode and the drain electrode is surface-modified so that the resist flow is suppressed, and the resist mask for the source electrode and By allowing an organic solvent to act on the resist mask for the drain electrode, softening the resist, and reflowing, Applying a reflow process for covering at least the Si film for ohmic contact in the recess for the channel region between the source electrode and the drain electrode with a resist deformed by reflow; and the resist and the source after deformation Etching the lower layer of the ohmic contact Si film and the a-Si film using the electrode and the drain electrode as a mask, removing the resist after the deformation, and removing the source electrode and the drain electrode The ohmic contact Si film is exposed again in the recess for the channel region between and the channel electrode recess exposed between the source electrode and the drain electrode as a mask. Etching a Si film for ohmic contact, and a method for manufacturing a TFT, including: .

[0013] 本発明の第 4の観点によれば、コンピュータ上で動作し、リフロー処理システムを制 御するプログラムが記憶された記憶媒体であって、前記プログラムは、下層膜と、該 下層膜よりも上層に前記下層膜が露出した露出領域と前記下層膜が被覆された被 覆領域とが形成されるようにパターン形成されたレジスト膜とを有する被処理体を準 備することと、前記被処理体に対して、前記下層膜の前記露出領域をレジストの流動 が抑制されるように表面改質処理することと、表面改質処理後、前記レジスト膜のレジ ストを軟化させて流動させることにより、前記露出領域を部分的に被覆することと、を 含むリフロー方法が行なわれるようにリフロー処理システムを制御する、記憶媒体が 提供される。 [0013] According to a fourth aspect of the present invention, there is provided a storage medium that operates on a computer and stores a program for controlling a reflow processing system, the program comprising: a lower layer film; and the lower layer film Preparing an object to be processed having a resist film patterned to form an exposed region where the lower layer film is exposed on the upper layer and a covered region covered with the lower layer film; A surface modification process is performed on the exposed body of the lower layer film so that resist flow is suppressed, and after the surface modification process, the resist film resist is softened and flowed. Thus, a storage medium is provided for controlling the reflow processing system such that a reflow method including: partially covering the exposed area is performed.

[0014] 本発明の第 5の観点によれば、被処理体に対して表面改質処理を行なう表面改質 処理ユニットと、表面改質処理後の被処理体上のレジストを溶剤雰囲気中で軟化さ せて流動化させるリフロー処理ユニットと、下層膜と、該下層膜よりも上層に前記下層 膜が露出した露出領域と前記下層膜が被覆された被覆領域とが形成されるようにパ ターン形成されたレジスト膜とを有する被処理体に対して、前記下層膜の前記露出 領域をレジストの流動が抑制されるように表面改質処理を行い、表面改質処理後、前 記レジスト膜のレジストを軟化させて流動させることにより、前記露出領域を部分的に 被覆するように制御する制御部と、を備えた、リフロー処理システムが提供される。  [0014] According to the fifth aspect of the present invention, a surface modification processing unit for performing a surface modification treatment on an object to be treated, and a resist on the object to be treated after the surface modification treatment in a solvent atmosphere. A pattern is formed so as to form a reflow processing unit that is softened and fluidized, a lower layer film, an exposed region in which the lower layer film is exposed above the lower layer film, and a covered region that is covered with the lower layer film. The object to be processed having the formed resist film is subjected to a surface modification process in the exposed region of the lower layer film so that the resist flow is suppressed, and after the surface modification process, There is provided a reflow processing system comprising: a control unit that controls to partially cover the exposed region by softening and flowing the resist.

[0015] 本発明によれば、リフロー処理に先立ち、軟化したレジストの流動が抑制されるよう に下層膜の露出面に予め表面改質処理を施すことにより、リフロー処理の際のレジス トの拡がりを効果的に抑制できる。これにより、リフロー処理によって流動化し、変形し たレジストによって被覆される下地膜の面積を調節することが可能になる。 [0015] According to the present invention, prior to the reflow process, the exposed surface of the lower layer film is subjected to a surface modification process in advance so that the flow of the softened resist is suppressed. Can effectively suppress the spread of the gap. This makes it possible to adjust the area of the base film that is fluidized by the reflow process and is covered with the deformed resist.

したがって、本発明のリフロー方法を、レジストをマスクにしたエッチング工程が繰り 返し行なわれる TFT素子などの半導体装置の製造に適用することにより、高いエツ チング精度を確保することができ、半導体装置の高集積化や微細化への対応を図る ことが可能になる。また、ハーフ露光処理や再現像処理を必要とせずに、省レジスト 化とフォトリソグラフィー工程数の削減を実現することができる。  Therefore, by applying the reflow method of the present invention to the manufacture of a semiconductor device such as a TFT element in which an etching process using a resist as a mask is repeatedly performed, high etching accuracy can be ensured, and the high performance of the semiconductor device can be ensured. It is possible to cope with integration and miniaturization. In addition, it is possible to reduce the number of resists and reduce the number of photolithography processes without requiring half exposure processing or re-development processing.

図面の簡単な説明 Brief Description of Drawings

[図 1]本発明のリフロー方法が実施されるリフロー処理システムを示す概略図。  FIG. 1 is a schematic diagram showing a reflow processing system in which a reflow method of the present invention is implemented.

[図 2]図 1のリフローシステムに搭載されたアドヒージョンユニット (AD)の概略構成を 示す断面図。  2 is a cross-sectional view showing a schematic configuration of an adhesion unit (AD) mounted on the reflow system of FIG.

[図 3]図 1のリフロー処理システムに搭載されたリフロー処理ユニット(REFLW)の概 略構成を示す断面図。  FIG. 3 is a sectional view showing a schematic configuration of a reflow processing unit (REFLW) mounted on the reflow processing system of FIG.

園 4A]比較リフロー方法を説明するための工程断面図。 4A] Cross-sectional process chart for explaining the comparative reflow method.

園 4B]比較リフロー方法を説明するための工程断面図。 4B] Cross-sectional process chart for explaining the comparative reflow method.

園 4C]比較リフロー方法を説明するための工程断面図。 4C] Cross-sectional process chart for explaining the comparative reflow method.

園 5A]本発明リフロー方法を説明するための工程断面図。 5A] Cross-sectional process chart for explaining the reflow method of the present invention.

[図 5B]本発明リフロー方法を説明するための工程断面図。  FIG. 5B is a process cross-sectional view for explaining the reflow method of the present invention.

[図 5C]本発明リフロー方法の工程を説明するための工程断面図。  FIG. 5C is a process cross-sectional view for explaining a process of the reflow method of the present invention.

園 5D]本発明リフロー方法の工程を説明するための工程断面図。 5D] Cross-sectional process chart for explaining the process of the reflow method of the present invention.

園 6]CDの変化量とリフロー時間との関係を示すグラフ。 Sono 6] A graph showing the relationship between CD variation and reflow time.

[図 7A]リフロー処理におけるチャンネル領域へのレジスト流動の原理を説明する断面 図。  FIG. 7A is a cross-sectional view illustrating the principle of resist flow to a channel region in reflow processing.

[図 7B]リフロー処理におけるチャンネル領域へのレジスト流動の原理を説明する断面 図。  FIG. 7B is a cross-sectional view for explaining the principle of resist flow to the channel region in the reflow process.

[図 8]本発明のリフロー方法を適用した液晶表示装置用 TFT素子の製造方法の一例 を示すフローチャート。  FIG. 8 is a flowchart showing an example of a manufacturing method of a TFT element for a liquid crystal display device to which the reflow method of the present invention is applied.

園 9A]図 8の TFT素子の製造方法を説明するための工程断面図。 [図 9B]図 8の TFT素子の製造方法を説明するための工程断面図。 9A] A process cross-sectional view for explaining a manufacturing method of the TFT element of FIG. 9B is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.

[図 9C]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9C is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 9D]図 8の TFT素子の製造方法を説明するための工程断面図。  9D is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.

[図 9E]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9E is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 9F]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9F is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 9G]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9G is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 9H]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9H is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 91]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 91 is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.

[図 9J]図 8の TFT素子の製造方法を説明するための工程断面図。  9J is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG. 8.

[図 9K]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9K is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

[図 9L]図 8の TFT素子の製造方法を説明するための工程断面図。  FIG. 9L is a process cross-sectional view for explaining the manufacturing method of the TFT element of FIG.

発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION

[0017] 以下、図面を参照しながら、本発明の好ましい形態について説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

図 1は、本発明のリフロー方法に好適に利用可能なリフロー処理システムの全体を 示す概略平面図である。ここでは、 LCD用ガラス基板(以下、単に「基板」と記す) G の表面に形成されたレジスト膜を、現像処理後に軟化させて変形させ、下層膜をエツ チングする際のエッチングマスクとして再使用するためのリフロー処理を行なうリフロ 一処理ユニットと、このリフロー処理に先だって表面改質処理を行なうアドヒージョン ユニットを備えたリフロー処理システムを例に挙げて説明することとする。このリフロー 処理システム 100は、図示しない基板搬送ラインを介して、外部のレジスト塗布 '現像 処理システムや露光装置、エッチング装置、アツシング装置などとの間で基板 Gの受 け渡しを行なえるように構成されている。  FIG. 1 is a schematic plan view showing an entire reflow processing system that can be suitably used in the reflow method of the present invention. Here, the resist film formed on the surface of the glass substrate for LCD (hereinafter simply referred to as “substrate”) G is softened and deformed after development, and reused as an etching mask when etching the underlying film A reflow processing system that includes a reflow processing unit that performs a reflow process for performing the reflow process and an adhesion unit that performs a surface modification process prior to the reflow process will be described as an example. The reflow processing system 100 is configured so that the substrate G can be transferred to and from an external resist coating and developing processing system, exposure device, etching device, ashing device, etc. via a substrate transfer line (not shown). Has been.

[0018] リフロー処理システム 100は、複数の基板 Gを収容するカセット Cを載置するカセット ステーション (搬入出部) 1と、基板 Gにリフロー処理およびこれに先行して行なわれる 表面改質処理を含む一連の処理を施すための複数の処理ユニットを備えた処理ス テーシヨン(処理部) 2と、リフロー処理システム 100の各構成部を制御する制御部 3と 、を備えている。なお、図 1において、リフロー処理システム 100の長手方向を X方向 、水平面上において X方向と直交する方向を Y方向とする。 [0019] カセットステーション 1は、処理ステーション 2の一方の端部に隣接して配置されてい る。このカセットステーション 1は、カセット Cと処理ステーション 2との間で基板 Gの搬 入出を行うための搬送装置 11を備えており、このカセットステーション 1にお!/、て外部 に対するカセット Cの搬入出が行われる。また、搬送装置 11は、カセット Cの配列方 向である Y方向に沿って設けられた搬送路 10上を移動可能な搬送アーム 11aを有し ている。この搬送アーム 11aは、 X方向への進出 '退避および回転可能に設けられて おり、カセット Cと処理ステーション 2との間で基板 Gの受渡しを行なえるように構成さ れている。 [0018] The reflow processing system 100 includes a cassette station (loading / unloading unit) 1 on which a cassette C that accommodates a plurality of substrates G is placed, and a substrate G with a reflow process and a surface modification process performed prior to the reflow process. A processing station (processing unit) 2 including a plurality of processing units for performing a series of processing including the above, and a control unit 3 that controls each component of the reflow processing system 100 are provided. In FIG. 1, the longitudinal direction of the reflow processing system 100 is the X direction, and the direction orthogonal to the X direction on the horizontal plane is the Y direction. The cassette station 1 is disposed adjacent to one end of the processing station 2. This cassette station 1 is provided with a transfer device 11 for loading and unloading the substrate G between the cassette C and the processing station 2, and the cassette station 1 is loaded into and out of the cassette C from the outside. Is done. In addition, the transport device 11 has a transport arm 11a that can move on a transport path 10 provided along the Y direction that is the arrangement direction of the cassettes C. The transfer arm 11a is provided so as to be able to advance and retract and rotate in the X direction, and is configured to transfer the substrate G between the cassette C and the processing station 2.

[0020] 処理ステーション 2は、基板 Gに対してレジストのリフロー処理、その前処理として表 面改質処理等を行うための複数の処理ユニットを備えている。これら各処理ユニット において基板 Gは 1枚ずつ処理される。また、処理ステーション 2は、基本的に X方向 に延在する基板 G搬送用の中央搬送路 20を有しており、この中央搬送路 20を挟ん でその両側に各処理ユニットが、中央搬送路 20に臨むように配置されている。  The processing station 2 includes a plurality of processing units for performing a resist reflow process on the substrate G and a surface modification process as a pre-process. In each of these processing units, one substrate G is processed. The processing station 2 basically has a central transport path 20 for transporting a substrate G extending in the X direction. Each processing unit is placed on both sides of the central transport path 20 with the central transport path 20 interposed therebetween. It is arranged to face 20th.

[0021] また、中央搬送路 20には、各処理ユニットとの間で基板 Gの搬入出を行うための搬 送装置 21が備えられており、処理ユニットの配列方向である X方向に移動可能な搬 送アーム 21aを有している。さらに、この搬送アーム 21aは、 Y方向への進出'退避、 上下方向への昇降および回転可能に設けられており、各処理ユニットとの間で基板 Gの搬入出を行なえるように構成されている。  In addition, the central transport path 20 is provided with a transport device 21 for loading and unloading the substrate G to and from each processing unit, and is movable in the X direction, which is the arrangement direction of the processing units. It has a transport arm 21a. Furthermore, the transfer arm 21a is provided so as to be advanced and retracted in the Y direction, reciprocated in the vertical direction, and rotated, and is configured so that the substrate G can be transferred into and out of each processing unit. Yes.

[0022] 処理ステーション 2の中央搬送路 20に沿って一方側には、カセットステーション 1の 側から、ァドヒージョンュニット( AD) 30およびリフロー処理ュニット(REFLW) 60力 Sこ の順に配列され、中央搬送路 20に沿って他方側には、三つの加熱'冷却処理ュニッ HHP/COU 80a, 80b, 80c力 S—歹 IJに酉己歹 IJされている。各加熱'冷却処理ユニット (HP/COL) 80a, 80b, 80cは、鉛直方向に多段に積層配置されている(図示省略 )。  [0022] Arranged in this order from the cassette station 1 side to the adjunct unit (AD) 30 and the reflow processing unit (REFLW) 60 forces S along the central transfer path 20 of the processing station 2 On the other side along the central conveying path 20, three heating / cooling processing units HHP / COU 80a, 80b, 80c force S— 歹 IJ are applied. Each heating / cooling processing unit (HP / COL) 80a, 80b, 80c is stacked in multiple layers in the vertical direction (not shown).

[0023] アドヒージョンユニット (AD) 30は、リフロー処理に先だって、基板 Gに対し、例えば HMDS (へキサメチルジシラザン)、 TMSDEA(N—トリメチルシリルジェチルァミン) 等のシリル化剤に代表される表面改質処理剤を含む雰囲気を形成して、レジストの 流動を促進するための表面改質処理を行なう。これらの表面改質処理剤は、疎水化 処理作用を持ち、疎水化処理剤としても知られて!/、る。 [0023] Adhesion unit (AD) 30 is a representative of silylating agents such as HMDS (hexamethyldisilazane) and TMSDEA (N-trimethylsilyljetylamine) for substrate G prior to reflow treatment. An atmosphere containing the surface modification treatment agent is formed, and surface modification treatment is performed to promote the flow of the resist. These surface modification treatment agents are hydrophobized It has a treatment effect and is also known as a hydrophobizing agent!

[0024] ここで、アドヒージョンユニット(AD) 30について図 2を参照しながら説明する。  Here, the adhesion unit (AD) 30 will be described with reference to FIG.

アドヒージョンユニット(AD) 30は、図示しない直方体形状のフレームを有しており、 このフレームの内側に固定式のチャンバ本体 31と昇降可能な蓋体 33とを有している 。チャンバ本体 31は、基板 Gよりもサイズが一回り大きぐ上面が開口した扁平な直 方体の下部容器として構成されてレ、る。  The adhesion unit (AD) 30 has a rectangular parallelepiped frame (not shown), and has a fixed chamber main body 31 and a lid 33 that can be raised and lowered inside the frame. The chamber body 31 is configured as a flat, rectangular parallelepiped lower container having an upper surface that is slightly larger in size than the substrate G.

[0025] 蓋体 33は、チャンバ本体 31とほぼ同サイズ (面積)の下面に開口した扁平な直方 体の上部容器として構成され、後述するように表面改質に用いる HMDSを貯留する HMDS供給源 35に接続されている。また、蓋体 33は、水平方向(X方向および Y方 向)に延びる複数本の水平支持部材 37に固定されており、各々の水平支持部材 37 は、図示しない昇降駆動機構例えば、複数のエアシリンダのピストンロッドに連結され ている。従って、これらのエアシリンダのピストンロッドを垂直上方に向けて進出させる と、水平支持部材 37と一体になつて蓋体 33が垂直上方に移動(上昇)してチャンバ が開放され、逆に、各ピストンロッドを垂直下方に後退させると、水平支持部材 37と 一体に蓋体 33が垂直下方に移動(下降)するようになって!/、る。  [0025] The lid 33 is configured as an upper container of a flat rectangular parallelepiped opening on the lower surface of substantially the same size (area) as the chamber body 31, and an HMDS supply source for storing HMDS used for surface modification as described later Connected to 35. The lid 33 is fixed to a plurality of horizontal support members 37 extending in the horizontal direction (X direction and Y direction), and each horizontal support member 37 is provided with an elevating drive mechanism (not shown) such as a plurality of air. It is connected to the piston rod of the cylinder. Therefore, when the piston rods of these air cylinders are advanced vertically upward, the lid 33 moves (rises) integrally with the horizontal support member 37, and the chamber is opened. When the piston rod is retracted vertically downward, the lid 33 moves (lowers) together with the horizontal support member 37 vertically (!).

[0026] チャンバ本体 31内には、基板 Gに略対応した大きさの矩形をした加熱プレート 41 が水平に配置され、固定具 42によって固定されている。この加熱プレート 41は、熱 伝導率の高い金属例えばアルミニウムからなり、その内部または下面には例えば抵 抗発熱体からなるヒータ(図示せず)が設けられて!/、る。  In the chamber body 31, a rectangular heating plate 41 having a size substantially corresponding to the substrate G is horizontally disposed and fixed by a fixture 42. The heating plate 41 is made of a metal having a high thermal conductivity, such as aluminum, and a heater (not shown) made of, for example, a resistance heating element is provided on the inside or the lower surface thereof.

[0027] また、加熱プレート 41には、複数の貫通孔 43が形成され、各貫通孔 43にはそれぞ れリフターピン 44が揷設されており、基板 Gを上下に昇降させる基板昇降機構 45が 設けられている。そして、外部の搬送装置 21の搬送アーム 21a (図 1参照)との間でこ れらのリフターピン 44を加熱プレート 41の表面から突出させて基板 Gを受渡しできる ように構成されている。リフターピン 44は、加熱プレート 41の下に配置された水平支 持板 46により互いに連結され、同期して昇降変位できるように構成されている。なお 、水平支持板 46を昇降移動させるための図示しない昇降駆動部力 チャンバ本体 3 1の内側または外側に配置されて!/、る。  [0027] Further, the heating plate 41 is formed with a plurality of through holes 43, and each through hole 43 is provided with a lifter pin 44, and a substrate lifting mechanism 45 that lifts and lowers the substrate G up and down. Is provided. These lifter pins 44 project from the surface of the heating plate 41 between the transfer arm 21a (see FIG. 1) of the external transfer device 21 so that the substrate G can be delivered. The lifter pins 44 are connected to each other by a horizontal support plate 46 disposed under the heating plate 41, and are configured to be able to move up and down synchronously. It should be noted that a lifting drive unit force (not shown) for moving the horizontal support plate 46 up and down is disposed inside or outside the chamber body 31.

[0028] チャンバ本体 31の側壁上端面には、周回方向に延びるシームレスなシール部材 3 2が取付けられている。蓋体 33をチャンバ本体 31に合体させた状態で、蓋体 33の側 壁下端面とチャンバ本体 31の側壁上端面との間にこのシール部材 32が介在して密 閉できるようになつている。これにより、チャンバ本体 31と蓋体 33とによる気密な処理 室 47が形成されるようになっている。 [0028] A seamless seal member 3 extending in the circumferential direction is formed on the upper end surface of the side wall of the chamber body 31. 2 is installed. The sealing member 32 is interposed between the lower end surface of the side wall of the lid 33 and the upper end surface of the side wall of the chamber body 31 in a state in which the lid 33 is combined with the chamber body 31 so that the lid 33 can be closed tightly. . Thereby, an airtight processing chamber 47 is formed by the chamber body 31 and the lid 33.

[0029] 蓋体 33の一側面には、 HMDSガス導入ポート 48が設けられ、この HMDSガス導 入ポート 48と対向する他方の側面には、排気ポート 49が設けられている。  An HMDS gas introduction port 48 is provided on one side surface of the lid 33, and an exhaust port 49 is provided on the other side surface facing the HMDS gas introduction port 48.

HMDSガス導入ポート 48は、蓋体 33の一側面に任意の間隔で形成された複数の 貫通孔 50と、各貫通孔 50にその外側から装着されたガス供給管 51の終端アダプタ 53と、各貫通孔 50より内側に設けられ、一定間隔で多数のガス吐出口 55が形成さ れたバッファ室 54とを有して!/、る。  The HMDS gas introduction port 48 includes a plurality of through holes 50 formed at an arbitrary interval on one side surface of the lid 33, a terminal adapter 53 of the gas supply pipe 51 attached to each through hole 50 from the outside, and each And a buffer chamber 54 provided inside the through hole 50 and having a large number of gas discharge ports 55 formed at regular intervals.

[0030] また、排気ポート 49は、 HMDSガス導入ポート 48と対向する蓋体 33の側面に一定 間隔で形成された多数の通気孔 56を有するとともに、蓋体 33の側壁の外側に設け られた排気ダクト室 57を有している。この排気ダクト室 57の底に形成された排気口 5 8は、排気管 59を介して排気ポンプ(図示せず)に接続している。  The exhaust port 49 has a large number of air holes 56 formed at regular intervals on the side surface of the lid 33 facing the HMDS gas introduction port 48, and is provided outside the side wall of the lid 33. It has an exhaust duct chamber 57. An exhaust port 58 formed at the bottom of the exhaust duct chamber 57 is connected to an exhaust pump (not shown) through an exhaust pipe 59.

[0031] このような構成のアドヒージョンユニット(AD) 30において表面改質処理を行なうとき は、まず、基板昇降機構 45のリフターピン 44を上昇させた状態で搬送装置 21の搬 送アーム 21aから基板 Gを受取る。そして、リフターピン 44を下降させて基板 Gをカロ 熱プレート 41上に載置した後、蓋体 33を退避位置から垂直に下降させ、チャンバ本 体 31に当接させ、チャンバを密閉する。基板 Gは、加熱プレート 41によって所定温 度例えば 110°C〜; 120°Cに加熱される。そして、図示しない排気ポンプにより処理室 47内を排気しながら、 HMDS供給源 35より HMDSガスをガス供給管 51および HM DSガス導入ポート 48を介して処理室 47に供給する。処理室 47内では、 HMDSガ ス導入ポート 48のガス吐出口 55より噴出された HMDSガス力 S、排気ポート 49に向か う気流を形成し、その途中で基板 Gの表面 (被処理面)に接触し、該表面を表面改質 する。  When performing the surface modification process in the adhesion unit (AD) 30 having such a configuration, first, the transport arm 21a of the transport device 21 is brought up with the lifter pins 44 of the substrate lift mechanism 45 raised. Receives board G from Then, after the lifter pin 44 is lowered and the substrate G is placed on the calo heat plate 41, the lid 33 is vertically lowered from the retracted position and brought into contact with the chamber body 31 to seal the chamber. The substrate G is heated by the heating plate 41 to a predetermined temperature, for example, 110 ° C. to 120 ° C. Then, the HMDS gas is supplied from the HMDS supply source 35 to the processing chamber 47 through the gas supply pipe 51 and the HMDS gas introduction port 48 while exhausting the inside of the processing chamber 47 by an exhaust pump (not shown). In the processing chamber 47, an HMDS gas force S ejected from the gas discharge port 55 of the HMDS gas introduction port 48 and an air flow toward the exhaust port 49 are formed, and the surface of the substrate G (processed surface) in the middle To modify the surface.

[0032] 処理室 47内を通過した HMDSガスは、排気ポート 49において通気孔 56から排気 ダクト室 57へ送られ、そこから排気ポンプの作用によって排気される。所定の処理時 間が経過し、表面改質処理が終了した後は、 HMDSガスの供給および排気ポンプ を停止させてから、図示しない昇降駆動機構の上昇駆動によって蓋体 33をチャンバ 本体 31から上方に引き離し、そのまま所定の退避位置まで持ち上げる。その後、基 板昇降機構 45のリフターピン 44を上昇させ、基板 Gを加熱プレート 41の上方へ持ち 上げ、搬送装置 21の搬送アーム 21aに受け渡す。その後、搬送アーム 21aにより、 表面改質処理後の基板 Gをアドヒージョンユニット (AD) 30から搬出する。 The HMDS gas that has passed through the processing chamber 47 is sent from the vent hole 56 to the exhaust duct chamber 57 at the exhaust port 49 and is exhausted therefrom by the action of the exhaust pump. After the prescribed treatment time has elapsed and the surface modification treatment is completed, supply of HMDS gas and exhaust pump Then, the lid 33 is pulled upward from the chamber main body 31 by the ascending drive of a lifting drive mechanism (not shown) and lifted up to a predetermined retracted position as it is. Thereafter, the lifter pin 44 of the substrate lifting mechanism 45 is raised, the substrate G is lifted above the heating plate 41, and transferred to the transfer arm 21 a of the transfer device 21. Thereafter, the substrate G after the surface modification treatment is unloaded from the adhesion unit (AD) 30 by the transfer arm 21a.

[0033] 表面改質処理後の基板 Gは、次に、搬送アーム 21aによって処理ステーション 2のリ フロー処理ユニット(REFLW) 60に搬入され、基板 G上に形成されたレジストを有機 溶媒例えばシンナー雰囲気で軟化させてマスク形状を変化させるリフロー処理が行 なわれる。 [0033] The substrate G after the surface modification treatment is then carried into the reflow treatment unit (REFLW) 60 of the treatment station 2 by the transfer arm 21a, and the resist formed on the substrate G is removed from the organic solvent such as a thinner atmosphere. A reflow process is performed to soften and change the mask shape.

[0034] ここで、リフロー処理ユニット(REFLW) 60の構成について、さらに詳細に説明する 。図 3は、リフロー処理ユニット(REFLW) 60の概略断面図である。リフロー処理ュニ ッ HREFLW) 60は、チャンバ 61を有しており、このチャンバ 61は、下部チャンバ 61 aと、この下部チャンバ 61aの上部に当接される上部チャンバ 61bと力、ら構成されてい る。上部チャンバ 61bと下部チャンバ 61aとは、図示しない開閉機構により開閉可能 に構成されており、開状態のときに、搬送装置 21により基板 Gの搬入出が行なわれる  Here, the configuration of the reflow processing unit (REFLW) 60 will be described in more detail. FIG. 3 is a schematic sectional view of the reflow processing unit (REFLW) 60. The reflow processing unit (HREFLW) 60 has a chamber 61, and this chamber 61 is composed of a lower chamber 61a and an upper chamber 61b abutting on the upper portion of the lower chamber 61a. The The upper chamber 61b and the lower chamber 61a are configured to be opened and closed by an opening / closing mechanism (not shown), and the substrate G is loaded and unloaded by the transfer device 21 when the chamber is open.

[0035] このチャンバ 61内には、基板 Gを水平に支持する支持テーブル 62が設けられてい る。支持テーブル 62は熱伝導率に優れた材質例えばアルミニウムで構成されて!/、る In the chamber 61, a support table 62 that supports the substrate G horizontally is provided. The support table 62 is made of a material having excellent thermal conductivity such as aluminum!

[0036] 支持テーブル 62には、図示しない昇降機構によって駆動され、基板 Gを昇降させ る 3本の昇降ピン 63 (図 3では 2本のみを図示する) 1S 支持テーブル 62を貫通する ように設けられている。この昇降ピン 63は、昇降ピン 63と搬送装置 21との間で基板 G を受け渡しする際には、基板 Gを支持テーブル 62から持ち上げて所定の高さ位置で 基板 Gを支持し、基板 Gのリフロー処理中は、例えば、その先端が支持テーブル 62 の上面と同じ高さとなるようにして保持される。 [0036] The support table 62 is driven by a lift mechanism (not shown) and lifts and lowers the substrate G. Three lift pins 63 (only two are shown in FIG. 3) 1S Provided so as to penetrate the support table 62 It has been. When transferring the substrate G between the lifting pins 63 and the transfer device 21, the lift pins 63 lift the substrate G from the support table 62 and support the substrate G at a predetermined height position. During the reflow process, for example, the tip of the support table 62 is held at the same height as the upper surface.

[0037] 下部チャンバ 61aの底部には、排気口 64a, 64bが形成されており、この排気口 64 a, 64bには排気系 64が接続されている。そして、この排気系 64を通ってチャンバ 61 内の雰囲気ガスが排気される。 [0038] 支持テーブル 62の内部には、温度調節媒体流路 65が設けられており、この温度 調節媒体流路 65には、例えば温調冷却水などの温度調節媒体が温度調節媒体導 入管 65aを介して導入され、温度調節媒体排出管 65bから排出されて循環し、その 熱(例えば冷熱)が支持テーブル 62を介して基板 Gに対して伝熱され、これにより基 板 Gの処理面が所望の温度に制御される。 [0037] Exhaust ports 64a and 64b are formed at the bottom of the lower chamber 61a, and an exhaust system 64 is connected to the exhaust ports 64a and 64b. Then, the atmospheric gas in the chamber 61 is exhausted through the exhaust system 64. [0038] A temperature control medium flow path 65 is provided inside the support table 62. In the temperature control medium flow path 65, for example, a temperature control medium such as temperature control cooling water is supplied to the temperature control medium introduction pipe 65a. And is discharged from the temperature control medium discharge pipe 65b and circulated, and its heat (for example, cold heat) is transferred to the substrate G through the support table 62, whereby the processing surface of the substrate G is changed. The desired temperature is controlled.

[0039] チャンバ 61の天壁部分には、シャワーヘッド 66力 支持テーブル 62に対向するよ うに設けられている。このシャワーヘッド 66の下面 66aには、多数のガス吐出孔 66b が設けられている。  [0039] The ceiling wall portion of the chamber 61 is provided so as to face the shower head 66 force support table 62. A large number of gas discharge holes 66b are provided on the lower surface 66a of the shower head 66.

[0040] また、シャワーヘッド 66の上部中央には、ガス導入部 67が設けられており、このガ ス導入部 67はシャワーヘッド 66の内部に形成された空間 68に連通している。ガス導 入部 67には配管 69が接続されている。配管 69には、有機溶媒例えばシンナーを気 化して供給するバブラ一タンク 70が接続され、その途中には開閉バルブ 71が設けら れている。バブラ一タンク 70の底部には、シンナーを気化させるための気泡発生手 段として、図示しない Nガス供給源に接続された Nガス供給配管 74が配備されてい  In addition, a gas introduction part 67 is provided at the upper center of the shower head 66, and the gas introduction part 67 communicates with a space 68 formed in the shower head 66. A pipe 69 is connected to the gas inlet 67. The pipe 69 is connected to a bubbler tank 70 that vaporizes and supplies an organic solvent such as thinner, and an open / close valve 71 is provided in the middle thereof. An N gas supply pipe 74 connected to an N gas supply source (not shown) is provided at the bottom of the bubbler tank 70 as a bubble generating means for vaporizing the thinner.

2 2  twenty two

る。この Nガス供給配管 74には、マスフローコントローラ 72および開閉バルブ 73が  The The N gas supply pipe 74 has a mass flow controller 72 and an opening / closing valve 73.

2  2

設けられている。また、バブラ一タンク 70は、内部に貯留されるシンナーの温度を所 定温度に調節するための図示しない温度調節機構を備えている。そして、図示しな い Nガス供給源から Nガスをマスフローコントローラ 72によって流量制御しながらバ Is provided. The bubbler tank 70 is provided with a temperature adjusting mechanism (not shown) for adjusting the temperature of the thinner stored therein to a predetermined temperature. Then, N gas is supplied from an N gas supply source (not shown) while the flow rate is controlled by the mass flow controller 72.

2 2 twenty two

ブラータンク 70の底部に導入することにより、所定温度に温度調節されたバブラータ ンク 70内のシンナーを気化させ、配管 69、ガス導入部 67を介してチャンバ 61内に 導入できるように構成されて!/、る。  By introducing it into the bottom of the blur tank 70, the thinner in the bubbler tank 70, the temperature of which has been adjusted to a predetermined temperature, can be vaporized and introduced into the chamber 61 via the pipe 69 and the gas inlet 67! /

[0041] また、シャワーヘッド 66の上部の周縁部には、複数のパージガス導入部 75が設け られており、各パージガス導入部 75には、例えばパージガスとしての Nガスをチャン [0041] Further, a plurality of purge gas introduction portions 75 are provided at the upper peripheral portion of the shower head 66, and each purge gas introduction portion 75 is filled with, for example, N gas as purge gas.

2  2

ノ 61内に供給するパージガス供給配管 76が接続されている。パージガス供給配管 76は、図示しないパージガス供給源に接続されており、その途中には開閉バルブ 77 が設けられている。  A purge gas supply pipe 76 for supplying the gas to the inside 61 is connected. The purge gas supply pipe 76 is connected to a purge gas supply source (not shown), and an opening / closing valve 77 is provided in the middle thereof.

[0042] このような構成のリフロー処理ユニット(REFLW) 60においては、まず、上部チャン ノ 61bを下部チャンバ 61aから開放し、その状態で、搬送装置 21の搬送アーム 21a により、既にパターン形成され、表面改質処理がなされたレジストを有する基板 Gを搬 入し、支持テーブル 62に載置する。そして、上部チャンバ 61bと下部チャンバ 61aを 当接させ、チャンバ 61を閉じる。 In the reflow processing unit (REFLW) 60 having such a configuration, first, the upper channel 61b is released from the lower chamber 61a, and in this state, the transfer arm 21a of the transfer device 21 is opened. As a result, the substrate G having the resist that has already been patterned and subjected to the surface modification treatment is loaded and placed on the support table 62. Then, the upper chamber 61b and the lower chamber 61a are brought into contact with each other, and the chamber 61 is closed.

[0043] 次に配管 69の開閉バルブ 71および Nガス供給配管 74の開閉バルブ 73を開放し Next, open the open / close valve 71 of the pipe 69 and the open / close valve 73 of the N gas supply pipe 74.

2  2

、マスフローコントローラ 72によって Nガスの流量を調節してシンナーの気化量を制  The flow rate of N gas is controlled by the mass flow controller 72 to control the vaporization amount of thinner.

2  2

御しつつ、バブラ一タンク 70から、気化されたシンナーを配管 69、ガス導入部 67を 介してシャワーヘッド 66の空間 68に導入し、ガス吐出孔 66bから吐出させる。これに より、チャンバ 61内が所定濃度のシンナー雰囲気とされる。  In the meantime, the vaporized thinner is introduced into the space 68 of the shower head 66 from the bubbler tank 70 via the pipe 69 and the gas introduction part 67 and discharged from the gas discharge hole 66b. As a result, the inside of the chamber 61 has a thinner atmosphere with a predetermined concentration.

[0044] チャンバ 61内の支持テーブル 62に載置された基板 G上には、既にパターン形成さ れたレジストが設けられているので、このレジストがシンナー雰囲気に曝されることに より、シンナーがレジストに浸透する。これにより、レジストが軟化してその流動性が高 まり、変形して基板 G表面の所定の領域 (ターゲット領域)が変形レジストで被覆され る。この際、支持テーブル 62の内部に設けられた温度調節媒体流路 65に、温度調 節媒体を導入することによって、その熱が支持テーブル 62を介して基板 Gに対して 伝熱され、これにより基板 Gの処理面が所望の温度例えば 20°Cに制御される。シャヮ 一ヘッド 66から基板 Gの表面に向けて吐出されたシンナーを含むガスは、基板 Gの 表面に接触した後、排気口 64a, 64bへ向けて流れ、チャンバ 61内から排気系 64へ 排気される。 [0044] Since a patterned resist is already provided on the substrate G placed on the support table 62 in the chamber 61, the resist is exposed to a thinner atmosphere. Penetrates the resist. As a result, the resist is softened and its fluidity is increased, and the resist is deformed and a predetermined region (target region) on the surface of the substrate G is covered with the deformed resist. At this time, by introducing the temperature adjustment medium into the temperature adjustment medium flow path 65 provided inside the support table 62, the heat is transferred to the substrate G via the support table 62, thereby The processing surface of the substrate G is controlled to a desired temperature, for example, 20 ° C. The gas containing thinner discharged from the head 66 toward the surface of the substrate G contacts the surface of the substrate G, then flows toward the exhaust ports 64a and 64b, and is exhausted from the chamber 61 to the exhaust system 64. The

[0045] 以上のようにして、リフロー処理ユニット(REFLW) 60におけるリフロー処理が終了 した後は、排気を継続しながらパージガス供給配管 76上の開閉バルブ 77を開放し、 パージガス導入部 75を介してチャンバ 61内にパージガスとしての Nガスを導入し、  [0045] After the reflow processing in the reflow processing unit (REFLW) 60 is completed as described above, the open / close valve 77 on the purge gas supply pipe 76 is opened while continuing the exhaust, and the purge gas introduction unit 75 is connected. N gas as a purge gas is introduced into the chamber 61,

2  2

チャンバ内雰囲気を置換する。その後、上部チャンバ 61bを下部チャンバ 61aから開 放し、前記と逆の手順でリフロー処理後の基板 Gを搬送アーム 21aによってリフロー 処理ユニット (REFLW) 60から搬出する。  Replace the atmosphere in the chamber. Thereafter, the upper chamber 61b is opened from the lower chamber 61a, and the substrate G after the reflow process is carried out from the reflow process unit (REFLW) 60 by the transfer arm 21a in the reverse procedure.

[0046] 三つの加熱.冷却処理ユニット(HP/COU 80a, 80b, 80cには、それぞれ基板 Gに対して加熱処理を行うホットプレートユニット(HP)、基板 Gに対して冷却処理を 行うクーリングプレートユニット(COL)力 多段例えば 2段ずつ合計 4段に重ねられて 構成されている(図示省略)。この加熱'冷却処理ユニット(HP/COU 80a, 80b, 8 Ocでは、表面改質処理後およびリフロー処理後の基板 Gに対して、必要に応じて加 熱処理や冷却処理が行なわれる。 [0046] Three heating and cooling processing units (HP / COU 80a, 80b, and 80c have a hot plate unit (HP) that heats the substrate G and a cooling plate that cools the substrate G, respectively. Unit (COL) force Multi-stage, for example, 2 stages are stacked in a total of 4 stages (not shown) .This heating / cooling processing unit (HP / COU 80a, 80b, 8 In Oc, the substrate G after the surface modification treatment and the reflow treatment is subjected to heat treatment or cooling treatment as necessary.

[0047] 図 1に示すように、リフロー処理システム 100の各構成部は、制御部 3の CPUを備 えたコントローラ 90に接続されて制御される構成となっている。コントローラ 90には、 オペレータがリフロー処理システム 100を管理するためにコマンドの入力操作等を行 うキーボードや、リフロー処理システム 100の稼働状況を可視化して表示するデイス プレイ等からなるユーザーインターフェース 91が接続されている。  As shown in FIG. 1, each component of the reflow processing system 100 is configured to be connected to and controlled by a controller 90 having a CPU of the controller 3. Connected to the controller 90 is a user interface 91 consisting of a keyboard on which an operator inputs commands to manage the reflow processing system 100, a display that visualizes and displays the operating status of the reflow processing system 100, and the like. Has been.

[0048] また、コントローラ 90には、リフロー処理システム 100で実行される各種処理をコント ローラ 90の制御にて実現するためのプログラムや処理条件データ等が記録されたレ シピが格納された記憶部 92が接続されている。  [0048] In addition, the controller 90 stores a storage unit storing a recipe in which programs for executing various processes executed by the reflow processing system 100 under the control of the controller 90 and processing condition data are recorded. 92 is connected.

[0049] そして、必要に応じて、ユーザーインターフェース 91からの指示等にて任意のレシ ピを記憶部 92から呼び出してコントローラ 90に実行させることで、コントローラ 90の制 御下で、リフロー処理システム 100での所望の処理が行われる。また、前記レシピは 、例えば、 CD-ROM,ハードディスク、フレキシブルディスク、フラッシュメモリなどの コンピュータ読み取り可能な記憶媒体に格納された状態のものを利用したり、あるい は、他の装置から、例えば専用回線を介して随時伝送させて利用したりすることも可 能である。  [0049] Then, if necessary, the reflow processing system 100 is controlled under the control of the controller 90 by calling an arbitrary recipe from the storage unit 92 according to an instruction from the user interface 91 and causing the controller 90 to execute it. The desired processing at is performed. In addition, the recipe may be stored in a computer-readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a flash memory, or may be dedicated from another device, for example. It is also possible to use it by transmitting it through the line at any time.

[0050] 以上のように構成されるリフロー処理システム 100においては、まず、カセットステー シヨン 1において、搬送装置 11の搬送アーム 11aが、既にレジストパターンが形成さ れた基板 Gを収容しているカセット Cにアクセスして 1枚の基板 Gを取り出す。基板 G は、搬送装置 11の搬送アーム 11aから、処理ステーション 2の中央搬送路 20におけ る搬送装置 21の搬送アーム 21aに受渡され、この搬送装置 21により、アドヒージョン ユニット(AD) 30へ搬入される。そして、アドヒージョンユニット(AD) 30にてリフロー 処理に先立ち表面改質処理が行なわれた後、基板 Gはアドヒージョンユニット (AD) 30から搬送装置 21によって取出され、加熱'冷却処理ユニット(HP/COL) 80a, 8 Ob, 80cのいずれかに搬入される。そして、各加熱.冷却処理ユニット(HP/COL) 80a, 80b, 80cにおいて冷却処理が施された基板 Gは、リフロー処理ユニット(REF LW) 60へ搬入され、そこでリフロー処理が行なわれる。 [0051] リフロー処理後は、必要に応じて各加熱.冷却処理ユニット(HP/COU 80a, 80b , 80cにおいて所定の加熱、冷却処理が施される。このような一連の処理が終了した 基板 Gは、搬送装置 21によりリフロー処理ユニット (REFLW) 60から取出され、カセ ットステーション 1の搬送装置 11に受渡され、任意のカセット Cに収容される。 In the reflow processing system 100 configured as described above, first, in the cassette station 1, the cassette in which the transfer arm 11 a of the transfer apparatus 11 contains the substrate G on which a resist pattern has already been formed. Access C and take out one board G. The substrate G is transferred from the transfer arm 11a of the transfer device 11 to the transfer arm 21a of the transfer device 21 in the central transfer path 20 of the processing station 2, and is transferred into the adhesion unit (AD) 30 by the transfer device 21. The Then, after the surface modification process is performed prior to the reflow process in the adhesion unit (AD) 30, the substrate G is taken out of the adhesion unit (AD) 30 by the transfer device 21, and is heated and cooled. (HP / COL) 80a, 8 Ob, or 80c. Then, the substrate G subjected to the cooling process in each heating / cooling processing unit (HP / COL) 80a, 80b, 80c is carried into the reflow processing unit (REF LW) 60, where the reflow process is performed. [0051] After the reflow process, the heating and cooling processing units (HP / COUs 80a, 80b, and 80c are subjected to predetermined heating and cooling processes as necessary. Substrate G after such a series of processes has been completed. Is taken out from the reflow processing unit (REFLW) 60 by the transfer device 21, delivered to the transfer device 11 of the cassette station 1, and stored in an arbitrary cassette C.

[0052] 次に、リフロー処理ユニット(REFLW) 60において行なわれる本発明リフロー方法 の原理について、表面改質処理を行なわない比較リフロー方法と対比しながら説明 する。ここでは、 TFT製造過程の中でリフロー処理を行なう場合について説明する。  Next, the principle of the reflow method of the present invention performed in the reflow processing unit (REFLW) 60 will be described in comparison with a comparative reflow method that does not perform surface modification processing. Here, a case where reflow processing is performed in the TFT manufacturing process will be described.

[0053] 図 4A〜4Cは、比較リフロー方法を説明するための工程断面図である。図 4Aに示 すように、ガラス等の透明基板からなる絶縁基板 201上には、ゲート電極 202および 図示しないゲート線が形成され、さらにシリコン窒化膜などのゲート絶縁膜 203、 a— Si (アモルファスシリコン)膜 204、ォーミックコンタクト層としての η+Si膜 205、ソース 電極 206aおよびドレイン電極 206b並びにソース電極用レジストマスク 210およびド レイン電極用レジストマスク 211がこの順に積層されている。ソース電極 206aおよび ドレイン電極 206bは、ソース電極用レジストマスク 210およびドレイン電極用レジスト マスク 211をマスクとしてエッチングされており、下地膜である n+Si膜 205の表面が 露出している。 4A to 4C are process cross-sectional views for explaining a comparative reflow method. As shown in FIG. 4A, a gate electrode 202 and a gate line (not shown) are formed on an insulating substrate 201 made of a transparent substrate such as glass. Further, a gate insulating film 203 such as a silicon nitride film, a-Si (amorphous (Silicon) film 204, η + Si film 205 as an ohmic contact layer, source electrode 206a and drain electrode 206b, source electrode resist mask 210 and drain electrode resist mask 211 are laminated in this order. The source electrode 206a and the drain electrode 206b are etched using the source electrode resist mask 210 and the drain electrode resist mask 211 as a mask, and the surface of the n + Si film 205 as the base film is exposed.

[0054] 次に、このような積層構造を有する被処理体に対して、リフロー処理システム 100の リフロー処理ユニット(REFLW) 60にてシンナー等の溶剤雰囲気でリフロー処理が 行なわれる。このリフロー処理によって、ソース電極用レジストマスク 210およびドレイ ン電極用レジストマスク 211を構成するレジストが軟化して流動性を持つようになる。 このリフロー処理によって、図 4Bに示すように、ソース電極 206aとドレイン電極 206b の間の凹部 220 (チャンネル形成領域)の n+Si膜 205の表面が流動化した変形レジ スト 212で覆われる。この処理は、次工程で n+Si膜 205および a— Si膜 204をエッチ ングする際に、チャンネル形成領域の n+Si膜 205および a— Si膜 204がエッチングさ れてしまうことを防ぐ目的で行われる。このように、ソース電極用レジストマスク 210お よびドレイン電極用レジストマスク 211を構成するレジストをリフローさせてレジストマス クを再利用することにより、フォトリソグラフィー工程を省略できるという利点がある。 Next, the object to be processed having such a laminated structure is subjected to a reflow process in a solvent atmosphere such as thinner in the reflow process unit (REFLW) 60 of the reflow process system 100. By this reflow treatment, the resist constituting the source electrode resist mask 210 and the drain electrode resist mask 211 is softened and has fluidity. By this reflow process, as shown in FIG. 4B, the surface of the n + Si film 205 in the recess 220 (channel formation region) between the source electrode 206a and the drain electrode 206b is covered with the fluidized deformation resist 212. This process is the purpose of preventing the n + Si layer 205 and the a- Si film 204 in the next step when etched ring, n + Si layer 205 and the a- Si film 204 of the channel formation region is etched Done in Thus, there is an advantage that the photolithography process can be omitted by reflowing the resist constituting the resist mask for source electrode 210 and the resist mask for drain electrode 211 and reusing the resist mask.

[0055] しかし、上記図 4Bに示すように、流動化して変形した変形レジスト 212がソース電 極 206aおよびドレイン電極 206bの面積を超えて下地の n+Si膜 205の表面に拡が つてしまう場合がある。すなわち、次工程で n+Si膜 205および a— Si膜 204をエッチ ングする際にマスクとなる変形レジスト 212が下層のソース電極 206aとドレイン電極 2 06bの面積を超えて周囲にはみ出し、その被覆面積が広がってしまう。その状態で n + Si膜 205および a— Si膜 204をエッチングすると、エッチング精度が低下してしまうと いう問題が生じる。すなわち、図 4Cに示すように、エッチング後の n+Si膜 205および a— Si膜 204の側面と、ソース電極 206aまたはドレイン電極 206bの側面とが面一に ならず、段差が生じてしまう。このように、ソース電極 206aまたはドレイン電極 206bに 対して、下地の n+Si膜 205および a— Si膜 204が横方向に突出した形状で以後のェ 程を行ない、 TFTを製造した場合、画素内で光が通過する割合を表す開口率が低 下するほか、この突出した部分で a— Si膜 204に当る光によって光電流が発生し、電 気ノイズが増加し、リーク電流が発生するなどの悪影響をもたらすことが懸念される。 [0055] However, as shown in FIG. In some cases, the surface of the base n + Si film 205 may extend beyond the area of the electrode 206a and the drain electrode 206b. That is, the deformed resist 212 that serves as a mask when etching the n + Si film 205 and the a-Si film 204 in the next process protrudes beyond the area of the lower source electrode 206a and drain electrode 206b, and covers it. The area will spread. If the n + Si film 205 and the a-Si film 204 are etched in this state, there arises a problem that the etching accuracy is lowered. That is, as shown in FIG. 4C, the side surfaces of the n + Si film 205 and the a-Si film 204 after etching and the side surfaces of the source electrode 206a or the drain electrode 206b are not flush with each other, resulting in a step. In this way, when the TFT is manufactured by performing the following steps with the n + Si film 205 and the a-Si film 204 as a base protruding in the lateral direction with respect to the source electrode 206a or the drain electrode 206b, In addition, the aperture ratio, which represents the rate of light passing through, decreases, and photocurrent is generated by light striking the a-Si film 204 at this protruding part, increasing electrical noise and generating leakage current. There is concern that it will cause adverse effects.

[0056] 一方、図 5A〜5Dは、本発明リフロー方法を説明するための工程断面図である。図  On the other hand, FIGS. 5A to 5D are process cross-sectional views for explaining the reflow method of the present invention. Figure

5Aに示す積層構造は、比較リフロー方法に関する図 4Aと同様であるので説明を省 略する。このような積層構造を有する被処理体に対して、図 5Bに示すように、リフロー 処理システム 100のアドヒージョンユニット(AD) 30にて表面改質処理を行なう。表面 改質処理により、ソース電極 206aおよびドレイン電極 206b (ソース電極用レジストマ スク 210およびドレイン電極用レジストマスク 211)によって被覆されていない n+Si膜 205の露出表面が表面改質される。この場合、 n+Si膜 205の表面改質処理面 205a における純水の接触角が、 50度以上例えば 50〜; 120度になるまで表面改質処理を 行なうことが好ましい。表面改質処理面 205aにおける接触角が 50度以上になるよう に表面改質することにより、引き続くリフロー工程でレジストの流動による拡がりを効果 的に抑制することができる。  The laminated structure shown in FIG. 5A is the same as that in FIG. As shown in FIG. 5B, the surface modification process is performed on the workpiece having such a laminated structure by the adhesion unit (AD) 30 of the reflow processing system 100. By the surface modification treatment, the exposed surface of the n + Si film 205 not covered with the source electrode 206a and the drain electrode 206b (the source electrode resist mask 210 and the drain electrode resist mask 211) is surface-modified. In this case, it is preferable to perform the surface modification treatment until the contact angle of pure water on the surface modification treatment surface 205a of the n + Si film 205 is 50 degrees or more, for example, 50 to 120 degrees. By modifying the surface so that the contact angle on the surface-modified surface 205a is 50 degrees or more, it is possible to effectively suppress the spread due to the resist flow in the subsequent reflow process.

[0057] 次に、リフロー処理ユニット(REFLW) 60にてシンナー等の溶剤雰囲気でリフロー 処理が行なわれる。このリフロー処理によって、ソース電極用レジストマスク 210およ びドレイン電極用レジストマスク 211を構成するレジストが軟化して流動性を持つよう になる。このリフロー処理によって、図 5Cに示すように、ソース電極 206aとドレイン電 極 206bの間の凹部 220 (チャンネル形成領域)の n+Si膜 205の表面が流動化した 変形レジスト 212で覆われる。このとき、流動化したレジストは変形し、ソース電極 206 aおよびドレイン電極 206bの面積を超えて下地の η+Si膜 205の表面に拡がろうとす る力 η+Si膜 205の表面は既に表面改質され、表面改質処理面 205aが形成されて いるため、軟化したレジストの流動が抑えられ、 n+Si膜 205表面に拡カ Sり難い。 Next, reflow treatment is performed in a reflow treatment unit (REFLW) 60 in a solvent atmosphere such as thinner. By this reflow treatment, the resist constituting the source electrode resist mask 210 and the drain electrode resist mask 211 is softened and has fluidity. By this reflow process, as shown in FIG. 5C, the surface of the n + Si film 205 in the recess 220 (channel formation region) between the source electrode 206a and the drain electrode 206b is fluidized. Covered with deformation resist 212. At this time, the fluidized resist is deformed, and the force that tries to spread over the surface of the underlying η + Si film 205 beyond the area of the source electrode 206 a and the drain electrode 206 b is already on the surface of the η + Si film 205. Since the modified surface 205a is formed by the modification, the flow of the softened resist is suppressed and the surface of the n + Si film 205 is difficult to spread.

[0058] したがって、図 5Cに示すように、リフロー後の変形レジスト 212が下層のソース電極 Therefore, as shown in FIG. 5C, the deformed resist 212 after reflow is formed as a source electrode in the lower layer.

206aとドレイン電極 206bの面積を超えて周囲にはみ出す現象力 比較リフロー方 法(図 4B参照)に比べて大幅に抑制される。つまり、リフロー後の変形レジストによる 被覆面積は、ソース電極 206aとドレイン電極 206bの面積より僅かに大きくなる程度 に改善される。  Phenomenon force that protrudes beyond the area of 206a and drain electrode 206b is greatly suppressed compared to the comparative reflow method (see Fig. 4B). That is, the area covered with the deformed resist after reflowing is improved to be slightly larger than the areas of the source electrode 206a and the drain electrode 206b.

[0059] このため、次工程で変形レジスト 212をマスクとして η+Si膜 205および a— Si膜 204 をエッチングし、さらに変形レジスト 212を除去した後で、図 5Dに示すように、 η+Si膜 205および a— Si膜 204の側面と、ソース電極 206aまたはドレイン電極 206bの側面 とを略面一に形成することが可能になる。したがって、 a— Si膜 204がソース'ドレイン 配線より横方向に広がって形成されることによる開口率の低下や光電流発生による 電気ノイズの増加、リーク電流の発生など、比較リフロー方法における問題点を解決 すること力 Sでさる。  [0059] For this reason, in the next step, the η + Si film 205 and the a-Si film 204 are etched using the deformed resist 212 as a mask, and after the deformed resist 212 is further removed, as shown in FIG. The side surfaces of the film 205 and the a-Si film 204 and the side surfaces of the source electrode 206a or the drain electrode 206b can be formed substantially flush with each other. Therefore, the problems in the comparative reflow method, such as a decrease in aperture ratio due to the formation of the a-Si film 204 extending laterally from the source / drain wiring, an increase in electrical noise due to the generation of photocurrent, and the occurrence of leakage current, are addressed. Solve with power S.

[0060] 表面改質処理により、エッチング精度が向上することは実験結果からも確認されて いる。図 6は、表面改質処理の有無が CD (Critical Dimension;臨界寸法)に与える影 響を調べた試験結果を示すグラフである。グラフの縦軸は、レジストパターンの CDと エッチング後のパターンの CDとの変化量(Δ CD)を示し、横軸は、リフロー処理の時 間を示している。なお、表面改質処理は、 HMDSを用い、処理温度 110°Cで 120秒 間実施した。  [0060] It has also been confirmed from experimental results that the etching accuracy is improved by the surface modification treatment. Fig. 6 is a graph showing the test results of examining the effect of surface modification treatment on CD (Critical Dimension). The vertical axis of the graph represents the amount of change (ΔCD) between the resist pattern CD and the etched pattern CD, and the horizontal axis represents the time of the reflow process. The surface modification treatment was performed using HMDS at a treatment temperature of 110 ° C for 120 seconds.

図 6より、 HMDSによる表面改質処理をした場合、表面改質処理を行なわない場 合に比較して CDの変化量が小さぐレジストパターンがエッチング形状に精度良く転 写されていることがわかる。これは、表面改質処理により、リフロー時のレジストの拡が りが抑制された結果であると考えられる。  From Fig. 6, it can be seen that when the surface modification treatment using HMDS is performed, the resist pattern with a small CD change amount is accurately transferred to the etched shape compared to the case where the surface modification treatment is not performed. . This is thought to be the result of the resist modification suppressing the spread of the resist during reflow.

[0061] なお、本発明方法では、リフロー後、変形レジスト 212に対して軽度のアツシング処 理を行なうことにより、変形レジスト 212による被覆面積をさらに減少させ、ソース電極 206aおよびドレイン電極 206bの面積に一層近づけることが可能になる。この場合、 アツシング処理は、例えば平行平板方式のプラズマ処理装置を使用し、 Oなどの酸 In the method of the present invention, after reflowing, a light ashing process is performed on the deformed resist 212 to further reduce the area covered by the deformed resist 212, and the source electrode It becomes possible to make it closer to the area of 206a and the drain electrode 206b. In this case, the ashing process uses, for example, a parallel plate type plasma processing apparatus, and an acid such as O.

2 素を含有するガスのプラズマにより、チャンバ内圧力 13Pa程度、処理時間 100秒程 度の条件で行なうことができるこの軽度のアツシング処理は変形レジスト 212がソース 電極 206aおよびドレイン電極 206bからはみ出した部分を除去できればよいため、 通常ハーフ露光技術でレジストの薄膜部を除去する目的で行なわれていたアツシン グに比べ短時間例えば 3分の 2程度の時間でよぐエッチング精度への影響もほとん ど問題とはならない。  2 This light ashing process, which can be carried out under the conditions of a chamber gas pressure of about 13 Pa and a processing time of about 100 seconds, is performed by the plasma of the gas containing elemental gas. This part of the deformed resist 212 protrudes from the source electrode 206a and the drain electrode 206b. Therefore, the effect on the etching accuracy is almost a problem in a short time, for example, about two-thirds of the time required for etching, which is usually performed for the purpose of removing the resist thin film with half exposure technology. It will not be.

[0062] また、リフロー処理後に、変形レジスト 212をマスクとして、 η+Si膜 205および a - Si 膜 204をエッチングする際には、 η+Si膜 205および a— Si膜 204のエッチングが等方 的に進行するような条件でエッチングを行なうことにより、エッチング後に n+Si膜 205 および a— Si膜 204がソース電極 206aおよびドレイン電極 206bよりも横方向へはみ 出す現象をさらに抑えることができる。例えば、ドライエッチングの場合、平行平板方 式等のプラズマ処理装置を使用し、エッチングガス種として、例えば SF、 C1ガス等 [0062] After the reflow process, when the η + Si film 205 and the a-Si film 204 are etched using the deformed resist 212 as a mask, the η + Si film 205 and the a-Si film 204 are isotropically etched. By performing the etching under such conditions as to proceed, it is possible to further suppress the phenomenon that the n + Si film 205 and the a-Si film 204 protrude laterally from the source electrode 206a and the drain electrode 206b after the etching. . For example, in the case of dry etching, a plasma processing apparatus such as a parallel plate method is used, and as an etching gas type, for example, SF, C1 gas, etc.

6 2 の混合ガスを用い、チャンバ内圧力 6. 7Pa、処理時間 120秒の条件で実施すること ができる。  This can be carried out using a gas mixture of 62 and under the conditions of a chamber internal pressure of 6.7 Pa and a processing time of 120 seconds.

[0063] 次に、リフロー処理におけるチャンネル領域へのレジスト流動の原理を説明する。  Next, the principle of resist flow to the channel region in the reflow process will be described.

図 7Aは表面改質処理を行わなかった場合のリフロー処理時におけるレジストの流 動状態をモデル化して示す図であり、図 7Bは表面改質処理を行った場合のリフロー 処理時におけるレジストの流動状態をモデル化して示す図である。これらの図におい て、リフローの際の粘性流動の速度と表面張力による流動の速度を矢印の大きさで 示している。  Fig. 7A is a diagram showing a modeled state of resist flow during reflow processing without surface modification treatment, and Fig. 7B shows resist flow during reflow processing with surface modification processing. It is a figure which models and shows a state. In these figures, the velocity of viscous flow during reflow and the velocity of flow due to surface tension are indicated by the size of the arrows.

[0064] リフローの速度は、軟化したレジスト 210a, 21 laの粘性流動と、凹部 220内で融合 したレジスト 210a, 211aの表面張力によって決定される。図 7Aに示すように表面改 質処理を行っていない場合には、ソース電極 206aとドレイン電極 206bとの間の凹部 へは、粘性流動と表面張力による流動により速やかに軟化したレジスト 210a, 211a が流入するカ、ソース電極 206aとドレイン電極 206bの外側領域へも粘性流動により 軟化したレジスト 210a, 21 laが広がる。 [0065] これに対して、 n+Si膜 205の露出部分に表面改質処理を行った場合には、軟化し たレジスト 210a, 21 laの粘性流動の速度が抑制され、軟化したレジスト 210a, 211 aの広がりが抑制される。 [0064] The reflow speed is determined by the viscous flow of the softened resists 210a and 21 la and the surface tension of the resists 210a and 211a fused in the recess 220. As shown in FIG. 7A, when the surface modification treatment is not performed, the resists 210a and 211a softened quickly by the viscous flow and the flow due to the surface tension are formed in the recesses between the source electrode 206a and the drain electrode 206b. The resists 210a and 21la softened by the viscous flow spread to the outer regions of the flowing-in source electrode 206a and the drain electrode 206b. [0065] On the other hand, when the surface modification treatment is performed on the exposed portion of the n + Si film 205, the velocity of the viscous flow of the softened resist 210a, 21 la is suppressed, and the softened resist 210a, The spread of 211 a is suppressed.

[0066] この場合に、表面改質処理は、ソース電極 206aおよびドレイン電極 206bにより覆 われていない η+Si膜 205の表面全体に対して行なわれるので、ソース電極 206aとド レイン電極 206bの外側領域のみならず、ソース電極 206aとドレイン電極 206bとの 間に露出する凹部 220内の n+Si膜 205の表面も表面改質されて表面改質処理面 2 05aが形成されてしまうことになり、その部分の粘性流動の速度も抑制される。 [0066] In this case, the surface modification treatment is performed on the entire surface of the η + Si film 205 that is not covered by the source electrode 206a and the drain electrode 206b, so that the outside of the source electrode 206a and the drain electrode 206b. In addition to the region, the surface of the n + Si film 205 in the recess 220 exposed between the source electrode 206a and the drain electrode 206b is also surface-modified to form a surface-modified surface 205a. The speed of the viscous flow in that portion is also suppressed.

[0067] し力、し、凹部 220内へのレジスト 210a, 21 l aの流入速度は、上述したように、リフロ 一処理により軟化したレジスト 210a, 21 laの粘性流動だけでなぐ凹部 220内へ互 いに反対の方向から流入したレジスト 210a, 21 laが接触した際の表面張力による流 動促進作用にも影響される。  [0067] As described above, the inflow speed of the resists 210a and 21 la into the recesses 220 is mutually changed into the recesses 220 formed only by the viscous flow of the resists 210a and 21 la softened by the reflow process. However, it is also affected by the flow promotion effect due to surface tension when resists 210a and 21 la that flowed in from the opposite direction come into contact.

[0068] したがって、表面改質処理を行なった場合でも、凹部 220内へ向力、うレジスト 210a , 211aが接触した以降は、表面張力によってスムーズにレジスト 210a, 211aの流入 が進む。そして、図 7Bに示すように、凹部 220の外側(ソース電極 206aおよびドレイ ン電極 206bの外側)の表面改質処理面 205aへ向力、う流動は抑制される一方、凹部 220内へのレジスト 210a, 211aの流入は、表面張力によって速やかに進行する。こ のような機構により、表面改質処理を施した後でも、凹部内外でのレジスト 210a, 21 laの流動速度に格差を持たせることができる。  Accordingly, even when the surface modification treatment is performed, the resist 210a, 211a smoothly flows in due to the surface tension after the resist 210a, 211a comes into contact with the directional force into the recess 220. Then, as shown in FIG. 7B, the directional force and flow to the surface modification surface 205a outside the recess 220 (outside the source electrode 206a and the drain electrode 206b) are suppressed, while the resist in the recess 220 is suppressed. The inflow of 210a and 211a proceeds rapidly due to surface tension. With such a mechanism, even after the surface modification treatment, the flow rates of the resists 210a and 21la inside and outside the recess can be made to have a difference.

[0069] このように、表面改質処理によってレジストの流動を抑制することで、チャンネル領 域を確実に被覆しながら、余分なレジストの拡がりを防止することができる。したがつ て、十分なエッチング精度を確保できるとともに、 LCD製品における光電流の発生な ども防止すること力できる。  [0069] As described above, by suppressing the resist flow by the surface modification treatment, it is possible to prevent the resist from spreading further while reliably covering the channel region. Therefore, it is possible to secure sufficient etching accuracy and to prevent generation of photocurrent in LCD products.

[0070] 次に、図 8および図 9A〜9Lを参照しながら、本発明のリフロー方法を液晶表示装 置用 TFT素子の製造工程に適用した実施形態について説明する。  Next, an embodiment in which the reflow method of the present invention is applied to a manufacturing process of a TFT element for a liquid crystal display device will be described with reference to FIG. 8 and FIGS. 9A to 9L.

図 8は、本発明のリフロー方法を適用した液晶表示装置用 TFT素子の製造方法の 一例を示すフローチャートであり、図 9A〜9Lはその製造方法を説明するためのェ 程断面図である。 まず、図 9Aに示すように、ガラス等の透明基板からなる絶縁基板 201上にゲート電 極 202および図示しないゲート線を形成し、さらにシリコン窒化膜などのゲート絶縁膜 203、 a— Si (アモルファスシリコン)膜 204、ォーミックコンタクト層としての η+Si膜 20 5、 A1合金や Mo合金等の電極用金属膜 206をこの順に積層して堆積する(ステップFIG. 8 is a flowchart showing an example of a manufacturing method of a TFT element for a liquid crystal display device to which the reflow method of the present invention is applied, and FIGS. 9A to 9L are cross-sectional views for explaining the manufacturing method. First, as shown in FIG. 9A, a gate electrode 202 and a gate line (not shown) are formed on an insulating substrate 201 made of a transparent substrate such as glass, and a gate insulating film 203 such as a silicon nitride film, a-Si (amorphous (Silicon) film 204, η + Si film 205 as ohmic contact layer, and metal film 206 for electrodes such as A1 alloy and Mo alloy are stacked in this order (step)

51)。 51).

[0071] 次に、図 9Bに示すように、電極用金属膜 206上にレジスト 207を形成する(ステップ  Next, as shown in FIG. 9B, a resist 207 is formed on the electrode metal film 206 (step

52)。そして、図 9Cに示すように露光マスク 300を用い、レジスト 207に対して露光処 理を行なう(ステップ S3)。この露光マスク 300は、レジスト 207を所定のパターンで露 光できるように構成されている。このようにレジスト 207を露光処理することにより、図 9 Dに示すように、露光レジスト部 208と、未露光レジスト部 209とが形成される。  52). Then, as shown in FIG. 9C, using the exposure mask 300, the resist 207 is exposed (step S3). The exposure mask 300 is configured so that the resist 207 can be exposed in a predetermined pattern. By exposing the resist 207 in this manner, an exposed resist portion 208 and an unexposed resist portion 209 are formed as shown in FIG. 9D.

[0072] 露光後は、現像処理を行なうことにより、図 9Eに図示するように、露光レジスト部 20 8が除去され、未露光レジスト部 209を電極用金属膜 206上に残存させることが可能 である(ステップ S4)。未露光レジスト部 209は、ソース電極用レジストマスク 210およ びドレイン電極用レジストマスク 211に分離されパターン形成されて!/、る。  [0072] After the exposure, by performing development processing, the exposed resist portion 208 is removed and the unexposed resist portion 209 can remain on the electrode metal film 206 as shown in FIG. 9E. Yes (step S4). The unexposed resist portion 209 is separated into a source electrode resist mask 210 and a drain electrode resist mask 211 and is patterned.

[0073] そして、ソース電極用レジストマスク 210およびドレイン電極用レジストマスク 211を エッチングマスクとして用い、電極用金属膜 206をエッチングし、図 9Fに示すように、 後にチャンネル領域となる部分に凹部 220を形成する(ステップ S5)。このエッチング によって、ソース電極 206aとドレイン電極 206bが形成され、これらの間の凹部 220 内に n+Si膜 205の表面を露出させることができる。 [0073] Then, using the source electrode resist mask 210 and the drain electrode resist mask 211 as an etching mask, the electrode metal film 206 is etched, and as shown in FIG. 9F, a recess 220 is formed in a portion that later becomes a channel region. Form (step S5). By this etching, the source electrode 206a and the drain electrode 206b are formed, and the surface of the n + Si film 205 can be exposed in the recess 220 between them.

[0074] 次に、図 2のアドヒージョンユニット(AD) 30において、露出した η+Si膜 205の表面 に表面改質処理を実施する(ステップ S6)。シリル化剤などを用いる表面改質処理に よって、 η+Si膜 205の表面は表面改質されて、図 9Gに示すように、純水による接触 角が 50度以上の表面改質処理面 205aが形成される。つまり、 η+Si膜 205の表面改 質処理面 205aには、レジストが流動し難い状態が形成される。  Next, in the adhesion unit (AD) 30 of FIG. 2, a surface modification process is performed on the exposed surface of the η + Si film 205 (step S6). The surface of the η + Si film 205 is modified by the surface modification treatment using a silylating agent, etc., and as shown in FIG. 9G, the surface modification treated surface 205a having a contact angle with pure water of 50 degrees or more. Is formed. That is, a state in which the resist hardly flows is formed on the surface modification surface 205a of the η + Si film 205.

[0075] 次に、図 3のリフロー処理ユニット(REFLW) 60によりリフロー処理を行う(ステップ S 7)。このリフロー処理においては、後にチャンネル領域となる目的の凹部 220にシン ナ一等の有機溶媒によって軟化させたレジストを流入させる。このリフロー処理に際し て、 η+Si膜 205の表面改質処理面 205aでは軟化したレジストの流動が抑制されるも のの、後にチャンネル領域となる凹部 220内では表面張力の作用によって軟化レジ ストの流入が早まり、凹部 220内を確実に被覆することができる。 Next, reflow processing is performed by the reflow processing unit (REFLW) 60 of FIG. 3 (step S 7). In this reflow process, a resist softened with an organic solvent such as a thinner is poured into a target recess 220 to be a channel region later. During this reflow process, the flow of the softened resist is suppressed on the surface modification surface 205a of the η + Si film 205. However, the inflow of the softening resist is accelerated by the action of the surface tension in the recess 220 which will later become the channel region, and the recess 220 can be reliably covered.

[0076] 図 9Hは、変形レジスト 212によって凹部 220内が被覆された状態を示している。ス テツプ S6の表面改質処理を行なわない場合、変形レジスト 212が例えばソース電極 206aやドレイン電極 206bの周囲(凹部 220とは反対側)にまで広がり、例えばォーミ ックコンタクト層としての n +Si膜 205の上を被覆してしまうため、被覆部分が次のシリ コンエッチング工程でエッチングされなくなり、エッチング精度が低下して TFT素子の 不良や歩留りの低下を招来するという問題が生じていた。また、変形レジスト 212によ る被覆面積を予め大きく見積もって設計しておくと、一つの TFT素子を製造するため に必要な面積(ドット面積)が大きくなり、 TFT素子の高集積化や微細化への対応が 困難になるとレ、う問題も生じて!/ヽた。 FIG. 9H shows a state where the recess 220 is covered with the deformation resist 212. When the surface modification treatment of step S6 is not performed, the deformed resist 212 extends to, for example, the periphery of the source electrode 206a and the drain electrode 206b (on the side opposite to the recess 220), for example, an n + Si film 205 as an ohmic contact layer 205 As a result, the coated portion is not etched in the next silicon etching process, resulting in a problem that the etching accuracy is deteriorated and the TFT element is defective and the yield is lowered. In addition, if the area covered with the deformed resist 212 is designed to be estimated in advance, the area (dot area) required to manufacture one TFT element will increase, and the integration and miniaturization of TFT elements will increase. When it became difficult to respond to the problem, there was a problem!

[0077] これに対し、本実施形態では、表面改質処理によってチャンネル領域となる凹部 2 20以外の n+Si膜 205表面への軟化レジストの流動が抑制されるので、図 9Hに示さ れるように、変形レジスト 212による被覆領域はリフロー処理のターゲット領域である 凹部 220に略限定されている。したがって、高いエッチング精度を確保できるとともに 、 TFTの高集積化、微細化への対応も可能になる。 On the other hand, in the present embodiment, the flow of the softened resist to the surface of the n + Si film 205 other than the recess 220 that becomes the channel region is suppressed by the surface modification treatment, and as shown in FIG. 9H. In addition, the area covered with the deformation resist 212 is substantially limited to the recess 220, which is the target area for the reflow process. Therefore, it is possible to ensure high etching accuracy and cope with high integration and miniaturization of TFTs.

[0078] 次に、リフロー後の変形レジストに対して、軽度のアツシング処理を実施する(ステツ プ S8)。このアツシング処理によって、図 91に示すように変形レジスト 212による被覆 面積をよりいっそう縮小させることができる。したがって、次のステップ S9で実施される エッチングの精度を格段に向上させることができる。なお、このアツシング処理は任意 工程であり、リフロー後の変形レジスト 212の外側(ソース電極 206aおよびドレイン電 極 206bの周囲)へのはみ出しが僅かである場合には、このアツシング工程を省略す ること力 Sでさる。  Next, a light ashing process is performed on the deformed resist after the reflow (step S8). By this ashing process, the area covered by the deformed resist 212 can be further reduced as shown in FIG. Therefore, the accuracy of the etching performed in the next step S9 can be significantly improved. Note that this ashing process is an optional process, and this ashing process may be omitted if there is little protrusion outside the deformed resist 212 after reflow (around the source electrode 206a and the drain electrode 206b). Touch with force S.

[0079] 次に、図 9Jに示すように、ソース電極 206a、ドレイン電極 206bおよび変形レジスト 212をエッチングマスクとして使用し、 n+Si膜 205および a— Si膜 204をエッチング処 理する(ステップ S9)。その後、例えばレジスト剥離液を用いるウエット処理などの手 法により、変形レジスト 212を除去し(ステップ S 10)、図 9Kに示すように、ソース電極 206aおよびドレイン電極 206bを露出させる。 [0080] 次に、ソース電極 206aおよびドレイン電極 206bをエッチングマスクとして使用し、 凹部 220内に露出した n+Si膜 205をエッチング処理する(ステップ Sl l)。これにより 、図 9Lに示すように、チャンネル領域 221が形成される。 Next, as shown in FIG. 9J, the n + Si film 205 and the a-Si film 204 are etched using the source electrode 206a, the drain electrode 206b, and the deformed resist 212 as an etching mask (step S9). ). Thereafter, the deformed resist 212 is removed by a method such as a wet process using a resist stripping solution (step S10), and the source electrode 206a and the drain electrode 206b are exposed as shown in FIG. 9K. Next, using the source electrode 206a and the drain electrode 206b as an etching mask, the n + Si film 205 exposed in the recess 220 is etched (step Sl 1). As a result, a channel region 221 is formed as shown in FIG. 9L.

[0081] 以降の工程は図示を省略するが、例えば、チャンネル領域 221とソース電極 206a およびドレイン電極 206bを覆うように有機膜を成膜した後(ステップ S12)、フォトリソ グラフィー技術によりソース電極 206a (ドレイン電極 206b)に接続するコンタクトホー ルをエッチングによって形成し(ステップ S 13)、次いでインジウム.錫酸化物(ITO) 等により透明電極を形成する (ステップ S14)ことにより、液晶表示装置用の TFT素子 が製造される。  Although the subsequent steps are not shown, for example, after forming an organic film so as to cover the channel region 221, the source electrode 206 a, and the drain electrode 206 b (step S 12), the source electrode 206 a ( A contact hole connected to the drain electrode 206b) is formed by etching (step S13), and then a transparent electrode is formed by indium tin oxide (ITO) or the like (step S14). The device is manufactured.

[0082] 上記実施形態では、ステップ S 7のリフロー工程を行なうことにより、ステップ S 5の電 極用金属膜 206をエッチングする工程と、ステップ S9の n+Si膜 205および a— Si膜 2 04をエッチングする工程を、一回のフォトリソグラフィ一により形成されたレジスト、つ まり、ソース電極用レジストマスク 210、ドレイン電極用レジストマスク 211および変形 レジスト 212により行なうことができるので、フォトリソグラフィー工程数の削減、省レジ スト化が可能になる。さらに、ステップ S6の表面改質処理により、高いエッチング精度 が確保され、 TFT素子の高集積化、微細化へも対応可能になる。 In the above embodiment, by performing the reflow process of Step S 7, the process of etching the electrode metal film 206 of Step S 5, and the n + Si film 205 and the a-Si film 204 of Step S 9 Can be performed by the resist formed by one photolithography process, that is, the resist mask 210 for the source electrode, the resist mask 211 for the drain electrode, and the deformation resist 212, so that the number of photolithography processes can be increased. Reduction and savings can be achieved. In addition, the surface modification process in step S6 ensures high etching accuracy, and can cope with high integration and miniaturization of TFT elements.

[0083] なお、本発明は上記実施形態に限定されることなく種々変形が可能である。  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made.

例えば、上記説明においては、 LCD用ガラス基板を用いる TFT素子の製造を例に 取り挙げたが、他のフラットパネルディスプレイ (FPD)基板や、半導体基板等の基板 に形成されたレジストのリフロー処理を行なう場合にも本発明を適用することができる  For example, in the above description, the manufacture of TFT elements using a glass substrate for LCD was taken as an example, but reflow processing of resist formed on a substrate such as another flat panel display (FPD) substrate or a semiconductor substrate is performed. The present invention can also be applied when performing

[0084] また、本発明のリフロー方法は、ハーフ露光技術および再現像処理を行なう TFTの 製造過程にも適用することができる。 Further, the reflow method of the present invention can be applied to a TFT manufacturing process in which half exposure technology and re-development processing are performed.

産業上の利用可能性  Industrial applicability

[0085] 本発明は、例えば TFT素子などの半導体装置の製造において好適に利用可能で ある。 The present invention can be suitably used in the manufacture of semiconductor devices such as TFT elements.

Claims

請求の範囲  The scope of the claims [1] 下層膜と、該下層膜よりも上層に前記下層膜が露出した露出領域と前記下層膜が 被覆された被覆領域とが形成されるようにパターン形成されたレジスト膜とを有する被 処理体を準備することと、  [1] A processing target having a lower layer film, and a resist film patterned so as to form an exposed region in which the lower layer film is exposed above the lower layer film, and a covered region covered with the lower layer film Preparing the body, 前記被処理体に対して、前記下層膜の前記露出領域をレジストの流動が抑制され るように表面改質処理することと、  Surface-modifying the object to be processed so that resist flow is suppressed in the exposed region of the lower layer film; 表面改質処理後、前記レジスト膜のレジストを軟化させて流動させることにより、前 記露出領域を部分的に被覆することと、  After the surface modification treatment, the resist of the resist film is softened and fluidized to partially cover the exposed region; を含むリフロー方法。  Including reflow method. [2] 前記表面改質処理を、シリル化剤を含む薬液雰囲気中で行なう、請求項 1に記載 のリフロー方法。  [2] The reflow method according to claim 1, wherein the surface modification treatment is performed in a chemical atmosphere containing a silylating agent. [3] 表面改質処理された前記露出領域の純水による接触角が 50度以上になるように 表面改質処理を施す、請求項 1に記載のリフロー方法。  [3] The reflow method according to claim 1, wherein the surface modification treatment is performed so that a contact angle with pure water of the exposed region subjected to the surface modification treatment is 50 degrees or more. [4] 被処理体の被エッチング膜より上層にレジスト膜を形成することと、 [4] forming a resist film above the etching target film of the object to be processed; 前記レジスト膜を露光処理することと、  Exposing the resist film; and 前記露光処理されたレジスト膜を現像処理してレジストパターンを形成することと、 前記被エッチング膜のレジストが形成されて!/、な!/、露出領域に対してレジストの流 動を抑制するように表面改質処理を施すことと、  The exposed resist film is developed to form a resist pattern, and the resist of the film to be etched is formed to prevent the resist from flowing to the exposed area! Applying surface modification treatment to 前記表面改質処理後、前記レジスト膜のレジストを軟化させてリフローさせ、それに よって変形したレジストにより前記被エッチング膜のターゲット領域を被覆するリフロ 一処理を行うことと、  After the surface modification treatment, the resist of the resist film is softened and reflowed, and a reflow treatment for covering the target region of the film to be etched with the deformed resist is performed. 変形後の前記レジストをマスクとして前記被エッチング膜の前記露出領域に対して 第 1のエッチングを行うことと、  Performing a first etching on the exposed region of the film to be etched using the deformed resist as a mask; 変形後の前記レジストを除去することと、  Removing the deformed resist; 変形後のレジストが除去されることにより再露出した前記被エッチング膜のターゲッ ト領域に対して第 2のエッチングを行なうことと、  Performing a second etching on the target region of the film to be etched that is re-exposed by removing the deformed resist; を含む、パターン形成方法。 覆面積を減少させることをさらに含む、請求項 4に記載のパターン形成方法。 A pattern forming method. 5. The pattern forming method according to claim 4, further comprising reducing the covered area. [6] 前記表面改質処理を、シリル化剤を含む薬液雰囲気中で行う、請求項 4に記載の パターン形成方法。 6. The pattern forming method according to claim 4, wherein the surface modification treatment is performed in a chemical solution atmosphere containing a silylating agent. [7] 表面改質処理された前記露出領域の純水による接触角が 50度以上になるように 表面改質処理を行なう、請求項 4に記載のパターン形成方法。  7. The pattern forming method according to claim 4, wherein the surface modification treatment is performed so that a contact angle with pure water of the exposed region subjected to the surface modification treatment is 50 degrees or more. [8] 被処理体は、基板上にゲート線及びゲート電極が形成されるとともに、これらを覆う ゲート絶縁膜が形成され、さらに前記ゲート絶縁膜上に、下から順に a— Si膜、ォーミ ックコンタクト用 Si膜およびソース'ドレイン用金属膜が形成された積層構造体であり 前記被エッチング膜として、少なくとも前記ォーミックコンタ外用 Si膜を含む、請求 項 4に記載のパターン形成方法。  [8] In the object to be processed, a gate line and a gate electrode are formed on a substrate, and a gate insulating film is formed to cover them, and an a-Si film and an ohmic contact are sequentially formed on the gate insulating film from the bottom. 5. The pattern forming method according to claim 4, wherein the Si film for source and the metal film for source / drain are formed, and the etching target film includes at least the ohmic contour external Si film. [9] 基板上にゲート電極を形成することと、 [9] forming a gate electrode on the substrate; 前記ゲート電極を覆うゲート絶縁膜を形成することと、  Forming a gate insulating film covering the gate electrode; 前記ゲート絶縁膜上に、下から順に a— Si膜、ォーミックコンタクト用 Si膜およびソー ス 'ドレイン用金属膜を堆積させることと、  Depositing an a-Si film, an ohmic contact Si film and a source 'drain metal film on the gate insulating film in order from the bottom; 前記ソース'ドレイン用金属膜上にレジスト膜を形成することと、  Forming a resist film on the source / drain metal film; 前記レジスト膜を所定の露光マスクを用いて露光処理することと、  Exposing the resist film using a predetermined exposure mask; 露光処理された前記レジスト膜を現像処理してパターン形成し、ソース電極用レジ ストマスクおよびドレイン電極用レジストマスクを形成することと、  Developing and patterning the exposed resist film to form a resist mask for a source electrode and a resist mask for a drain electrode; 前記ソース電極用レジストマスクおよび前記ドレイン電極用レジストマスクをマスクと して前記ソース'ドレイン用金属膜をエッチングし、ソース電極とドレイン電極とを形成 することと、  Etching the source / drain metal film using the source electrode resist mask and the drain electrode resist mask as a mask to form a source electrode and a drain electrode; 前記ソース電極および前記ドレイン電極で被覆されて!/、な!/、前記ォーミツタコンタク ト用 Si膜の露出領域をレジストの流動が抑制されるように表面改質処理することと、 前記ソース電極用レジストマスクおよび前記ドレイン電極用レジストマスクに有機溶 媒を作用させてレジストを軟化させ、リフローさせることにより、少なくとも前記ソース電 極と前記ドレイン電極との間のチャンネル領域用凹部内の前記ォーミックコンタクト用 Si膜をリフローにより変形したレジストにより覆うリフロー処理を施すことと、 変形後の前記レジストならびに前記ソース電極および前記ドレイン電極をマスクとし て、下層の前記ォーミックコンタクト用 Si膜および前記 a— Si膜をエッチングすることと 変形後の前記レジストを除去して、前記ソース電極と前記ドレイン電極との間のチヤ ンネル領域用凹部内に前記ォーミックコンタクト用 Si膜を再び露出させることと、 前記ソース電極と前記ドレイン電極とをマスクとして、これらの間の前記チャンネル 領域用凹部に露出した前記ォーミックコンタクト用 Si膜をエッチングすることと、 を含む、 TFTの製造方法。 Surface-treating the exposed region of the Si film for the contactor covered with the source electrode and the drain electrode so that the resist flow is suppressed; and An organic solvent is allowed to act on the electrode resist mask and the drain electrode resist mask to soften and reflow the resist, thereby at least the channel region in the channel region recess between the source electrode and the drain electrode. -Applying reflow treatment to cover Si film for Mic contact with resist deformed by reflow, Etching the lower Si film for ohmic contact and the a-Si film using the deformed resist and the source and drain electrodes as a mask, and removing the deformed resist, Re-exposing the silicon film for ohmic contact in the recess for the channel region between the source electrode and the drain electrode, and using the source electrode and the drain electrode as a mask, the channel between them. Etching the Si film for ohmic contact exposed in the concave portion for region, and a method for manufacturing a TFT. [10] 前記リフロー処理の後に、変形後の前記レジストをアツシングしてその被覆面積を 減少させることをさらに含む、請求項 9に記載の TFTの製造方法。 10. The method for manufacturing a TFT according to claim 9, further comprising ashing the deformed resist to reduce a covering area after the reflow process. [11] 前記ォーミックコンタクト用 Si膜および前記 a— Si膜をエッチングする際に、エツチン グが等方的に進行する条件でドライエッチングを行なう、請求項 9に記載の TFTの製 造方法。 [11] The TFT manufacturing method according to [9], wherein when etching the Si film for ohmic contact and the a-Si film, dry etching is performed under a condition in which etching proceeds isotropically. . [12] 前記表面改質処理を、シリル化剤を含む薬液雰囲気中で行なう、請求項 9に記載 の TFTの製造方法。  12. The method for producing a TFT according to claim 9, wherein the surface modification treatment is performed in a chemical atmosphere containing a silylating agent. [13] 表面改質処理された前記露出領域の純水による接触角が 50度以上になるように 表面改質処理を行なう、請求項 9に記載の TFTの製造方法。  13. The method for manufacturing a TFT according to claim 9, wherein the surface modification treatment is performed so that a contact angle with pure water of the exposed region subjected to the surface modification treatment is 50 degrees or more. [14] コンピュータ上で動作し、リフロー処理システムを制御するプログラムが記憶された 記憶媒体であって、 [14] A storage medium that runs on a computer and stores a program for controlling the reflow processing system, 前記プログラムは、下層膜と、該下層膜よりも上層に前記下層膜が露出した露出領 域と前記下層膜が被覆された被覆領域とが形成されるようにパターン形成されたレジ スト膜とを有する被処理体を準備することと、  The program includes a lower layer film, a resist film patterned so as to form an exposed region where the lower layer film is exposed above the lower layer film, and a covered region covered with the lower layer film. Preparing an object to be processed, 前記被処理体に対して、前記下層膜の前記露出領域をレジストの流動が抑制され るように表面改質処理することと、  Surface-modifying the object to be processed so that resist flow is suppressed in the exposed region of the lower layer film; 表面改質処理後、前記レジスト膜のレジストを軟化させて流動させることにより、前 記露出領域を部分的に被覆することと、  After the surface modification treatment, the resist of the resist film is softened and fluidized to partially cover the exposed region; を含むリフロー方法が行なわれるように前記リフロー処理システムを制御する、記憶 媒体。 被処理体に対して表面改質処理を行なう表面改質処理ユニットと、 A storage medium for controlling the reflow processing system such that a reflow method is performed. A surface modification processing unit for performing a surface modification treatment on the workpiece; 表面改質処理後の被処理体上のレジストを溶剤雰囲気中で軟化させて流動化させ るリフロー処理ユニットと、  A reflow processing unit that softens and fluidizes the resist on the target object after the surface modification treatment in a solvent atmosphere; 下層膜と、該下層膜よりも上層に前記下層膜が露出した露出領域と前記下層膜が 被覆された被覆領域とが形成されるようにパターン形成されたレジスト膜とを有する被 処理体に対して、前記下層膜の前記露出領域をレジストの流動が抑制されるように 表面改質処理を行い、表面改質処理後、前記レジスト膜のレジストを軟化させて流動 させることにより、前記露出領域を部分的に被覆するように制御する制御部と、 を備えた、リフロー処理システム。  An object to be processed having a lower layer film, and a resist film patterned to form an exposed region in which the lower layer film is exposed above the lower layer film and a covered region coated with the lower layer film Then, the exposed region of the lower layer film is subjected to a surface modification process so that resist flow is suppressed, and after the surface modification process, the resist of the resist film is softened and fluidized to flow the exposed region. A reflow processing system comprising: a control unit that controls to partially cover.
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