WO2008053858A2

WO2008053858A2 - Interface device and electronic device

Info

Publication number: WO2008053858A2
Application number: PCT/JP2007/071066
Authority: WO
Inventors: Tomoaki Kurosawa; Masaki Horikawa; Hiroshi Kamizono
Original assignee: Gpaphin Co., Ltd.
Priority date: 2006-11-01
Filing date: 2007-10-29
Publication date: 2008-05-08
Also published as: JPWO2008053858A1; WO2008053858A3; JP5252292B2

Abstract

Provided is an interface device of the PCIe standard which can simplify the connection to an external device and realize a high speed and a high efficiency. The interface device includes: a first interface unit having reset signal superimposing means which has a physical layer of the PCIe standard, inserts a reset signal detected from a first electronic device into a reception packet received from the first electronic device, and transmits the reception packet superimposed by the reset signal to a second interface unit; the second interface unit having resent signal generation means which has a physical layer of the PCIe standard, reads thereception packet received from the first packet, and generates a reset signal for resetting the second electronic device upon detection of a reset signal in the reception packet; and means for connecting the first interface unit to the second interface unit by an electric signal or an optical communication.

Description

Specification

Interface device and electronic device

Technical field

The present invention relates to an interface device and an electronic device, and more particularly, to an interface device and an electronic device having a serial interface using the PCI Express (PCIe) standard.

Background art

[0002] PCs (personal computers) have various I / Fs (interfaces) corresponding to each device so that various peripheral devices can be connected inside and outside to increase the storage capacity and functions. I have. The motherboard, the main PC component, has various I / Fs for connecting to external devices. Typical examples are portable music players, memory devices, external hard disks, General purpose such as USB (Unversal Serial Bus) that transfers data with printers, scanners, etc., PCI bus that can add various I / F functions in the form of interface cards corresponding to low to high speed data transfer In addition to highly functional I / Fs, there are dedicated I / Fs with limited applications such as SATA (SerialATA) for adding HDDs and LAN connection.

[0003] PCs often use interface cards when connecting to various peripheral devices, networks, etc., but as the mainstream interface card standard, desktop PCs have a board shape. PCI buses, PCI-X buses that have been upgraded to a higher speed by upgrading PCI, and PCIe, which has been made even faster by serialization. PC Ie is a serial-based I / O (input / output) standard, like USB, IEEE1394, SATA, Hiper—Transport InfiniBand, and so on.

[0004] The PCI standard is an industry standard architecture that was developed by PCI—PCI Special Interest Group (SIG) and has been continually improved since version 2 of 1993, with a 64-bit bus and a 64-bit bus. This includes a 64-bit bus specification for the CPU! /, A parallel bus with a maximum bus clock of 33 MHz and a transfer rate of 132 bytes / second (peak value) on a 32-bit data bus. As an interface card for PC There are some examples as in Patent Document 1.

[0005] The PCI Express (PCIe) standard is a serial bus that has been further increased from the conventional parallel transfer PCI bus and the PCI-X bus that has been expanded to expand the PCI bus standard. The point of transfer is the biggest difference from these. The PCIe standard uses a low-voltage differential serial signal system of 0.8V to connect devices by point points (one-to-one), with two signals in one direction of the differential pair and a total of four signals in both directions. The number of configured lanes can be increased as needed, and the standard has a one-way transfer rate of 2.5 Gbps per lane, and a configuration of up to 32 lanes is specified, which broadens the bandwidth. The physical layer (PHY) that can

[0006] The PCIe standard employs a hierarchical architecture that was not found in the conventional PCI standard, and has a configuration similar to the structure of the network standard, such as serial transfer and transfer in units of packets. The standard, software, protocol, media, and implementation (mechanism) specifications are changed from those defined collectively, and are defined in the transaction layer, data link layer, and physical layer. The transaction layer regulates message transmission / reception and interrupts, the data link layer regulates CRC (cycle redundancy check), packet loss, and retry in case of error. Stipulates configuration and configuration.

[0007] When connecting a PC and an external device (externally connected peripheral device) using such an interface card, the interface card is generally connected to a circuit for interfacing with the inside of the PC and the external device. Circuit (application part). Conventionally, the interface part with the PC has been transferred data by parallel signals such as PCI bus and PCI—X bus. In the PCIe standard, the interface with the PC is a physical layer called PHY (SerDes: Serialize Deserialize). This is done by serial transfer as defined by the lowest layer (layer 1) of the OSI hierarchical model.

[0008] Explaining the case where data is transmitted and received between an external device and a PC. Data transmitted to the external device power PC is transferred to the interface card mounted on the PC by cable connection, and mounted on the PC. Sent from the interface card to the motherboard of the PC. In the opposite case, data is transferred from the PC mother board to the external device via the interface card. Is sent. At that time, アプリケーション 802.3 is installed as an application for network interface cards, and an interface such as IEEE1394 is adopted for digital video. If the application is video compression, the interface card is equipped with a video data compression circuit, and this data is transferred to the necessary memory via the PC's motherboard.

[0009] When listing examples of combinations of these main interface cards, in the case of network cards, external devices are LAN, HUB, etc., and the cable transfer method is IEEE802.3ab (1000Base-T), etc. . In the case of SATA compatible RAID (Redundant Arrays of Inexpensive Disks) cards, the external device is HDD (Hand Disk Drive) and the cable transfer method is SATA (1.5G serial method). In the case of a video capture card, the external device is an analog VTR, etc., the cable transfer method is RS-170 / NTSC, etc., and the interface card performs Video MPEG2 (Moving Picture Experts Group phase 2) conversion. In the case of a DVC capture card, the external device is a DVC (digital video camera) and the cable transfer method is IEEE1394. In the case of industrial camera capillaries, the external device is an industrial camera, and the cable transfer method is mostly a dedicated method, and the interface card encodes and decodes data of this dedicated method and connects to the PC. In a medical X-ray device, the external device is a medical X-ray device, the cable transfer method is a dedicated method using an optical cable, and the interface card is based on data encoding and decoding of the dedicated method and optical-electrical signal conversion. Connect to a PC, etc.

[0010] As described above, such an interface card is often used to connect an external device and a PC. In order to connect an external device and a PC, the external input / output (I / O) of the external device is used. ) Can be converted to PCI or PCIe, which is the I / O of the PC, by the interface card. The PC interface card can be installed in large ways: (1) One-chip LSI system in which simple network protocols such as NIC are integrated into a single-chip LSI and mounted as an interface card; (2) PC side of PCI or PCIe Conversion to interface between peripheral interface and I / O of peripheral equipment. (3) FPGA (Programmable logic circuit: Program rewritable ASIC) etc. In addition, the application built-in method including the application part can be divided into the device built-in method implemented on one FPGA, and (4) the I / O part and the application can be divided into device separation methods realized by separate LSIs and FPGAs. When the interface on the PC side is PCIe, in general, an expensive device with high-speed SerDes is required to implement the physical layer with FPGA.

[0011] On the other hand, the PC interface card can be thought of as interfacing with the PC by converting the I / O of the external device and adding processing for each application in order to connect the PC and the external device with a cable. . When connecting dedicated external devices such as HDDs and monitors, the interface card has cable transfer methods and protocols that support SATA for HDD and DVI for monitors and liquid crystal displays, and each process (processing by application) Connected to the PC via PCI or PCIe.

[0012] Therefore, in PCs and external devices, when data and control signals are transferred via a cable, when the cable length is long, a network transfer method such as LAN is reliable for transfer such as TCP / IP. However, in the PtoP connection between the above-mentioned SATA, DVI, various peripheral devices, external devices, etc. and a PC, a protocol that requires a retransmission is not used, but a physical protocol is used. There are few cases of data transfer only with simple connection.

[0013] For example, when connecting a DVI monitor to a PC with a graphics card that supports the PCIe standard, the data transfer in the DVI standard used to connect the liquid crystal display is the physical layer of the graphics power (TMDS : Differential serial transfer) is the main video data transfer, and the communication protocol for automatically determining what kind of monitor is connected is the existing force S, data retransmission is performed by collision detection, etc. There is no advanced communication protocol. In such a case, it should be noted that the connection between the graphic card and the liquid crystal display is a connection between physical layers that perform cable transfer.

[0014] The physical layer used for this transfer uses a differential serial transfer method called TMDS in the DVI standard, and iLINK (IEEE 1394) also uses the differential serial transfer method. When connecting to an external device such as analog NTSC or composite for the video signal of the TV, the I / O specification of the device is used, or if a new specification is adopted, the application, distance, and transfer Depending on speed, cable cost, etc., which transfer method is used is decided. Patent Document 1: Japanese Patent Laid-Open No. 08-288977

Disclosure of the invention

Problems to be solved by the invention

[0016] By adopting PCIe in the PC, it becomes possible to mount an interface card that can realize high-performance and high-speed signal transfer, although the cost is rather high. However, in the method of mounting the interface card on the PC in the conventional manner as described above, it is necessary to overlap the physical layer for cable connection on both the interface card and the external device. This was a wasteful configuration, and there was a problem that the system was complicated and the cost was increased.

[0017] Therefore, the present invention improves efficiency by using a PCIe standard physical layer for signal transfer between an interface card mounted on a PC (or control device) and an external device (an externally connected electronic device). In particular, control signals such as a reset signal from a PC (or control device) that was previously required separately from the PCIe standard signal are superimposed and transferred within the PCIe standard packet signal. An object of the present invention is to provide an interface device and an electronic device having a PCIe interface capable of realizing a high-speed and high-efficiency signal transfer while simplifying the configuration of the interface card as compared with the prior art.

Means for solving the problem

[0018] An interface device according to the present invention made to achieve the above object includes a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device, and a second interface unit. A connector for a metal cable for transferring a signal by an electrical signal for connecting between the first interface unit and the second interface unit having at least a PCIe standard physical layer to be connected to the electronic device; At least an optical transceiver configured to transmit a signal by communication and an optical communication cable connector, and the first interface unit receives a first signal other than the PCI e standard serial signal from the first electronic device. When the second signal is transmitted, the second signal is assembled in the packet signal of the PCIe standard serial signal received from the first electronic device. And includes a signal superimposing means for transmitting the packet signal on which the second signal is superimposed to the second interface unit, wherein the second interface unit is the first interface unit. When the received packet signal is read and the second signal is detected in the packet signal, the second signal is extracted and the second signal is transmitted to the second electronic device. It has a number extraction means.

[0019] Further, an interface device according to the present invention made to achieve the above object includes a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device, and a second interface unit. A second interface unit having at least a PCIe standard physical layer to be connected to the electronic device, and a metal cable connector for transferring a signal by an electrical signal for connecting between the first and second interface units, Or at least an optical transmission module comprising an optical transceiver for transmitting signals by optical communication and an optical communication cable connector, and the first interface unit detects a reset signal from the first electronic device. A packet signal in which the reset signal is embedded in the packet signal received from the first electronic device and the reset signal is superimposed on the packet signal. Reset signal superimposing means for transmitting to the second interface unit, wherein the second interface unit reads the packet signal received from the first interface unit, and reset signal is included in the packet signal; And a reset signal generating means for generating a reset signal for resetting the second electronic device when the second electronic device is detected.

Furthermore, an interface device according to the present invention made to achieve the above object is

A first interface unit having at least a PCIe (PCI Express) standard physical layer connected to the first electronic device, a second interface unit having at least a PCIe standard physical layer connected to the second electronic device, and An optical transmission module comprising a metal cable connector for transferring a signal by an electrical signal or an optical transceiver and an optical communication cable connector for transferring a signal by optical communication for connecting between the first and second interface units; , And the first interface unit sends an inquiry signal to the second interface unit as to whether it can detect a reset signal superimposed on the packet signal and sent from the first interface unit. A reset detection inquiry means for transmitting and receiving the response signal; and the second interface section in the reset detection inquiry means. There is a response enabling discovery of the reset signal, and when detecting a reset signal from said first electronic device, built the reset signal to the first in the packet signal received from the electronic device, 該Ri Reset signal superimposing means for transmitting the packet signal superimposed with the set signal to the second interface unit.

Here, when the second interface unit receives the inquiry signal from the first interface unit, the second interface unit can detect a reset signal superimposed in a packet signal received from the first interface unit. A response signal is transmitted to the first interface unit, and when a reset signal is detected in the packet signal received from the first interface unit, a reset signal for resetting the second electronic device is generated. It has a reset signal generating means to perform.

In addition, the second interface unit includes clock recovery means for recovering and generating a clock signal based on the packet signal and the external reference signal.

The first and second interface units may include a transmission compensation circuit for extending a transmission distance during signal transfer.

Further, the first and second interface units have a multilink function of performing signal transfer with a single electronic device using a plurality of lanes.

Further, the first or second interface unit further includes a PCIe standard-compliant HUB device that is connected to a plurality of electronic devices and performs signal transfer of a plurality of channels.

[0021] An electronic device according to the present invention made to achieve the above object includes a PCIe standard physical layer connected to a control device and an interface unit having at least a PCIe control unit for controlling signal transfer based on the PCIe standard. At least a main body control unit that mutually converts and connects communication standards between the electronic device main body and the interface unit, and the PCIe control unit passes through the interface unit from the control device. And a reset signal generating means for generating a reset signal for resetting the electronic apparatus main body when the received packet signal is read and a reset signal is detected in the packet signal.

The invention's effect

[0022] According to the present invention, the interface configuration of the interface card and the external device is achieved by connecting the PC and the external device (externally connected electronic device) via the PCIe standard physical layer and transmitting the signal. The logic on the interface card mounted on the PC can be simplified. It can be simplified as a connector board type that can be reduced, and the interface card can be a common card unrelated to the types of external devices.

In addition, the transmission speed of the transmission system between the PC and the external device is increased by superimposing and transmitting control signals such as reset signals not included in the PCIe standard on the PCIe standard packet signal between the PC and the external device. This also has the effect of simplifying the configuration even when connecting cables. At that time, it is determined whether or not to superimpose the sideband signal depending on whether or not the external device has a function capable of detecting a sideband signal such as a reset signal superimposed on the packet signal. The possibility of malfunctions of external devices that cannot be handled can be eliminated. Furthermore, when an optical communication cable is used, the noise resistance performance can be improved and a long-distance connection between devices can be achieved.

Brief Description of Drawings

FIG. 1 is a configuration diagram of an interface device and an electronic device according to an embodiment of the present invention.

2 is a block diagram of the interface unit (1) shown in FIG.

FIG. 3 is a block diagram of the interface unit (2) shown in FIG.

4 is another configuration diagram of the interface unit (1) shown in FIG.

FIG. 5 is another configuration diagram of the interface unit (2) shown in FIG.

FIG. 6 is a configuration diagram using a transmission compensation circuit.

[Fig. 7] Configuration diagram of PtoN transmission method using PCIe-compatible HUB.

FIG. 8 is a configuration diagram in which PCIe signals are aggregated.

FIG. 9 is a configuration diagram of a camera system according to an embodiment of the present invention.

FIG. 10 is a schematic configuration diagram of a conventional camera system.

FIG. 11 is a configuration diagram in which a reset signal is superimposed on the camera system shown in FIG.

FIG. 12 is a configuration diagram of a conventional camera system.

Explanation of symbols

[0024] 1, 11 Interface (I / F) section with physical layer of PCIe standard

2, 12 PCIe controller

3, 13 Serial Parallel converter

4, 4a K code converter for reset 5, 15 Parallel Serial converter

6, 16 Electric-light converter

7, 17 Optical-electrical converter

10 Signal transmission Cape Nore

10a Optical Communication Cape Nore

10b coaxial cable

14, 14a Idle K code converter

18 PCIe devices

19 Main unit controller

21 Optical transceiver

22 Transmission compensation circuit

23 Coaxial connector

24 PCIe HUB

25 PCIe X 4inlOGbps conversion

26 lOGbps optical transceiver or InfiniBand X 4 connector

101 PCIe compatible interface card

102 Electronic equipment (external equipment)

103 Industrial CCD camera

104, 112 Camera Control Department

105 Oscillator (〇SC)

106 Power-on reset circuit

107 Reset switch

110 Conventional PCIe compatible interface card

111 PCIe control and converter

113, 114 LVDS driver & receiver

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an interface device and an electronic device according to an embodiment of the present invention. 2 shows the configuration of the interface unit (1), and FIG. 3 shows the configuration of the interface unit (2). In the present embodiment, a reset signal (control signal) is taken as an example of the second signal other than the PCIe standard signal, and this second signal is superimposed on the PCIe standard serial signal packet. The case of transmission to (external device) will be described.

In FIG. 1, reference numeral 101 denotes a PCIe compatible interface card connected to a PCIe bus mounted on a control device (first electronic device) configured by a PC or a computer system. The interface part (1) 1 is provided. Reference numeral 102 denotes a second electronic device (external device) that is externally connected to a PC or a control device via a signal transmission cable 10 such as an optical communication cable, a coaxial cable, or a twisted cable via the interface card 101. The second interface unit (2) 11 includes a PCIe device 18 that transmits and receives PCIe signals, and a main body control unit 19 that controls the electronic device main body. The first interface unit (1) 1 has a first PCIe control unit (1) 2 for transmitting a reset signal, which will be described later, superimposed on a packet signal, and the second interface unit (2) 11 The second PCIe control unit (2) for extracting the superimposed reset signal from the packet signal transmitted from the first interface unit (1) 1 and received via the signal transmission cable 10 Has 12.

[0027] The functions in the first interface unit (1) 1 and the second interface unit (2) 2 corresponding to the PCIe standard are all functions including the main body control unit 19 of the electronic device 102, or individual functions. Functions are combined and implemented by one or more LSIs or FPGAs. In addition, the PCI e standard (standard verl. La established in July 2002) performs high-speed differential serial transfer of 2.5 Gbps per lane per lane, but because of the high speed, the total extension distance is extended with a metal cable. Has its limits. Therefore, to increase cable transmission efficiency, adopt cables and connectors with high transmission efficiency, adopt optical transmission modules that perform OE (Optical / Electrical) conversion, add transmission compensation circuits, etc. in cable transmission. Thus, stable cable transmission can be realized.

As shown in FIG. 2, the first interface unit (1) 1 according to the present embodiment has a first PCIe control unit (1) 2 and is provided on the electronic device 102 side. (2) and optical communication cable 1 It has an electro-optical conversion unit 6 and a photoelectric conversion unit 7 for communication connection via Oa. PCIe pair with first interface part (1) 1 inserted into the PCIe bus of PC The interface card 101 includes a PCIe signal (Tx) of a serial packet signal transmitted from the PC and received by the electronic device 102, and a PCIe signal (Rx) of a serial packet signal transmitted from the electronic device 102 and received by the PC. In addition, the sideband signals of the reference clock RefCLK signal and the reset signal that are not included in the PCIe standard signal are supplied.

[0029] The PCIe physical layer can be divided into two logical sub-blocks that perform coding and link control and electrical sub-blocks that perform signaling. In the logical sub-block, the data link layer is A special code (K code) indicating the boundary of the packet is added to the passed TLP (Transaction Layer Pakcet) or DLLP (Data Link Layer Packet) at the beginning and end. In the case of TLP, the STP ( Start of TLP) Force is also added at the end so that the number of bytes until END becomes a predetermined number;! ~ 3 K codes called PAD may be inserted between TLP and END.

[0030] The data divided into each lane is scrambled and 8b / 10b converted (8bits / 10bits conversion) for each lane, and transmitted as serial data. 8b / 10b conversion has the disadvantage that the effective transfer amount becomes 80% S, and there is no long crossing point between consecutive “0” and “;!”! /, The state continues, and it has features such as easy clock recovery and AC coupling due to DC balance. The code space is expanded by 8b / 10b conversion, and a control code called K code can be added here.

[0031] Here, in the 8b / 10b conversion, each bit of 8 bits from LSB (least significant bit) to MSB (most significant bit) is called ABCDEFGH, which is divided into two groups, EDC BA and HGF. In this order, if the data is Dx. Y, and the K code is Κχ · y, then if the data is 001 10000b (Nonari) and Κ code force 01 1 1 1 100b, the data is HGF = Since 001b and EDCBA = 10000b, it can be expressed as D 16.1, and the K code can be expressed as K28.3 because HGF = 01 1b and EDCBA = 1 1 100b.

[0032] In the embodiment of the present invention, an undefined K code in the PCIe standard is assigned as a reset code. As shown in FIG. 2, the first PCIe control unit (1) 2 includes a PCIe code. Sideband that is not included in the serial signal transmitted by the PCIe standard after receiving the PCIe signal (Tx) that is a standard serial transmission signal and converting it to a parallel signal by the serial / parallel converter 3 A reset signal, which is one of the signals, is received from the PCIe bus, and this reset signal is converted into a K code defined for resetting in the K code part and inserted as, for example, K24.4. Here, the PCIe signal (Tx) transmitted from the PC is a serial signal in which 8bits data is converted to 8b / 10b, and the serial-to-parallel converter 3 parallelizes the lObits pattern including the K code to the D code. Perform conversion.

[0033] The reset K code conversion unit 4 monitors the reset signal and K code, and if it detects that the reset signal is active, it indicates an IDL (idle) K code indicating that there is no data to be transmitted on the serial bus. (Example: Κ28 · 3) is assigned and replaced with a K code undefined in the PCIe standard (eg, Κ24 · 4) for resetting, and this reset K code is superimposed on the Tx signal. The D code of the lObits pattern obtained by converting the K code and the transmission signal including the K code are converted again to a serial signal by the normal-reel serial conversion unit 5 at the subsequent stage. The converted serial signal is converted into an optical signal suitable for the optical communication cable 10a by the electrical-optical conversion unit 6, and is connected to the outside via the optical communication cable connector and the optical communication cable 10a ( (External device) sent to 102 (reset signal superimposing means or signal superimposing means)

As shown in FIG. 3, the optical signal that has reached the electronic device 102 is converted into an electrical signal by the optical-electrical conversion unit 17 provided in the interface unit (2) 11 provided on the electronic device 102 side. The converted serial signal is extracted from the reset signal by the PCIe control unit (2) 12, converted into the original serial signal, and delivered to the PCIe device 18 and the main body control unit 19. The PCIe control unit (2) 12 converts the received serial signal into a parallel code having an lObits pattern by the serial / parallel conversion unit 13, and passes the signal to the idle K code conversion unit 14.

[0035] The K code conversion unit for idle 14 monitors the K code and, when detecting the K code assigned for reset, generates a reset signal for the PCIe device 18 or the main body control unit 19 and outputs the signal. Is activated and the reset K code (eg Κ24 · 4) is replaced with the original IDL K code (eg K28.3) and sent to the parallel-serial converter 15. The lObits pattern signal replaced with the original IDL K code is converted to the original serial signal via the parallel serial converter 15 and sent to the PCIe device 18. to this Further, the PCIe device 18 can receive the PCIe signal (Tx) and perform an appropriate operation (reset signal generation means or signal extraction means).

On the other hand, the PCIe signal (Rx) output from the PCIe device 18 side of the electronic device 102 is converted into an optical signal by the electrical-to-optical conversion unit 16 of the interface unit (2) 11, and the optical communication cable 10 a Is sent to the PC interface card 101 side. The optical signal that has reached the interface card 101 is converted into an electrical signal by the optical-to-electric conversion unit 7 of the interface unit (1) 1 and delivered to the PCIe bus. Thereby, the PC (or control device) can receive the PCIe signal (Rx) from the electronic device (external device) 102 and perform an appropriate operation.

[0037] The reference clock (RefCLK, Ref Clock: 100MHz) of the sideband signal shown in Fig. 1 and Fig. 2 is used as a clock signal for serial-parallel conversion and parallel-serial conversion of the PCIe controller (1) 2. Although not shown, a clock signal actually required is generated by a DLL (Delay Locked Loop) or PLL (Phase Locked Loop) configuration.

[0038] The configuration of the serial / parallel conversion units 3, 13, the reset or idle K code conversion units 4, 14, and the parallel / serial conversion units 5, 15 shown in FIGS. First-In First-Out buffer is used to superimpose or extract the reset signal described above.

[0039] On the electronic device 102 side, a clock signal is regenerated from the received serial signal and used as a clock signal for serial-parallel conversion and parallel-serial conversion of the PCIe control unit (2) 12. The data recovery circuit and its operation are omitted (not shown in Fig. 3).

[0040] It should be noted that when detecting the K code assigned for resetting, in order to avoid false detection due to noise on the transmission path, the reset signal is only generated when the κ code is detected for a predetermined number of times. It may have a function to activate.

[0041] Next, referring to FIG. 4 and FIG. 5, in the configuration and processing for the electronic device 102 that cannot extract a sideband signal such as a reset signal superimposed in the received serial packet signal, Tsu!

[0042] The difference between the configuration shown in FIGS. 2 and 3 is that sideband signals such as a reset signal are serialized. Before superimposing in the nore packet signal, the electronic device 102 is inquired whether or not the sideband signal superimposed in the serial packet signal can be detected. In this way, it is possible to connect to an unspecified electronic device 102 by inquiring in advance whether or not the serial packet signal on which the sideband signal is superimposed can be processed. In this case, the present invention can also be applied to a case where only a part of the sideband signals can be recognized, not whether or not all sideband signals can be recognized. In other words, it can be applied to the case where the K code assigned to the reset signal can be recognized but the unrecognizable K code assigned to other sideband signals cannot be processed. Hereinafter, a reset signal will be described as an example of the sideband signal.

[0043] FIG. 4 shows a reset K code conversion unit 4 shown in FIG. 2 replaced with a reset detection inquiry signal transmission function and a reset detection confirmation function (reset detection inquiry means) based on the response signal. It is one Example of the K code conversion part 4a. Therefore, a detailed description of the functions overlapping those in FIG. 2 is omitted.

[0044] The PCIe control unit (1) 2 on the PC side according to the present embodiment is in communication connection with the electronic device 102 via the optical communication cable 10a. The PCIe control unit (1) 2 receives a PCIe signal (Tx), which is a serial transmission signal of the PCIe standard, from the PC, and converts it into a parallel signal by the serial / parallel conversion unit 3. At that time, as the first packet signal transmitted from the PC side, an inquiry signal is transmitted to inquire whether or not a reset signal superimposed as a code on the PCIe signal (Tx) can be detected. A response signal (A CK (Acknowledgment), etc.) cannot be obtained even after a predetermined time has passed from the electronic device 102 that has received the inquiry signal! /, Or if the inquiry signal cannot be interpreted (NACK (Negative Acknowledgment, etc.) If there is a response, the reset K code conversion unit 4a does not superimpose the reset signal on the subsequent packet signal, and the parallel signal is converted from the parallel signal to the serial packet signal by the parallel serial conversion unit 5, and remains as it is. Send.

[0045] Here, the inquiry signal may be transmitted as a K code defined as the inquiry signal, or may be added before or after the first serial packet signal. Unlike the example in Fig. 4, it may be incorporated into the communication protocol as the first packet signal sent from the PC. When the reset signal is not superimposed, a configuration in which the serial / parallel conversion unit 3 and the parallel / serial conversion unit 5 of the PCIe control unit (1) 2 are passed is also possible. When electronic device 102 having received the reset detection inquiry signal from the PC side has a reset signal detection function, it transmits a reset detection response signal to the PC side in response to the inquiry signal from the PC side. If the electronic device 102 receives the reset detection response signal from the electronic device 102 and determines that the electronic device 102 has a reset signal detection function, the reset K code conversion unit 4a on the PC side then transmits the serial signal transmitted according to the PCIe standard. When a reset signal not included in the signal is received from the PCIe bus, the K code defined for reset is inserted into the K code part in the serial packet signal transmitted from the PC and transmitted to the electronic device 102. .

The details of the confirmation of the reset detection response signal are not shown in FIG. 4, but are converted into parallel data by the serial / parallel converter in the same way as the processing on the electronic device 102 side shown in FIG. 3, and the signal is interpreted. After that, there are a method of returning to the original serial packet signal by the parallel-serial converter, and a method of directly interpreting the serial packet signal by a circuit provided separately. In the case of a configuration similar to the method shown in Fig. 3, a response signal can be assigned to the K code part. Unlike the example in Fig. 4, serial packet signals received on the PC side may be incorporated into the transmission / reception protocol so that they can be directly interpreted.

FIG. 5 shows an idle K-code conversion in which the idle K-code conversion unit 14 shown in FIG. 3 is replaced with a reset detection inquiry signal reception function and a reset detection response function for generating a response signal. This is an example of the unit 14a. Therefore, a detailed description of the functions overlapping those in Fig. 3 is omitted.

[0049] The PCIe control unit (2) 12 on the electronic device 102 side according to the present embodiment is communicatively connected from the PC side via the optical communication cabinet 10a. The optical signal that has reached the electronic device 102 is converted into an electrical signal by the optical-electrical conversion unit 17 on the electronic device 102 side, and converted into a parallel signal by the serial / parallel conversion unit 13 of the PCIe control unit (2) 12. When the idle K-code conversion unit 14a of the electronic device 102 shown in FIG. 5 receives the reset detection inquiry signal as to whether or not the reset signal superimposed in the packet signal can be detected, it responds to the reset detection inquiry signal. Send a reset detection confirmation response signal to the PC. If a signal other than the reset signal cannot be interpreted! /, A NACK is returned when a signal is received. As described above, the electronic device 102 that does not have a function to detect the reset signal superimposed in the received packet signal and cannot respond to the reset detection inquiry signal also has a response signal to the reset detection inquiry signal on the PC side. Predetermined time Since it cannot be obtained even after elapse of time, the reset signal is not superimposed on the subsequent transmission packet signal.

[0050] The PCIe control unit (2) 12 on the electronic device 102 side that has transmitted the reset detection confirmation response signal in response to the reset detection inquiry signal received from the PC side performs the reset superimposed on the packet signal received thereafter. When the signal is detected, the idle K code conversion unit 14a shown in FIG. 5 extracts the reset signal superimposed on the packet signal, and replaces the reset K code with the idle K code and delivers it to the PCIe device 18. When a K code assigned for reset is detected, a reset signal is generated for the PCIe device 18 or the main body control unit 18 and the signal is activated. Here, the inquiry signal may be assigned as a K code, or may be configured to be added before or after the first serial packet signal. Also, unlike the example in Fig. 5, it may be incorporated into the communication protocol as the first packet signal for transmission / reception with the PC.

[0051] FIG. 6 is a configuration diagram using a transmission compensation circuit for the transmission of the above-mentioned PCIe standard serial signal, and shows a case where the transmission compensation circuit 22 suitable for the transmission speed and transmission distance of the PCIe standard is used. Yes. The transmission compensation circuit 22 is connected between the PCIe control unit (1) 2 of the interface unit (1) 1 and the coaxial connector 23, and between the coaxial connector 23 of the interface unit (2) 11 and the PCIe control unit (2) 12. By using such a transmission compensation circuit 22, the cable transmission distance can be extended even when the coaxial connector 23 and the coaxial cable 10 b are used for signal transmission. Note that the embodiment shown in FIG. 6 can be applied by optimizing the transmission compensation circuit for optical communication even when using the optical fiber communication cable 10a that uses the coaxial cable 10b for serial signal transmission. Is possible.

[0052] In the PCIe standard, as described above, code conversion by 8b / 10b encoding is performed so that a state where there is no cross point for a long time does not continue due to continuous "0" or "1". Adopting power to ease restrictions on wiring Even if code conversion by 8b / 10b encoding is performed, up to 5 consecutive "0" or "1" may continue. If the same value continues, it is specified that when the second signal is sent, de-emphasis transfer is performed on the transmitting side so that the transmitting side reduces the amplitude and increases the noise margin of the signal received on the receiving side. ing. [0053] FIG. 7 shows a case where signals are transmitted to a plurality of electronic devices 102 # 1 to 4 using a plurality of lanes, and is a configuration diagram of a PtoN transmission method using a PCIe-compatible HUB device. A configuration is shown in which one PC and multiple (four in the figure) electronic devices 102 # 1 to 4 are connected by using PCIe-compatible HUB devices. The PCIe controller (1) 2 on the interface card 101 side and four optical transceivers 21 #;! To 4 are equipped with a PCIe-compatible HUB24, and four optical transceivers 21 # ;! from this PCIe-compatible HUB24 Branch to -4, and control each electronic device 102 # 1-4 via the optical communication cable 10a and each optical transceiver 21 in the electronic device (external device) 102 # 1-4. In this case, the transmission method using the optical transceiver 21 and the optical communication cable 10a as well as the transmission method using the coaxial cable 10b can be realized. In this case, the reset signal can be transmitted by being superimposed on the packet signal for each of the four lanes, or can be transmitted only to the required electronic devices 1 02 # 1 to 4. .

[0054] Figure 7 shows a PtoN configuration with a PCIe-compatible HUB24 on the PC interface card 101 side. However, the PCIe-compatible HUB24 is installed on the electronic device 102 side, and each optical transceiver 21 # from the PCIe-compatible HUB2 4 Branch to 1 to 4 (4 units) and connect to the optical transceiver 21 of the PCIe interface card 101 inserted into each PC # 1 to 4 via the optical communication cable 10a, and the data is sent to each PC # 1 As shown in FIG. 7, one electronic device 102 and one PC may be applied to a plurality of configurations.

FIG. 8 is a configuration diagram in which PCIe signals are aggregated, and is a configuration in which transmission using an optical communication cable or transmission based on the InfiniBand standard is used for serial transmission.

The InfiniBand standard (communication standard promoted by industry groups) uses a composite cable that can extend 2.5 Gbps transmission per lane by 10 meters and a high transmission efficiency connector in order to increase speed. It is possible to use such commercially available collective cables and connectors for PCIe cable transmission. The InfiniBand standard currently defines Xlch, X4ch, and X12ch composite cables and connectors. As an example of cable aggregation using this, in the case of Figure 8, PCIe X 4 (T x + / —, Rx +/— X 4ch) is transmitted using 4 channels of the InfiniBand standard. InfiniBand X 4ch aggregate cable is used. [0056] The case where the PCIe signal was directly loaded onto the capeule as transmission using the InfiniBand standard cable was explained. However, in the case of using a high-speed interface, the lane per PCIe lane can be used with multiple lanes. 2. Collect several channels of 5Gbps signals, convert them to a high-speed interface with an expanded signal band, and transmit the signals to the electronic device 102.

[0057] For example, when 4ch of 2.5Gbps signal is input, PCIe X 4inlOGbps conversion 25, which is a high-speed interface that can be synthesized and converted to differential serial of lOGbps, is used for IJ and transmits PCIe X 4 Power S can be. In order to transmit lOGbps, OE (optical one-electric) conversion is performed by optical transceiver 26, and the power that can be transmitted by optical communication cable 10a is so fast that it is possible that lOGbps can be transmitted by metal cable in the near future. is expected. In this case, the reset signal should be superimposed on one of the lanes without having to be superimposed on the packet signals of all four lanes! /.

FIG. 10 is a configuration diagram of a conventional industrial CCD camera system connected to a conventional PCIe interface card 110 provided with a PCIe interface on the PC side for comparison. Until now, using a specific product such as the power industrial CCD camera 103 that explained general cable transmission, transmission by the interface having the PCIe physical layer of the present invention is performed by a PC (or control device). ) And the electronic device 102 are used for cable transmission, which proves the power and the effect of which part is actually cost-saving.

[0059] Figure 10 shows a conventional PCIe interface card (industrial camera capture card) 110, for example, an industrial product that outputs 2048 1024 dots 3 (^ 丫 1; ¥ 161 ^). FIG. 3 is a general block diagram when the CCD camera 103 is connected to a PCIe-capable interface card (PCIe standard) 110 for PC capture by an optical transceiver.

[0060] In this case, the video data from the industrial CCD camera 103 is 960Mbps (120MB / sec), which is a simple calculation of data that is easy to calculate. In addition, if 8b / 10b conversion is added to reduce serial transmission errors, a transfer rate of 1.2Gbps (150MB / sec) is required at a minimum.

An outline of the control operation along the data flow will be described. First, the industrial CCD camera 103 performs imaging of the image sensor CCD sensor by driving the CCD with the CCD controller. The transmission control unit controls the captured moving image data so that it can be transmitted. 1. 25Gbps interface In the processing unit, the moving image data is converted into differential serial that drives the optical transceiver 21. A differential serial signal is transmitted from the optical transceiver 21 on the industrial CCD camera 103 side to the optical transceiver 21 of the PCIe interface card 110 on the PC side via the optical communication cable 10a. In the PCIe compatible interface card 110, 1. The differential serial signal is converted into LVTTL (Low Voltage TTL), etc., with a 25Gbps interface, and the transmission control unit controls the video data to be received. The bridge controller performs control so that it can be passed to the PCIe bridge, and the PCIe bridge performs PCIe conversion and transmits the PCIe standard signal to the PCIe connector on the PC mother board on the PC side.

FIG. 9 is a block diagram of an embodiment in which the circuit of FIG. 10 is improved by moving the PCIe interface to the external device side, ie, the industrial CCD camera 103 side, based on the present invention. The industrial CCD camera 103 shown in FIG. 9 controls the image sensor CCD sensor with a CCD control unit to capture an image. The bridge controller controls this imaging signal so that it can be passed to the PCIe bridge, the PCI e-bridge performs PCIe conversion, and the PCIe interface signal is sent from the optical transceiver 21 via the optical communication cable 10a to the interface card on the PC side. Transmit to 101 optical transceiver 21. The PC-side interface card 101 transmits to the PC motherboard via the PC PCIe connector.

In this way, comparing the configuration of the conventional FIG. 10 with the components of FIG. 9 according to the present invention, the PC-side interface card 101 has a configuration with only an optical transceiver, and a significant cost saving can be realized.

Finally, an embodiment in which a reset signal is incorporated in signal transmission with the industrial CCD camera 103 described with reference to FIGS. 9 and 10 will be described with reference to the drawings.

FIG. 12 is a block diagram of a camera system having a conventional configuration including a reset circuit, and FIG. 11 is a block diagram of a camera system according to an embodiment incorporating the reset circuit according to the present invention.

The PCIe standard itself enables signal transmission using only four in total, two each for transmission and reception, and as described above, no signal for clock transfer is particularly required. A clock signal and reset signal are provided as band signals and can be used as needed. Figures 11 and 12 show such This is an example in which a camera system is configured using a clock signal and a reset signal.

[0064] As shown in FIG. 12, in the conventional example, the PCIe control unit and conversion unit 111, the camera control unit 112 configured by FPGA, the LVDS (Low Voltage Differential Signaling) driver & receiver 113 are the interface card on the PC side. It is provided as a camera capture card that includes a camera control unit, and is connected to the LVDS driver & receiver 114 provided on the camera side by an original dedicated camera cable.

As shown in FIG. 11, the PC-side interface card 101 is equipped with a PCIe controller (1) that superimposes the reset signal on the PCIe signal and an optical transceiver. ) Connect to the optical transceiver 21 having the conversion unit with the optical communication cable 10a. The signal based on the PCIe standard converted by the OE conversion unit of the optical transceiver 21 is transferred to the PCIe control unit (2) and the conversion unit 12 that extract the reset signal.

[0066] The PCIe control unit (2) and the conversion unit 12 interpret the received packet sent from the PC side, and when the reset signal is detected in the received packet, the reset signal is extracted and generated. At that time, the packet signal is received by regenerating the clock signal based on the signal from the external oscillator (OSC 100 MHz) 105 and the received signal. The received packet signal is passed along with the extracted reset signal to the camera control unit 104 through a local I / F (interface).

[0067] It should be noted that the force S for transferring the reset signal from the PC (or control unit) side extracted together with the received packet signal from the PCIe control unit (2) and the conversion unit 12 to the camera control unit 104, and the camera control. The control unit 104 also has a function of generating a reset signal and resetting the camera control unit 104 itself. The camera control unit 104 is provided with a power-on reset circuit 106 and a reset switch 107 when the power is turned on. As shown in Figs. 4 and 5, first, a reset detection inquiry signal is sent from the PC side to the camera side, and a reset detection confirmation response signal is sent from the camera side to the PC side in response to the reset detection inquiry signal. Of course, it can be configured as follows.

[0068] As described above, in the above-described embodiments, a case where a reset signal (sideband signal) is transmitted as an example of a second signal other than a PCIe standard serial signal in a PCIe standard packet signal is described. However, it can be configured to transmit a plurality of other necessary control signals (sideband signals), and the first electronic device (PC) can transmit the second power. In addition to transmission to the slave device (external device) side, the necessary signal can be superimposed and transmitted from the second electronic device (external device) to the second electronic device (PC) side. It is also possible to make it bidirectional by superimposing both signals.

Claims

The scope of the claims

[1] a first interface unit having at least a PCIe (PCI Express) standard physical layer connected to the first electronic device;

A second interface unit having at least a PCIe standard physical layer connected to the second electronic device;

An optical transmission module comprising a metal cable connector for transferring a signal by an electric signal or an optical transceiver and an optical communication cable connector for transferring a signal by optical communication for connecting the first and second interface units. The first interface unit transmits the second signal other than the PCIe standard serial signal from the first electronic device, and receives the PCI e received from the first electronic device. A signal superimposing means for incorporating the second signal into a packet signal of a standard serial signal and transmitting the packet signal on which the second signal is superimposed to the second interface unit;

The second interface unit interprets the packet signal received from the first interface unit, and when the second signal is detected in the packet signal, extracts the second signal and extracts the second signal. An interface device comprising signal extraction means for transmitting the second signal to the second electronic device.

[2] a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device;

An optical transmission module comprising a metal cable connector for transferring a signal by an electric signal or an optical transceiver and an optical communication cable connector for transferring a signal by optical communication for connecting the first and second interface units. When the first interface unit detects a reset signal from the first electronic device, the first interface unit incorporates the reset signal in a packet signal received from the first electronic device, and A reset signal superimposing means for transmitting the packet signal superimposed with the signal to the second interface unit; The second interface unit reads a packet signal received from the first interface unit, and when a reset signal is detected in the packet signal, the second interface unit outputs a reset signal for resetting the second electronic device. An interface device comprising reset signal generation means for generating.

[3] a first interface unit having at least a physical layer of a PCIe (PCI Express) standard connected to the first electronic device;

An optical transmission module comprising a metal cable connector for transferring a signal by an electric signal or an optical transceiver and an optical communication cable connector for transferring a signal by optical communication for connecting the first and second interface units. The first interface unit includes:

Reset detection inquiry means for transmitting an inquiry signal to the second interface unit and receiving a response signal as to whether or not a reset signal transmitted from the first interface unit can be detected by being superimposed on a packet signal;

When the reset detection inquiry means has a response that the reset signal can be detected from the second interface unit, and the reset signal is detected from the first electronic device, the reset signal is received from the first electronic device. An interface device comprising: reset signal superimposing means for incorporating the reset signal in a packet signal and transmitting the packet signal on which the reset signal is superimposed to the second interface unit.

[4] The second interface unit includes:

When the inquiry signal is received from the first interface unit, a response signal indicating that the reset signal superimposed on the packet signal received from the first interface unit can be detected is sent to the first interface unit. Send

The reset signal generating means for generating a reset signal for resetting the second electronic device when a reset signal is detected in a packet signal received from the first interface unit. 3. The interface device according to 3.

[5] The second interface unit includes a clock signal based on the packet signal and the external reference signal. 4. The interface device according to claim 1, further comprising a clock recovery means for generating and generating the clock.

6. The interface device according to claim 1 or 2, wherein the first and second interface units have a transmission compensation circuit for extending a transmission distance during signal transfer.

7. The first and second interface units according to claim 1, wherein the first and second interface units have a multilink function of performing signal transfer with a single electronic device using a plurality of lanes.

V, an interface device as described in any of the above.

[8] The first or second interface unit further includes a PCIe standard-compliant HUB device that is connected to a plurality of electronic devices and performs signal transfer of a plurality of channels. The interface device described in 1.

[9] A PCIe standard physical layer connected to the control device and an interface unit having at least a PCIe control unit for controlling signal transfer based on the PCIe standard;

At least a main body control unit for performing a signal transfer by mutually converting communication standards between the electronic device main body and the interface unit;

The PCIe control unit reads a packet signal received from the control unit via the interface unit, and generates a reset signal for resetting the electronic device main body when a reset signal is detected in the packet signal. An electronic device comprising a reset signal generating means.