WO2008047832A1

WO2008047832A1 - Semiconductor device, semiconductor device manufacturing method, and inspection method

Info

Publication number: WO2008047832A1
Application number: PCT/JP2007/070247
Authority: WO
Inventors: Shigekazu Komatsu; Mitsuyoshi Miyazono
Original assignee: Tokyo Electron Limited
Priority date: 2006-10-17
Filing date: 2007-10-17
Publication date: 2008-04-24
Also published as: JP2008103421A

Abstract

When inspecting electric characteristic of a power device having a terminal on the front and the rear surface, it is possible to accurately and stably perform the inspection by forming an electric path of a small load. A power device is formed in a device forming region of a semiconductor device. In a region outside the device formation region on the surface of the semiconductor device, a metal wire is arranged to lead to an electrode layer of the rear surface of the power device passing through the interior of the semiconductor. In the inspection of the electric characteristic of the power device, a plurality of probe pins are respectively brought into contact with the power device surface terminal and the metal wire from the surface side of the semiconductor device. By the probe pins, voltage is applied between terminals of the front and the rear surfaces of the power device, thereby inspecting the electric characteristic.

Description

Specification

Semiconductor device, semiconductor device manufacturing method and inspection method

Technical field

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having a structure in consideration of inspection of electrical characteristics of a power device, a manufacturing method thereof, and an inspection method of the semiconductor device.

Background art

[0002] For example, the inspection of electrical characteristics of power devices having terminals on the front and back surfaces, such as power transistors, power MOSFETs (field effect transistors), and IGBTs (insulated gate bipolar transistors), is usually performed using an inspection device. Is called.

[0003] As shown in FIG. 6, the above-described inspection apparatus normally includes a chuck 100 for holding a semiconductor device W on which a power device is formed, and a probe card 102 in which a probe pin 101 is supported above the chuck 100. And a tester 103 electrically connected to the probe card 102. Since the power device has terminals on the upper and lower surfaces of the semiconductor device W, an inspection electrode 104 is formed on the holding surface of the chuck 100, and this inspection electrode 104 is a wiring formed inside the chuck 100. It is electrically connected to the tester 103 through 105! /, (See patent document).

In the above inspection apparatus, the probe pin 101 is brought into contact with the terminal on the upper surface side of the power device, a voltage is applied to the probe pin 101 and the inspection electrode 104 by the tester 103, and a current is passed through the power device. The electrical characteristics of power devices were inspected.

Patent Document 1: JP-A-6-242177

Disclosure of the invention

Problems to be solved by the invention

[0005] However, in the inspection apparatus described above, since an electric circuit is formed from the inspection electrode 104 through the inside of the chuck 100 to the tester 103 at the time of inspection, this electric circuit becomes long and complicated, and has a large resistance and inductance. Occurs. For this reason, during energization during inspection, various loads that impede current flow in the circuit are applied, making it difficult to conduct stable inspection with high accuracy. . In particular, when a large current was passed through the power device as in the reliability test, a larger resistance and inductance were generated in the circuit, and the required inspection could not be performed properly.

[0006] The present invention has been made in view of the force and the point, and it is an object of the present invention to inspect the electrical characteristics of a power device stably with high accuracy using an electric circuit with a small load. Do

Yes

Means for solving the problem

[0007] To achieve the above object, the present invention provides a semiconductor device in which a power device having terminals on the front surface and the back surface is formed, and an electrode serving as a terminal on the back surface side of the power device is formed on the back surface of the semiconductor device. A metal wiring that passes through the inside of the semiconductor device and communicates with the electrode layer is formed on the surface of the semiconductor device and without any terminal on the surface side of the semiconductor device. It is characterized by that.

[0008] According to the present invention, since the metal wiring leading to the electrode layer on the back surface is formed on the front surface of the semiconductor device, inspection is performed from the front surface side of the semiconductor device to the terminal and metal wiring on the front surface side of the power device. The electrical characteristics can be inspected by bringing the probe pins into contact with each other and applying a voltage between the front and back terminals of the power device using these probe pins. In this case, the electric circuit formed during the inspection is simple and short, and no large resistance or inductance is generated! /, So the desired inspection can be performed stably with high accuracy.

[0009] The power device may be formed in each of a plurality of device formation regions of the semiconductor device, and the metal wiring may be formed between adjacent device formation regions. In addition, an insulating layer may be formed around the metal wiring.

[0010] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a power device having terminals on the front surface and the back surface is formed. The first step of forming the surface layer element portion including the second step, the second step of grinding the back side of the semiconductor device, and the electrode layer serving as the terminal on the back side of the first device are formed on the back side of the semiconductor device And having a predetermined depth in a region on the surface of the semiconductor device without the surface layer element portion, before the first step, at the time of the first step, or immediately after the first step. Forming a recess portion of the semiconductor device in the second step; The recess is penetrated by grinding the surface side, and in the third step, when the electrode layer is formed, a metal is embedded in the recess to extend from the electrode layer to the surface of the semiconductor device. Form metal wiring that leads to

[0011] In the third step, the electrode layer may be formed by plating, and a metal wiring may be formed by embedding a metal in the recessed portion by the contact.

[0012] The power device may be formed in each of a plurality of device formation regions of the semiconductor device, and the metal wiring may be formed between adjacent device formation regions. Also

Then, after forming the recess of the predetermined depth, an insulating film may be formed on the inner surface of the recess.

[0013] According to another aspect of the present invention, there is provided a method for inspecting electrical characteristics of the semiconductor device with respect to the power device, from the surface side of the semiconductor device to the terminal and metal wiring on the surface side of the power device. The probe pins are brought into contact, and the electrical characteristics are inspected by applying a voltage between the front and back terminals of the power device using these probe pins.

[0014] A pair of probe pins is brought into contact with a terminal on the surface side of the power device, and a voltage is applied between the probe pins. Utilizes the fritting phenomenon that occurs when electrical connection between the terminals on the surface side is made, a pair of probe pins are brought into contact with the metal wiring, and a voltage is applied between the probe pins. Then, electrical continuity may be achieved between the probe pin and the metal wiring. Further, a plurality of sets of probe pins may be brought into contact with the surface side terminal of the power device and the metal wiring, respectively.

The invention's effect

[0015] According to the present invention, it is possible to form an electric circuit with a small load at the time of inspection and to perform stable inspection with high accuracy.

Brief Description of Drawings

FIG. 1 is a schematic view showing a configuration of a semiconductor device.

FIG. 2 is an explanatory diagram showing a manufacturing process of a semiconductor device. FIG. 3 is a side view schematically showing the configuration of the inspection apparatus.

FIG. 4 is a schematic view showing a state in which a probe pin is brought into contact with a semiconductor device.

FIG. 5 is an explanatory diagram showing a circuit configuration when using the fritting phenomenon.

FIG. 6 is a schematic diagram showing an outline of a configuration of a conventional power device inspection apparatus.

Explanation of symbols

[0017] 1 Semiconductor device

17 Electrode layer

20 Metal wiring

60 Probe pin

P power device

P1 Surface layer element

R device formation region

C1 Surface contact

C2 Back terminal

BEST MODE FOR CARRYING OUT THE INVENTION

[0018] Hereinafter, a preferred embodiment of the present invention will be described. FIG. 1 is a schematic diagram showing the configuration of the semiconductor device 1 according to the present embodiment.

In the plate-like semiconductor device 1, a plurality of divided device forming regions R are formed, and in each device forming region R, a power device P such as an IGBT is formed. For example, in the power device P, a surface layer element portion P1 such as a p-type emitter region 11, an n-type drain region 12, a gate electrode 13, and an emitter electrode 14 is formed on the upper layer side of the n-type base 10, and the n-type base 10 An n-type buffer layer 15, a p-type layer 16, and an electrode layer 17 are formed on the lower layer side. In this example, the gate electrode 13 and the emitter electrode 14 constitute a surface terminal C1 on the surface side of the power device P, and the electrode layer 17 constitutes a back surface terminal C2 on the back side of the power device P.

[0020] Between the adjacent device formation regions R in the semiconductor device 1, that is, in a region without a power device, a metal wiring 20 is formed in the vertical direction from the front surface of the semiconductor device 1 to the electrode layer 17 on the back surface. Metal wiring 20 is formed for each power device P . For example, an insulating layer 21 is formed around the metal wiring 20.

The semiconductor device 1 is manufactured by, for example, the following process. First, as shown in FIG. 2 (a), the surface element portion P1 is formed on the surface side of the device formation region R of the semiconductor device 1. The surface layer element portion pit is formed using, for example, a photolithography technique. A wiring hole 30 to be a recessed portion with a predetermined depth is formed from the surface side of the semiconductor device 1 before the formation process of the surface element part P1, during the formation process of the surface element part P1, or immediately after the formation of the surface element part P1. Is done. This wiring hole 30 is formed outside the device formation region R by, for example, etching. Next, an insulating film 21 such as an oxide film or a nitride film is formed on the inner surface of the wiring hole 30 by, for example, a CVD method.

Thereafter, as shown in FIG. 2B, for example, the back surface side of the semiconductor device 1 is ground, and the semiconductor device 1 is shaved to a predetermined thickness. At this time, the wiring hole 30 penetrates. After that, an n-type buffer layer 15 and a p-type layer 16 are formed in this order on the back side of the semiconductor device 1, and then an electrode layer 17 is formed as shown in Fig. 2 (c), for example, by a plating technique. At this time, a metal is buried in the wiring hole 30 by, for example, a plating technique, and a metal wiring 20 that leads from the electrode layer 17 to the surface of the semiconductor device 1 is formed. In this way, the semiconductor device 1 having the power device P and the metal wiring 20 is manufactured.

Next, an inspection apparatus that inspects the electrical characteristics of the power device P formed in the semiconductor device 1 will be described. FIG. 3 is an explanatory diagram showing an outline of the configuration of the inspection device 50.

The inspection device 50 includes, for example, a probe card 51 and a chuck that holds the semiconductor device 1 by suction.

52, a moving mechanism 53 for moving the chuck 52, a tester 54, and the like.

The probe card 51 includes, for example, a contactor 61 that supports a plurality of probe pins 60 on the lower surface, and a printed wiring board 62 that is attached to the upper surface side of the contactor 61. The probe pin 60 is electrically connected to the printed wiring board 62 through the main body of the contactor 61. A tester 54 is electrically connected to the probe card 51, and an electrical signal for inspecting electrical characteristics can be transmitted and received from the tester 54 to each probe pin 60 via the probe card 51.

[0026] The chuck 52 is formed in a substantially disc shape having a horizontal upper surface. Upper surface of chuck 52 Is provided with a suction port 52a for adsorbing the semiconductor device 1. For example, a suction pipe 52b that passes through the inside of the chuck 52 and communicates with an external negative pressure generator 63 is connected to the suction port 52a.

[0027] The moving mechanism 53 includes, for example, an elevating drive unit 70 such as a cylinder for elevating the chuck 52, and an elevating drive unit 70 for moving in two directions orthogonal to the horizontal X direction and the Y direction. The 71 is equipped. As a result, the semiconductor device 1 held by the chuck 52 is moved three-dimensionally, and the specific probe pin 60 located above is moved to a predetermined position on the surface of the semiconductor device 1 with a force.

[0028] Next, an inspection process of the electrical characteristics of the power device P performed by the inspection apparatus 50 configured as described above will be described.

First, the semiconductor device 1 is sucked and held on the chuck 52 as shown in FIG. Subsequently, the chuck 52 is moved in the X and Y directions by the moving mechanism 53, and the position of the semiconductor device 1 is adjusted. Thereafter, the chuck 52 is raised, and a plurality of probe pins 60 are brought into contact with the surface of the semiconductor device 1 as shown in FIG. At this time, for example, the probe pin 60a contacts the surface terminal C1 of each power device P. The probe pin 60b is in contact with the metal wiring 20 in the region where the power device P is not formed.

[0030] Then, for example, a high voltage is applied between the probe pin 60a and the probe pin 60b by the tester 54, and the current is applied to the probe pin 60b, the metal wiring 20, the back surface terminal C2, the surface layer element portion P1, and the surface terminal C1. And the probe pin 60a in this order, and the electrical characteristics of the power device P, such as a large current switching test, are inspected.

When the inspection of the electrical characteristics is completed, the chuck 52 is lowered by the drive mechanism 53, and each probe pin 60 is separated from the semiconductor device 1. Thereafter, the semiconductor device 1 is removed from the chuck 52, and the series of inspection processes is completed.

[0032] According to the above embodiment, since the metal wiring 20 leading to the electrode layer 17 on the back surface is formed on the front surface of the semiconductor device 1, the probe pin 60 can be connected to the surface terminal C1 of the power device P and the metal with the upward force. The electrical characteristics can be inspected by contacting the wiring 20 and applying a voltage between both terminals CI and C2 of the power device P. In this case, the electric circuit from the back terminal C2 of the power device P to the probe pin 60 is short, and the tester 54 and the power device P Since an electric circuit with a small load can be formed between the two, a highly accurate and stable inspection can be performed. In addition, since an electrode that is electrically connected to the back terminal C2 is formed on the surface of the semiconductor device 1 itself, it is necessary to form a special wiring inside the chuck for electrical connection with the back terminal C2. In addition, the configuration of the inspection device 50 can be simplified.

[0033] Since the metal wiring 20 is formed between the adjacent device formation regions R, the power device P itself is not affected!

In the manufacturing process of the semiconductor device 1, the wiring hole 30 is formed when the surface element portion P 1 of the power device P is formed, and then the wiring hole 30 is ground when the back surface of the semiconductor device 1 is ground. When the electrode layer 17 was formed, metal wiring 20 was formed by embedding metal in the wiring holes 30. In this way, the metal wiring 20 can be easily formed in a small number of steps in the manufacturing process of the semiconductor device 1.

[0035] The electrical characteristic inspection performed using the probe pin 60 described in the above embodiment may be performed using the fritting phenomenon. The fritting phenomenon is the application of a potential gradient of 10 ⁵ to 10 ⁶ V / cm to the metal surface on which the oxide film is formed, causing the oxide film to break down and current to flow through the metal surface. A phenomenon.

In such a case, for example, the printed circuit board 12 causes a fringing phenomenon, as shown in FIG. 5, with a test circuit 80 that transmits / receives an electrical signal for inspecting electrical characteristics to / from the probe pin 60. For this purpose, a fringing circuit 81 for applying a voltage to a pair of probe pins 60 and a switching circuit 82 for switching the connection of the test circuit 80 and the fritting circuit 81 to the probe pin 60 are formed! .

[0037] When the power device P is inspected, for example, a plurality of pairs of probe pins 60a are brought into contact with the surface terminal C1 of the power device P of the semiconductor device 1 so that the outer side of the power device P Multiple sets of two probe pins 60b are in contact with the metal wiring 20. A predetermined voltage is applied between each pair of probe pins 60a (60b) by the fritting circuit 81, and the potential gradient between the pair of probe pins 60a (60b) is increased. . This causes dielectric breakdown in the surface oxide film at the surface terminal C1 and the metal wiring 20 of the power device P, respectively, and between the surface terminal C1 and the probe pin 60a and between the metal wiring 20 and the probe pin 60b. Electrical continuity is achieved. After that, Switching from the fritting circuit 81 to the test circuit 80 is performed by the pinching circuit 82. For example, a voltage is generated between the surface terminal C1 of the power device P and the metal wiring 20 by both probe pins 60a and 60b. The electrical characteristics of the power device P, which are the same as those in the above-described embodiment, are inspected. When testing electrical characteristics at a large current, the test may be performed using the number of probe pins corresponding to the current value.

[0038] In such a case, the electrical connection between the probe pin 60 and the surface terminal C or the metal wiring 20 is achieved by utilizing the fritting phenomenon, so that the probe pin 60 is strongly pressed against the surface terminal C1 or the metal wiring 20 This is unnecessary, and damage to the semiconductor device 1 due to the pressing can be reduced. As a result, for example, damage to the semiconductor device 1 can be prevented.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to these examples. It will be apparent to those skilled in the art that various changes or modifications can be made within the scope of the idea described in the claims. It is understood that it belongs to. For example, the power device P described in the above embodiment is an example of an IGBT, and the present invention can be applied to power devices having other configurations. For example, the present invention can be applied to other power devices such as a power transistor and a power MOSFET as long as it is a vertical power device having terminals on the front and back surfaces.

Industrial applicability

The present invention is useful when inspecting the electrical characteristics of a power device, forming an electric circuit with less load and performing a stable inspection with high accuracy.

Claims

The scope of the claims

[1] A semiconductor device in which a power device having terminals on the front and back surfaces is formed, and an electrode layer serving as a terminal on the back side of the power device is formed on the back surface of the semiconductor device.

In the region of the surface of the semiconductor device where there is no terminal on the surface side of the power device, a metal wiring that passes through the inside of the semiconductor device and communicates with the electrode layer is formed.

[2] In the semiconductor device according to claim 1,

The power device is formed in each of a plurality of device formation regions of a semiconductor device,

The metal wiring is formed between adjacent device formation regions.

[3] In the semiconductor device according to claim 1,

An insulating layer is formed around the metal wiring.

[4] A method of manufacturing a semiconductor device in which a power device having terminals on the front and back surfaces is formed.

A first step of forming a surface element portion including a terminal on the surface side of the power device on the surface side of the semiconductor device;

A second step of grinding the back side of the semiconductor device;

A third step of forming an electrode layer on the back surface of the semiconductor device, which serves as a terminal on the back surface side of the power device,

Before the first step, at the time of the first step, or immediately after the first step, a recess portion having a predetermined depth is formed in a region of the surface of the semiconductor device that does not have the surface layer element portion. In step 2, by grinding the back side of the semiconductor device, the recess is penetrated,

In the third step, when the electrode layer is formed, a metal wiring is formed by burying a metal in the recessed portion and extending from the electrode layer to the surface of the semiconductor device.

[5] In the method of manufacturing a semiconductor device according to claim 4,

In the third step, the electrode layer is formed by plating, and metal is embedded in the recessed portion by the plating to form a metal wiring.

[6] In the method of manufacturing a semiconductor device according to claim 4,

The metal wiring is formed between adjacent device formation regions.

[7] In the method of manufacturing a semiconductor device according to claim 4,

After forming the recess of the predetermined depth, an insulating film is formed on the inner surface of the recess.

[8] A method for inspecting the electrical characteristics of a semiconductor device in which a power device having terminals on the front and back surfaces is formed.

An electrode layer serving as a terminal on the back side of the power device is formed on the back side of the semiconductor device.

In the region of the surface of the semiconductor device where there is no terminal on the surface side of the power device, a metal wiring that passes through the inside of the semiconductor device and communicates with the electrode layer is formed, and further from the surface side of the semiconductor device. The probe pins are brought into contact with the terminals on the front side of the power device and the metal wiring, and the electrical characteristics are inspected by applying a voltage between the front and back terminals of the power device with these probe pins.

[9] In the inspection method according to claim 8,

The probe pin and the surface-side terminal are utilized by utilizing a fritting phenomenon caused by bringing a pair of probe pins into contact with the surface-side terminal of the power device and applying a voltage between the probe pins. To establish electrical continuity between

An electrical connection between the probe pin and the metal wiring is made by utilizing a fritting phenomenon caused by bringing a pair of probe pins into contact with the metal wiring and applying a voltage between the probe pins. Ensuring continuity.

[10] In the inspection method according to claim 9,

Plural pairs of probe pins are brought into contact with the terminal on the surface side of the power device and the metal wiring.