WO2008047495A1

WO2008047495A1 - Display device

Info

Publication number: WO2008047495A1
Application number: PCT/JP2007/061171
Authority: WO
Inventors: Takayuki Mizunaga; Hideki Morii
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2006-10-18
Filing date: 2007-06-01
Publication date: 2008-04-24

Abstract

Provided is a display device, which is enabled to correct a display failure due to a break by a simple constitution. A display control circuit (200) comprises a data correcting unit (22), an address register (27) for holding address information to specify the broken portion, and a data correcting LUT (28) for storing the corresponding relations of data values before and after corrected. When the break occurs, that broken line is connected at its two end portions with a correcting line, so that the address register (27) is given the address information of the broken portion. At the action time of the display device, the data correcting unit (22) specifies, on the basis of the input data sending timing and the address information, such data (i.e., the data of a corrected pixel forming unit) of the input data as has to be corrected. If the input data is the data of the corrected pixel forming unit, the data correcting unit (22) acquires, on the basis of the data correcting LUT (28), the data value of the output data corresponding to the data value of the input data.

Description

Specification

Display device

Technical field

The present invention relates to a display device, and more particularly, to data correction when a disconnection occurs in such a display device.

Background art

Conventionally, a manufacturing process of a display device such as a liquid crystal display device has been provided with an inspection process for inspecting the presence or absence of defects in the panel. In the inspection process, for example, a display defect called a point defect or a display defect called a line defect is inspected by lighting the panel. One of the causes of line defects is the disconnection of the source bus line (video signal line). This is because if a part of the source bus line is disconnected, the video signal is not normally transmitted to the part beyond the disconnected part.

[0003] By the way, if all the panels in which display defects are detected are discarded, the manufacturing yield is remarkably reduced. Therefore, when a display defect is detected, the defective part is corrected if possible. Various techniques are known for correcting the display defect due to the disconnection of the source bus line described above.

FIG. 14 is a diagram (a block diagram of a liquid crystal display device) for explaining a conventional technique for correcting a display defect due to disconnection of a source bus line (hereinafter referred to as “first conventional example”). The liquid crystal display device includes a display control circuit 920, a source driver substrate 930, a plurality of source drivers 931, a gate driver substrate 940, a plurality of gate drivers 941, and a display panel 950. Further, a display area indicated by reference numeral 951 in the display panel 950 includes a plurality of source nos lines (not shown) connected to the source driver 931 and a plurality of gate bus lines (not shown) connected to the gate driver 941. Are provided). Further, as shown in FIG. 14, wiring for correcting display defects due to disconnection of the source bus line (hereinafter referred to as “correction line”) DL is provided outside the display area 951 in the display panel 950. Is provided.

FIG. 15 is a block diagram showing a configuration of display control circuit 920 in the first conventional example. is there. Based on the data control signal Sd given from the timing control unit 923, the data processing unit 921 receives the image data (three-color input data RIN, GIN, BIN) DAT as the data signal (data signal ( 3-color output data ROUT, GOUT, B OUT) Output as DA. In the first conventional example, even if a disconnection occurs, the data processing unit 921 does not correct the data value. In the following, it is assumed that a break has occurred at a location indicated by reference symbol PD (hereinafter referred to as “disconnection location”) of a source bus line indicated by reference symbol SLd (hereinafter referred to as “disconnection location” t). explain.

[0006] When disconnection occurs, disconnection line SLd and correction line DL are connected by a laser or the like at a location indicated by reference symbol P1 in FIG. 14 (hereinafter referred to as “P1 portion”). Further, the disconnection line SLd and the correction line DL are also connected at a location indicated by reference symbol P2 (hereinafter referred to as “P2 section”). As a result, the video signal is transmitted to the P2 part by the correction line DL. As a result, the video signal is transmitted from the P1 part to the disconnection point PD between the PI and PD of the disconnection line SLd, and the video signal is transmitted from the P2 part to the disconnection point PD between the P2 and PD of the disconnection line SLd. As described above, the video signal is also transmitted to the part beyond the disconnection point.

[0007] However, in the case of the above-described configuration, the luminance between P2 and PD (in the case of a normally black type) may be lower than that between P1 and PD. In FIG. 16, the waveform of the video signal between PI and PD is indicated by reference symbol VI, and the waveform of the video signal between P2 and PD is indicated by reference symbol V2. As shown in Fig. 16, the rounding of waveform V2 is larger than that of waveform VI. This is because the video signal supplied between P2 and PD is transmitted through the correction line DL, and thus has the influence of the wiring length and wiring capacity of the correction line DL.

Therefore, as shown in FIG. 17, by using unused terminals of the source driver 931 as terminals for the correction line DL (hereinafter referred to as “correction terminals”) TDL (correction line DL (2) A technology to shorten the wiring length (hereinafter referred to as “second conventional example”) has been proposed. In this configuration, the display control circuit 920 is provided with an address register 927 that stores information (hereinafter referred to as “address information”) indicating the address of the disconnection location PD.

FIG. 18 is a block diagram showing a configuration of a display control circuit 920 in the second conventional example.

The display control circuit 920 includes a data processor 921, a data converter 922, and a timing controller. A register unit 923, a counter unit 924, a comparison unit 925, a ROM interface unit 926, and an address register 927. The ROM interface unit 926 is connected to an external ROM 929.

When disconnection occurs, address information of the disconnection location PD is written in ROM 929. The address information written in the ROM 929 is written in the address register 927 by the ROM interface unit 926. In the counter unit 924, in accordance with the transmission of data of external power, the number of columns and rows of (input data) is counted. Then, the value counted by the counter unit 924 and held in the address register 927 is compared with the value (address value) by the comparison unit 925, and the input data is disconnected at the disconnection point PD of the disconnection line SLd. The data correction flag Dflg is turned on only when the data is ahead of the data.

[0011] If the data correction flag Dflg is on, the data conversion unit 922 performs data conversion so that the correction terminal TDL force in the source driver 931 also outputs data to the correction line DL. Is done. On the other hand, if the data correction flag Dflg is off, the data conversion unit 922 does not perform data conversion.

As described above, in the display control circuit 920, the video signal to be applied between P2 and PD is transferred from the correction terminal TDL to the correction line DL based on the address information stored in the address register 927. A data signal DA and a source driver control signal Ss are generated so as to be output. With this configuration, the length of the correction line DL is shorter than the configuration of the first conventional example shown in FIG. 14, so that the rounding of the video signal applied between P2 and PD is reduced, and the decrease in luminance is suppressed. The In order to further suppress the rounding of the video signal, a configuration is proposed in which a buffer amplifier 961 for amplifying the video signal is provided in the correction line DL as shown in FIG.

Furthermore, as shown in FIG. 20, the source driver 931 includes an input / output terminal for the correction line DL, and the buffer amplifier 932 is used as an output terminal (hereinafter referred to as “third conventional example”). .) Has also been proposed. This configuration also reduces the rounding of the video signal and suppresses the decrease in luminance.

Patent Document 1: Japanese Unexamined Patent Publication No. 2000-321599

Patent Document 2: Japanese Unexamined Patent Publication No. 2005-352499 Disclosure of the invention

Problems to be solved by the invention

However, in the case of the second conventional example, since the video signal given between P2 and PD is output from the correction terminal TDL, the processing in the display control circuit 920 becomes complicated. For example, the order of data transmitted from the outside to the display control circuit 920 and the order of data output from the display control circuit 920 need to be interchanged.

[0015] In the case of the third conventional example, since the wiring length of the correction line DL differs depending on the position of the disconnection point PD, the capability of the buffer amplifier 932 must be determined for each source driver 931. . This is because the display quality can be degraded if the capacity of the buffer amplifier 932 is too large or too small.

Therefore, an object of the present invention is to provide a display device that can correct a display defect due to disconnection with a simple configuration.

Means for solving the problem

[0017] A first aspect of the present invention includes a display unit that displays an image in a predetermined display area, a plurality of video signal lines for transmitting a plurality of video signals representing the image, and a display area within the display area. A plurality of scanning signal lines intersecting with the plurality of video signal lines, and a plurality of pixel forming portions arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively. A display device for displaying the image based on input pixel data that is input data for each pixel forming unit,

Wiring provided outside the display area, and when one of the plurality of video signal lines is disconnected, it is electrically connected to substantially both ends of the video signal line where the disconnection occurs. Corrective wiring for

An address holding unit for holding address information for specifying a pixel forming unit corresponding to the position where the disconnection has occurred;

An output pixel data generation unit that generates output pixel data, which is output data for each pixel forming unit, based on the input pixel data;

A video signal output unit configured to supply the plurality of video signals to the plurality of video signal lines based on the output pixel data; Have

The output pixel data generation unit identifies a correction pixel formation unit, which is a pixel formation unit to which a video signal transmitted through the correction wiring is supplied, based on the address information, and the correction pixel formation unit Is characterized by correcting the data value of the input pixel data to generate the output pixel data.

[0018] A second aspect of the present invention is the first aspect of the present invention,

The correction of the data value of the input pixel data for the correction pixel formation unit is performed by digital processing.

[0019] A third aspect of the present invention is the second aspect of the present invention,

The output pixel data generation unit generates the output pixel data by adding a predetermined value to the data value of the input pixel data for the correction pixel formation unit.

[0020] A fourth aspect of the present invention is the second aspect of the present invention,

A data correction table for storing a correspondence relationship between the data value of the input pixel data and the data value of the output pixel data;

The output pixel data generation unit corrects a data value of the input pixel data based on the data correction table and generates the output pixel data for the correction pixel formation unit.

[0021] A fifth aspect of the present invention is the fourth aspect of the present invention,

The data correction table stores a correspondence relationship between the data value of the input pixel data and the data value of the output pixel data for each gradation of the input pixel data.

[0022] A sixth aspect of the present invention is the fourth aspect of the present invention,

The data correction table stores a correspondence relationship between the data value of the input pixel data and the data value of the output pixel data for each of a plurality of gradations of the input pixel data. .

[0023] A seventh aspect of the present invention is the fourth aspect of the present invention,

The data correction tape for each display block obtained by dividing the display area into a plurality of areas It is characterized by providing a ru.

[0024] An eighth aspect of the present invention is the first aspect of the present invention,

The address information includes information for specifying video signal lines included in the plurality of video signal lines and information for specifying scanning signal lines included in the plurality of scanning signal lines.

[0025] According to a ninth aspect of the present invention, in the first aspect of the present invention,

The video signal output unit includes a buffer for amplifying the video signal transmitted through the correction wiring.

[0026] A tenth aspect of the present invention is the first aspect of the present invention,

The correction wiring is provided with a notch for amplifying the video signal transmitted through the correction wiring.

[0027] An eleventh aspect of the present invention is the first aspect of the present invention,

The display device is a liquid crystal display device.

The invention's effect

According to the first aspect of the present invention, when a disconnection occurs in the video signal line, both ends of the video signal line in which the disconnection occurs are connected to the correction wiring. For this reason, regardless of the presence or absence of disconnection, the data (video signal) for each pixel forming portion is output from a predetermined output terminal of the video signal output portion. Therefore, complicated processing such as changing the order of data when disconnection occurs is not necessary. Further, the output pixel data generation unit identifies a pixel formation unit (correction pixel formation unit) to which the video signal is transmitted through the correction wiring based on the address information held in the address holding unit, and forms the correction pixel formation. The data value of the part is corrected. For this reason, only by storing the address information of the disconnected video signal line in the address holding unit, the data value of the correction pixel forming unit is corrected, and the deterioration of display quality due to the disconnection is suppressed.

[0029] According to the second aspect of the present invention, the correction of the data value of the correction pixel forming unit is performed by digital processing. For this reason, the correction amount of the data value can be easily set. Thereby, when disconnection occurs, it is possible to easily suppress deterioration of display quality.

[0030] According to the third aspect of the present invention, the data value of the correction pixel forming unit is calculated by a predetermined addition process. For this reason, when a disconnection occurs, a predetermined process is performed. Thus, it is not necessary to perform processing such as changing the correction amount according to the disconnection location. As a result, regardless of the disconnection location in the display unit, the correction amount is satisfactory, and in the case where the correction value is correct, the data value of the correction pixel forming unit can be corrected with a simple configuration.

[0031] According to the fourth aspect of the present invention, there is provided a data correction table in which data values before and after correction are associated. Therefore, a suitable correction amount can be set in advance according to the data value (gradation value) of the input pixel data. As a result, it is possible to suppress deterioration in display quality regardless of the data value (gradation value) of the input pixel data.

[0032] According to the fifth aspect of the present invention, the data correction table stores data values before and after correction for each gradation of the input pixel data. Therefore, a suitable correction amount can be set for each gradation.

[0033] According to the sixth aspect of the present invention, the data correction table stores data values before and after correction for each of the multiple gradations of the input pixel data. As a result, the amount of memory required for the data correction table can be reduced.

[0034] According to the seventh aspect of the present invention, a data correction table is provided for each display block obtained by dividing the display area. For this reason, the correction of data is more preferably performed according to the position of the disconnection location or the position of the correction pixel forming portion. Thereby, the display quality when the disconnection occurs can be further improved.

[0035] According to the eighth aspect of the present invention, the address information includes information for specifying a video signal line and information for specifying a scanning signal line. For this reason, the information on the disconnection location can be easily given to the address holding cage.

[0036] According to the ninth aspect of the present invention, the rounding of the waveform of the video signal supplied to the correction pixel forming unit is suppressed by the noffer.

[0037] According to the tenth aspect of the present invention, as in the ninth aspect of the present invention, the waveform rounding of the video signal supplied to the correction pixel forming unit is suppressed.

[0038] According to the eleventh aspect of the present invention, a liquid crystal display device capable of suppressing a reduction in display quality due to disconnection with a simple configuration is realized.

Brief Description of Drawings

[0039] [FIG. 1] A display control circuit of an active matrix liquid crystal display device according to an embodiment of the present invention. It is a block diagram which shows the structure of a path.

2] A block diagram showing the overall configuration of the active matrix liquid crystal display device according to the embodiment.

FIG. 3 is a diagram showing a configuration of a data correction LUT in the embodiment.

FIG. 4 is a diagram for explaining processing when disconnection occurs in the embodiment.

FIG. 5 is a diagram for explaining correction of data values in the embodiment.

FIG. 6 is a signal waveform diagram for describing effects in the embodiment. [7] FIG. 7 is a diagram showing a configuration of a data correction LUT in a first modification of the embodiment.

[8] FIG. 8 is a diagram for explaining division of the display area in the second modification of the embodiment.

FIG. 9 is a diagram for explaining correction of a data value in the second modified example.

FIG. 10 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a fourth modification of the embodiment.

[11] FIG. 11 is a signal waveform diagram for explaining correction of data values in the fourth modified example.

FIG. 12 is a diagram for explaining scan directions in the horizontal and vertical directions in the fifth modification of the embodiment.

FIG. 13 is a block diagram for explaining the arrangement of source drivers in the sixth modification of the embodiment.

FIG. 14 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first conventional example.

FIG. 15 is a block diagram showing a configuration of a display control circuit in the first conventional example. 16] A signal waveform diagram for explaining the rounding of the waveform of the video signal in the first conventional example.

FIG. 17 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a second conventional example. FIG.

FIG. 18 is a block diagram showing a configuration of a display control circuit in the second conventional example.

FIG. 19 is a block diagram showing a configuration in which a noffer amplifier is provided in a correction line in the second conventional example.

FIG. 20 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a third conventional example. .

Explanation of symbols

5 ... Pixel formation part

21 · ·-Data processing section

-Data correction part

23 ·· 'Timing control section

24

25 ·· -Comparison

26 ROM interface section

27

28 ·· 'Data correction LUT

200 ··· Display control circuit

210 •• ROM

300 '··· Source driver board

310 '"source driver

400- "Gate Driver Board

410 -...

500 ···· Display No Nere

510 ··· Display area

CntH to H count value

CntV to V count value

DA: Data signal

Dflg: Data correction flag DL ... Correction line

RegH '.'H register value

RegV to V register value

Ss: Source driver control signal

Sg: Gate driver control signal

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0042] <1. Overall configuration and operation of liquid crystal display device>

FIG. 2 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device includes a display control circuit 200, a source driver substrate 300, a plurality of source drivers 310 as video signal output units, a gate driver substrate 400, a plurality of gate drivers 410, And a display panel 500. In addition, one or more correction lines DL are provided outside the display area 510 in the display panel 500.

[0043] The display panel 500 includes a plurality of (n) source bus lines (video signal lines) SLl to SLn connected to the source driver 310 and a plurality (m) of source bus lines (m) connected to the gate driver 410. Gate bus lines (scanning signal lines) GLl to GLm and a plurality (n X m pieces) provided corresponding to the intersections of the plurality of source bus lines SL1 to SLn and the plurality of gate bus lines GLl to GLm ) Includes a pixel forming portion 5.

Each pixel forming unit 5 includes a TFT 6 that is a switching element in which a gate terminal is connected to a gate bus line passing through a corresponding intersection and a source terminal is connected to a source bus line passing through the intersection. The pixel electrode connected to the drain terminal of the TFT 6 and a liquid crystal layer provided in common to the plurality of pixel forming portions 5 and sandwiched between the pixel electrode and the common electrode Ec. A pixel capacitance Cp is formed by the capacitance formed by the pixel electrode and the common electrode Ec. Each pixel forming unit 5 corresponds to one pixel in the display image, and gradation and luminance are determined for each pixel.

The display control circuit 200 receives the image data DAT and the synchronization signal TS sent from the outside, and operates the data signal DA representing the gradation of the image to be displayed and the operation of the source driver 310. A source driver control signal Ss that also has a plurality of signal forces for control and a gate driver control signal Sg that also has a plurality of signal forces for controlling the operation of the gate driver 410 are output.

[0046] The source driver substrate 300 fixes a plurality of source drivers 310 on the substrate. In addition, the source driver substrate 300 supplies the data signal DA and the source driver control signal Ss sent from the display control circuit 200 to the source driver 310. The source driver 310 receives the data signal DA and the source driver control signal Ss, and applies a video signal for displaying an image in the display area 510 in the display panel 500 to each of the source bus lines SL1 to SLn.

[0047] The gate driver substrate 400 fixes a plurality of gate drivers 410 on the substrate. Further, the gate driver substrate 400 provides the gate driver 410 with the gate driver control signal Sg sent from the display control circuit 200. The gate driver 410 applies an active scanning signal to the gate bus lines GLl to GLm based on the gate driver control signal Sg.

[0048] As described above, an image signal is applied to each source nose line SLl to SLn, and a scanning signal is applied to each gate bus line GLl to GLm. Is displayed. Note that the liquid crystal display device according to this embodiment will be described as being of a normally black type.

[0049] <2. Configuration and operation of display control circuit>

FIG. 1 is a block diagram showing the configuration of the display control circuit 200 in the present embodiment. The display control circuit 200 includes a data processing unit 21, a data correction unit 22, a timing control unit 23, a counter unit 24, a comparison unit 25, a ROM interface unit 26, an address register 27, and a data correction LUT 28. The ROM interface unit 26 is connected to an external ROM 210!

[0050] The timing control unit 23 is based on the synchronization signal TS to which an external force is also sent, and the source driver control signal Ss, the gate driver control signal Sg, and the data control signal Sd for controlling the operation of the data processing unit 21. The counter control signal Sc for controlling the operation of the counter unit 24 is output. The data processing unit 21 is a three-color (RGB) input data sent from the outside. Data (input pixel data) Receives image data DAT consisting of RIN, GIN, and BIN, and outputs intermediate data scale, G, and B based on data control signal Sd output from timing control unit 23 .

[0051] Based on the counter control signal Sc output from the timing control unit 23, the counter unit 24 has a value (hereinafter referred to as "H count value" t) indicating which column (input data) is data. ) Count CntH and the value (hereinafter referred to as “V count value”) indicating the number of rows of data (the gate bus line of which row is driven).

The ROM 210 stores the address information of the disconnection location and the data correction value for correcting the data value of the pixel formation portion in the portion ahead of the disconnection location (source bus line). In the following, the pixel formation portion in the portion ahead of the disconnection point (source bus line) is referred to as a “correction pixel formation portion”.

The ROM interface unit 26 reads the address information and the data correction value stored in the ROM 210, writes the address information to the address register 27, and writes the data correction value to the data correction LUT 28.

[0054] The address register 27 holds address information of a broken portion during operation of the liquid crystal display device. The data correction LUT 28 holds data correction values during operation of the liquid crystal display device. Note that the address information held in the address register 27 is a value indicating what column source bus line the disconnection part corresponds to (hereinafter referred to as “H register value”). A value indicating whether it corresponds to the gate bus line (hereinafter referred to as “V register value”) RegV and power. A detailed description of the data correction LUT 28 will be given later.

[0055] Based on the H count value CntH and V count value C ntV counted by the counter unit 24 and the address register 28, the comparison unit 25 is based on the H register value RegH and the V register value RegV. The data correction flag Dflg is output. Specifically, the H count value CntH and the H register value RegH are compared, and the V count value CntV and the V register value RegV are compared. When the H count value CntH and the H register value RegH are different values, the data correction flag Dflg is turned off. On the other hand, if the H count value CntH is equal to the H register value RegH! /, The data is compensated if the V count value CntV is less than or equal to the V register value RegV. The positive flag Dflg is turned off. If the V power value CntV is larger than the V register value Reg V, the data correction flag Dflg is turned on. As a result, the data correction flag Dflg that is turned on is output from the comparison unit 25 only when the input data is data of the correction pixel forming unit.

[0056] The data correction unit 22 receives the intermediate data R, G, and B output from the data processing unit 21, and determines the V based on the ON / OFF state of the data correction flag Dflg output from the comparison unit 25. The three-color output data (output pixel data) to be supplied to the source driver 310 is output as a data signal DA having ROUT, GOUT, and BOUT power. Here, when the data correction flag Dflg is off, the data correction unit 22 outputs the intermediate data as the data signal DA without correcting the intermediate data. On the other hand, when the data correction flag Dflg is on, the data correction unit 22 refers to the data correction LUT 28 and corrects the intermediate data, and then outputs the corrected data as the data signal DA. A specific example of correction in the data correction unit 22 will be described later.

In the present embodiment, an output pixel data generation unit is realized by the data processing unit 21, the data correction unit 22, the timing control unit 23, the counter unit 24, and the comparison unit 25. Further, an address holding unit is realized by the address register 27, and a data correction table is realized by the data correction LUT.

[0058] <3. LUT for data correction>

Next, in the present embodiment, a data correction LUT 28 used for correcting a data value will be described. FIG. 3 is a diagram showing the configuration of the data correction LUT 28 in the present embodiment. In this data correction LUT 28, the data value of the input data and the data value of the output data (corrected data) are stored in association with each gradation of the input data. For example, if the data value of the input data is “1”, the data value of the output data is “1”, and if the data value of the input data is “127”, the data value of the output data is “128”. If the data value of the data is “253”, the data value of the output data is “255”.

Note that in the data correction LUT 28, the data value of the output data may be determined in consideration of the position of the broken line, the wiring length in the display panel 500, the wiring capacity, and the like. Also, In the case where a plurality of correction lines DL are provided in the display panel 500, a configuration in which a plurality of data correction LUTs 28 are provided so as to correspond to each of a plurality of disconnection points may be employed.

[0060] <4. Processing when disconnection occurs>

Next, processing when disconnection occurs will be described with reference to FIGS. 1, 4, and 5. FIG. If a disconnection (disconnection point PD) as shown in FIG. 4 is found in the inspection process of this liquid crystal display device, the disconnection line SLd and the correction line DL are connected by a laser or the like at the P1 part. Furthermore, the disconnection line SLd and the correction line DL are also connected in the P2 part. In this way, the disconnection line SLd and the correction line DL are connected at almost both ends of the disconnection line SLd. In addition, the address information and the data correction value of the disconnection location are written into the ROM 210.

When this liquid crystal display device operates, the address information and the data correction value stored in the ROM 210 are written into the address register 27 and the data correction LUT 28 by the ROM interface unit 26, respectively. During the operation of the liquid crystal display device, the counter unit 24 counts the H count value CntH and the V count value CntV. Specifically, every time image data DAT for one pixel is sent, the H count value CntH increases by one. In addition, the V count value CntV increases by 1 each time the driving line among the gate bus lines GLl to GLm changes (changes to the next line). When reception of the image data DAT for one frame is completed, the H count value CntH and V count value CntV are cleared.

Here, description will be made assuming that the display panel 500 of this liquid crystal display device is a VGA type (640 × 480), and the coordinates of the disconnection point PD are (500, 180). At this time, the comparison unit 25 compares the value “500” of the H register value RegH held in the address register 27 with the H count value CntH output from the counter unit 24 and holds it in the address register 27. The V register value RegV value “180” is compared with the V count value CntV output from the counter unit 24.

[0063] When the H count value CntH is other than "500", the data correction flag Dflg is turned off regardless of the value of the V count value CntV. On the other hand, when the H count value CntH is “500”, the data correction flag Dflg is off if the V count value CntV is “180” or less. If the V count value CntV is greater than “180”, the data correction flag Dflg is turned on. In this way, the data correction flag Dflg is turned on only when the input data is data of the correction pixel forming unit.

The data correction unit 22 operates as follows according to the on / off state of the data correction flag Dflg described above. When the data correction flag Dflg is off, the data correction unit 22 does not correct the intermediate data (R, G, B) output from the data processing unit 21 without correcting the intermediate data as the data signal DA (ROUT, (GOUT, BOUT). On the other hand, when the data correction flag Dflg is on, the data correction unit 22 refers to the data correction LUT 28 and acquires the data value of the output data associated with the data value of the input data.

For example, it is assumed that the data value (gradation value) of the input data is “128” in the entire range of the display area 510. In this case, as shown in FIG. 5, for the data between P1 and PD, “128”, which is the data value of the input data, is directly output from the data correction unit 22 as output data. On the other hand, the data between P2 and PD is associated with the data value “128” of the input data in the data correction LUT 28 and output from the data correction unit 22 as the output data value “130”. Is done.

[0066] <5.Effect>

FIG. 6 is a signal waveform diagram for explaining the effect of the present embodiment. When the waveform of the video signal supplied between P1 and PD in Fig. 5 is as shown by the reference symbol VI in Fig. 6, the waveform of the video signal supplied between P2 and PD is The waveform is as shown by the reference symbol VP1 in FIG. Here, the video signal supplied between P2 and PD is transmitted through the correction line DL. For this reason, the waveform of the video signal that is actually supplied between P2 and PD is affected by the length of the correction line DL and the wiring capacity, as shown by reference numeral V2 in FIG. Thus, the waveform VI of the video signal between P1 and PD and the waveform V2 of the video signal between P2 and PD have the same waveform. This suppresses the occurrence of a luminance difference between PI-PD and P2-PD. As a result, even if the source bus line is disconnected, the degradation of display quality due to the disconnection is suppressed.

[0067] Further, according to the present embodiment, the data for each pixel forming portion (regardless of the presence or absence of disconnection) Video signal) is output from a predetermined output terminal of the source driver 310. Therefore, unlike the configuration in which the unused terminal of the source driver is used as the terminal for the correction line DL (the configuration of the second conventional example shown in FIG. 17), complicated data processing is performed in the display control circuit 200. It is not necessary to do.

[0068] Further, in the display control circuit 200, the address information held in the address register 27 and the value counted by the counter unit 24 are compared, and if the input data is data of the correction pixel forming unit, Based on the LUT28 for data correction, the data value of the input data is corrected. As described above, since the data value of the input data is corrected by digital processing, the correction amount can be easily set, and complicated processing is unnecessary. Therefore, the configuration according to the present embodiment can be realized with a relatively simple circuit.

[0069] <6.Modification>

Hereinafter, various modifications of the above embodiment will be described.

[0070] <6.1 First Modification>

In the above embodiment, the data correction LUT 28 stores the correspondence between the data value of the input data and the data value of the output data for each gradation of the input data. It is not limited to this. Only the data value of the output data corresponding to a specific value of the input data may be stored in the data correction LUT 28.

[0071] For example, as shown in FIG. 7, the correspondence between the data value of the input data and the data value of the output data is stored in the data correction LUT 28 for every eight gradations of the input data. Can do. At this time, for input data having data values not stored in the data correction LUT 28, the data value of the output data may be calculated by interpolation calculation. For example, if the data value of the input data is “122”, the data value Dout of the output data can be calculated by the following equation (1).

Dout = 122+ (130- 122) X 2/8 (1)

According to the above formula (1), the data value Dout of the output data is “124”.

[0072] According to the present modification, the amount of data stored in the data correction LUT 28 is reduced as compared with the above embodiment, so that the memory capacity for the data correction LUT 28 can be reduced. In addition, the data correction LUT 28 can be easily created. [0073] <6.2 Second modification>

In the above-described embodiment, the force described on the assumption that one data correction LUT 28 is provided for one disconnection is not limited to this. A configuration may be adopted in which a plurality of data correction LUTs 28 are provided corresponding to one disconnection. This will be described with reference to FIG.

FIG. 8 is a diagram schematically showing a display area 510 divided into nine areas (hereinafter referred to as “display blocks BLKa to BLKi”). Here, it is assumed that a disconnection has occurred at the position indicated by the reference symbol PD in the display block BLKb. For the part ahead of the disconnection point PD of the disconnection line SLa, the video signal is transmitted from the source driver 310 through the P1 part and the correction lines DL and P2 part for any of the display blocks BLKb, BLKe, and BLKh. .

[0075] However, comparing the time when data in block BLKb is transmitted with the time when data in block BLKh is transmitted, the length of the wiring (wiring length) through which data is transmitted is It takes longer when data in block BLKb is transmitted than when data in BLKh is transmitted. For this reason, when the data in block BLKb is transmitted, the waveform of the video signal tends to be rounded.

In order to suppress the waveform rounding as described above, it is preferable to increase the correction amount of the data value as the wiring length through which data is transmitted when a disconnection occurs is increased. For example, in the case of the configuration shown in FIG. 8, the correction amount is increased from left to right in the display area 510, and the correction amount is increased from the bottom to the top of the display area 510. ,.

Therefore, by adopting a configuration in which the data correction LUT 28 is provided for each display block as shown in FIG. 8, waveform rounding is suppressed according to the position of the disconnection point PD and the position of the correction pixel forming unit. Thus, the data value of the input data can be corrected. For example, when the data value (gradation value) of the input data is “128” in the entire display area 510, the data value of the correction pixel forming portion is set to a different value for each display block as shown in FIG. Is possible.

[0078] <6.3 Third Modification>

In the embodiment described above, the correction amount (of the output data) is determined according to the data value of the input data. The power with which the difference between the data value and the data value of the input data is different The present invention is not limited to this. Regardless of the data value of the input data, the correction amount may be a constant value. For example, the correction amount can be “1” regardless of the data value of the input data. In this case, if the data value of the input data is “50”, the data value of the output data is “51”, and if the data value of the input data is “253”, the data value of the output data is “254”.

[0079] According to this modification, the data correction LUT 28 is not required, and therefore, with a simple configuration, it is possible to suppress display defects when disconnection occurs.

[0080] <6.4 Fourth modification>

FIG. 10 is a block diagram showing an overall configuration of an active matrix liquid crystal display device according to a fourth modification. In this modification, unlike the above embodiment, the source driver 310 is provided with an input / output terminal for the correction line DL, and the buffer amplifier 311 is used as an output terminal. Here, it is assumed that the disconnection occurs at two locations (PD1 and PD2) as shown in FIG.

As shown in FIG. 10, regarding the wiring to which the corrected data is transmitted, the wiring length from the P2 portion to the disconnection location PD2 is larger than the wiring length from the P1 portion to the disconnection location PD1. For this reason, in order to suppress waveform rounding between P4 and PD2, the correction amount for the disconnection point PD2 is made larger than the correction amount (data value) for the disconnection point PD1. For example, if the target video signal waveform is as shown by reference symbol V in FIG. 11, the waveform of the video signal at P1 in FIG. 10 becomes the waveform shown by reference symbol VP1 in FIG. The data correction unit 22 in the display control circuit 200 corrects the data value of the input data so that the waveform of the video signal in the P2 part of 10 becomes a waveform as indicated by the reference symbol VP2 in FIG. As a result, even if disconnection occurs at a plurality of locations, the data value of the input data is corrected according to each disconnection location, and deterioration in display quality due to disconnection is suppressed.

Note that the above-described buffer amplifier 311 may be provided in the correction line DL in place of the source driver 310.

[0083] <6.5 Fifth Modification>

In the above embodiment, the scan direction (data is displayed in each pixel formation portion in the display area 510). The order of writing) is based on the assumption that the left force is also right (reference symbol K1 in Fig. 12) in the horizontal direction and from top to bottom (reference symbol K3 in Fig. 12) in the vertical direction. The present invention is not limited to this. The horizontal scan direction can be from right to left (reference symbol K2 in Figure 12) !, and the vertical scan direction is from bottom to top (reference symbol K4 in Figure 12). There may be. Further, the combination of the scan direction in the horizontal direction and the scan direction in the vertical direction is not limited. However, the processing in the comparison unit 25 in the display control circuit 200 differs depending on the combination of the scan directions in the horizontal and vertical directions, and will be described below. Note that the display panel 500 of this liquid crystal display device will be described as being of the VGA type (640 × 480).

[0084] In the comparison unit 25 in the display control circuit 200, the H count value CntH and the H register value RegH are compared, and the V count value CntV and the V register value RegV are compared as in the above embodiment. The ON / OFF state of the data correction flag Dflg is determined according to the comparison result. In the following, how to determine the ON / OFF state of the data correction flag Dflg depending on the scanning direction will be described in different cases. In the following, the H count value CntH is abbreviated as “CntH”, the V count value CntV as “CntV”, the H register value RegH as “R egH”, and the V register value RegV as “RegV”.

[0085] <6. 5. 1 Left force for horizontal, right, top to bottom for vertical

>

When CntH and RegH are different values, the data correction flag Dflg is turned off. On the other hand, when CntH and RegH are equal, if CntV is RegV or less, the data correction flag Dflg is turned off, and if CntV is greater than RegV, the data correction flag Dflg is turned on.

[0086] <6. 5. 2 For horizontal direction, left to right, for vertical direction, bottom to top

>

When CntH and RegH are different values, the data correction flag Dflg is turned off. On the other hand, when CntH and RegH are equal, if CntV is (479— RegV) or less, the data correction flag Dflg is turned on, and if CntV is greater than (479— RegV), the data correction flag Dflg is turned off. Put it in a state. [0087] <6.5.3 Right force for horizontal direction Left, for top to bottom for vertical direction>

When CntH and (639—RegH) are different values, the data correction flag Dflg is turned off. On the other hand, when CntH and (639-RegH) are equal, if CntV is RegV or less, the data correction flag Dflg is turned off, and if CntV is greater than RegV, the data correction flag Dflg is turned on.

[0088] <6. 5. 4 Right to left for horizontal direction, bottom to top for vertical direction

>

When CntH and (639—RegH) are different values, the data correction flag Dflg is turned off. On the other hand, when CntH is equal to (639—RegH), if CntV is (479—RegV) or less, the data correction flag Dflg is turned on, and if CntV is greater than (479—RegV), the data Set the correction flag Dflg to OFF.

[0089] As described above, any processing (combination of scan directions in the horizontal and vertical directions) can be performed by making the processing in the comparison unit 25 different depending on the combination of scan directions in the horizontal and vertical directions. The present invention can also be applied.

[0090] <6.6 Sixth Modification>

In the embodiment described above, the power described with reference to the example in which the source driver 310 is disposed only on one side (upper side) of the display panel 500 is not limited to this. For example, as shown in FIG. 13, the present invention can also be applied to a configuration in which source drivers 311 and 312 are provided on both upper and lower sides of the display panel 500. In the configuration shown in FIG. 13, for example, the video signal is applied from the upper source driver 311 for the odd-numbered source bus lines, and the video signal from the lower source driver 312 for the even-numbered source bus lines. Is applied.

Here, when the upper source driver 311 and the lower source driver 312 are controlled by different display control circuits 200, the respective scan directions are taken into consideration in each display control circuit 200. The comparator 25 should be operated. On the other hand, when the upper source driver 311 and the lower source driver 312 are controlled by the same display control circuit 200, In this case, the comparison unit 25 in the display control circuit 200 may be operated by considering the scanning direction and dividing the case depending on whether the H count value CntH is an odd number or an even number.

<7.Others>

Although the liquid crystal display device has been described as an example in the above-described embodiment and each modification, the present invention is not limited to this. The present invention can also be applied to other display devices such as organic EL (Electro Luminescnet).

Claims

The scope of the claims

[1] A display unit that displays an image in a predetermined display area, a plurality of video signal lines for respectively transmitting a plurality of video signals representing the image, and the plurality of video signal lines in the display area A plurality of scanning signal lines intersecting each other, and a plurality of pixel forming sections arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively, A display device that displays the image based on input pixel data that is input data for

A video signal output unit configured to supply the plurality of video signals to the plurality of video signal lines based on the output pixel data;

Have

The output pixel data generation unit identifies a correction pixel formation unit, which is a pixel formation unit to which a video signal transmitted through the correction wiring is supplied, based on the address information, and the correction pixel formation unit A display device, wherein the output pixel data is generated by correcting a data value of the input pixel data.

2. The display device according to claim 1, wherein the correction of the data value of the input pixel data is performed by digital processing for the correction pixel forming unit.

[3] The output pixel data generation unit may generate the output pixel data by adding a predetermined value to a data value of the input pixel data for the correction pixel formation unit. Item 3. The display device according to Item 2.

[4] A data correction table for storing a correspondence relationship between the data value of the input pixel data and the data value of the output pixel data, The output pixel data generation unit generates the output pixel data by correcting a data value of the input pixel data based on the data correction table for the correction pixel formation unit. Item 3. The display device according to Item 2.

[5] The data correction table stores a correspondence relationship between a data value of the input pixel data and a data value of the output pixel data for each gradation of the input pixel data. The display device according to claim 4.

[6] The data correction table stores a correspondence relationship between the data value of the input pixel data and the data value of the output pixel data for each of a plurality of gradations of the input pixel data. The display device according to claim 4, wherein the display device is characterized.

7. The display device according to claim 4, further comprising the data correction table for each display block obtained by dividing the display area into a plurality of areas.

[8] The address information includes information for specifying video signal lines included in the plurality of video signal lines and information for specifying scanning signal lines included in the plurality of scanning signal lines. The display device according to claim 1.

[9] The display device according to claim 1, wherein the video signal output unit includes a notch for amplifying the video signal transmitted through the correction wiring.

10. The display device according to claim 1, wherein the correction wiring is provided with a nota for amplifying a video signal transmitted through the correction wiring.

11. The display device according to claim 1, wherein the display device is a liquid crystal display device.