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WO2008035392A1 - Dispositif de circuit intégré à semi-conducteur - Google Patents

Dispositif de circuit intégré à semi-conducteur Download PDF

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Publication number
WO2008035392A1
WO2008035392A1 PCT/JP2006/318481 JP2006318481W WO2008035392A1 WO 2008035392 A1 WO2008035392 A1 WO 2008035392A1 JP 2006318481 W JP2006318481 W JP 2006318481W WO 2008035392 A1 WO2008035392 A1 WO 2008035392A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor integrated
integrated circuit
circuit device
bit lines
resistance state
Prior art date
Application number
PCT/JP2006/318481
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English (en)
Japanese (ja)
Inventor
Kenzo Kurotsuchi
Satoru Hanzawa
Norikatsu Takaura
Yuichi Matsui
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2006/318481 priority Critical patent/WO2008035392A1/fr
Priority to JP2008535200A priority patent/JP4966311B2/ja
Publication of WO2008035392A1 publication Critical patent/WO2008035392A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly, a memory cell that discriminates stored information using a difference in resistance value, for example, a high-density integrated memory circuit including a memory cell using a phase change material
  • the present invention relates to a technology effective when applied to a logic-embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, or a semiconductor integrated circuit device having an analog circuit.
  • FLASH memory Because of its inherently low speed, it is used as a programmable ROM. On the other hand, high-speed RAM is required as work memory, and both FLASH and DRAM memory are installed in portable devices. If an element with these two memory features can be realized, it would be possible to integrate all the semiconductor memory by force if it is possible to integrate FLASH and DRAM on a single chip. Very big!
  • Phase change memory is sometimes called PRAM (Phase change RAM) or OUM (Ovonic Unified Memory).
  • phase change memory cells use materials that can be reversibly switched from one phase to another. These phase states can be read out depending on the difference in electrical characteristics. For example, these materials can change between a disordered phase in the amorphous state and an ordered phase in the crystalline state. In the amorphous state, information can be stored by utilizing this difference in electrical resistance, which is higher in electrical resistance than in the crystalline state.
  • a suitable material for the phase change memory cell is an alloy containing at least one element of sulfur, selenium, and tellurium called chalcogenide.
  • chalcogenide is an alloy of germanium, antimony and tellurium (Ge Sb Te), which has already been rewritten
  • phase change is obtained by locally raising the temperature of the chalcogenide. Below 70 ° C or below 130 ° C, both phases are stable and information is retained.
  • the 10-year data retention temperature for chalcogenides is generally 70-130 ° C, depending on the composition. Holding for 10 years above this temperature causes a phase change from the amorphous state to the thermodynamically stable crystalline state.
  • chalcogenide is held at a crystallization temperature of 200 ° C or higher for a sufficient period of time, the phase changes and becomes a crystalline state.
  • the crystallization time depends on the chalcogenide composition and the temperature at which it is retained. In the case of Ge2Sb2Te5, it is 150 nanoseconds, for example. In order to return the chalcogenide to the amorphous state, the temperature is raised to the melting point (about 600 ° C) or more and rapidly cooled.
  • a method for raising the temperature there is a method in which an electric current is passed through the chalcogenide and heated by Joule heat generated in the chalcogenide or in an adjacent electrode.
  • crystallizing the chalcogenide of the phase change memory cell is called a set operation, and making it amorphous is called a reset operation.
  • the state in which the phase change part is crystallized is called a set state or a crystalline state, and the state in which the phase change part is amorphized is called a reset state or amorphous state.
  • the set time is, for example, 150 nanoseconds
  • the reset time is, for example, 50 nanoseconds.
  • a read operation (hereinafter referred to as a read operation) is as follows. By applying a voltage to the chalcogenide and measuring the current passing through it, the resistance of the chalcogenide is read and information is identified. If the chalcogenide is in the set state at this time, even if the temperature is raised to the crystallization temperature, the chalcogenide is crystallized from the beginning, so the set state is maintained. However, in the case of a reset state, information is destroyed. Therefore, the read voltage must be a very small voltage such as 0.3V so that crystallization does not occur.
  • phase change memory changes by 2 to 3 digits depending on whether the resistance value of the phase change part is crystalline or non-crystalline, and this resistance value corresponds to binary information '0' and '1' Therefore, the sensing operation is easy and the reading is fast because the resistance difference is large! /.
  • multi-value storage can be performed by supporting information in ternary or higher.
  • the information storage unit includes a chalcogenide, an upper electrode and a lower electrode sandwiching the chalcogenide.
  • the lower electrode has a plug structure with a smaller contact area with the chalcogenide than the upper electrode.
  • Non-Patent Document 1 describes a general operation of the phase change memory cell as described above.
  • the reset operation is performed by starting the word line and applying a current pulse with a pulse width of 20 to 50 nanoseconds to the bit line.
  • the set operation is performed by starting the word line and applying a current pulse with a pulse width of 60 to 200 nanoseconds to the bit line.
  • Read operation is performed by starting the word line and applying a current pulse with a pulse width of 20 to: LOO nanoseconds to the bit line.
  • a method of controlling the reset current using a word line has been proposed as described in FIG. 8 of Patent Document 1.
  • Non-Patent Document 2 describes that the characteristics of an irregular solid such as an amorphous semiconductor can be expressed by an equivalent circuit based on the CTRW (continuous-time random-walk) approximation.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-260014
  • Non-Patent Document 1 “2004 IEEE International Solid-State Circuits Conference, Digest, International 'Solid State' Circuit Conference, Digest of Technical Technical Papers or rechnical Papers) ”, p. 40—41
  • Non-Patent Document 2 “Universality of Dynamic Electrical Conduction in Disturbed Systems”, Applied Physics, 1996, Vol. 65, No. 3, p. 256-260
  • the memory cell of the phase change memory as described above has a configuration as shown in FIG. 16, for example.
  • FIG. 16 is a circuit diagram showing a configuration example around the memory cell in the semiconductor integrated circuit device studied as a premise of the present invention.
  • Memory cell MC also has select element SW and phase change element R force.
  • the selection element SW it is preferable to use an NMOS transistor having a good process compatibility as a microcomputer mixed memory and a large driving capability. NMOS transistors have a larger drive current than PMOS transistors.
  • the current flowing through the phase change element R flows from the bit line BL toward the source line SL.
  • the phase change element R is placed between the selection element SW and the bit line BL.
  • the source potential of the SW rises compared to the source line SL. descend.
  • the gate width of the selection element SW must be increased, which causes a problem that the memory cell area increases. Therefore, the phase change element R should be placed between the selection element SW and the bit line BL.
  • FIG. 17 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • the memory cell MCOO is selected, the reset operation, the set operation, and the read operation are performed, and the memory cell MC01 is not selected.
  • applying a rectangular wave pulse to the bit line BLO during the operation of the MCOO affects the memory cell MC01 connected to the same bit line BLO.
  • the voltage of the word line WL1 connected to MC01 is OV and is not selected. Therefore, the selection element SW01 is turned off, and the drain current ID01 does not flow.
  • the equivalent circuit of R01 uses the CTRW approximation described in Non-Patent Document 2, and a pair of capacitors and resistors as shown in FIG. It becomes a circuit connected to. Therefore, R01 accumulates electric charge, and as a result, as shown in FIG. 17, a current IBL01 is generated for R01 when the bit line BLO rises and falls.
  • a capacitive interface layer may be formed between the phase change element R and the selection element SW. In this case as well, the current IBL01 is generated.
  • Semiconductor memory is generally required to retain data for 10 years at a temperature of 70 to 120 ° C.
  • the 10-year data retention temperature of amorphous chalcogenides is generally 70 to 130 ° C, depending on the composition, but there is little margin for 10 ° C on the high temperature side. Therefore, in order to ensure the data retention characteristics, it is necessary to minimize the current flowing through the unselected memory cell in the reset state.
  • FIG. 19 and FIG. 20 are diagrams for explaining the contents of an experiment conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells.
  • the ambient temperature is room temperature, as shown in Figure 19.
  • the memory cell MC shown in FIG. 19 includes a selection element SW and a phase change element R, and the source line SL is set to 0 V and the word line WL is set to 0.4.
  • the selection element SW is an NMOS transistor, and its threshold voltage is 0.2 to 0.4 V, and is off. Normally, the current that flows when 3V is applied to the drain of the selection element SW is 100 nanoamperes or less, and even if such a current is applied, the resistance of the phase change element R does not change.
  • a pulse having an amplitude of 3 V, a pulse width of 30 nanoseconds, a rising width of 2 nanoseconds, and a falling width of 2 nanoseconds was applied to the bit line BL.
  • rise time and fall time There are several types of definition of rise time and fall time.
  • % (2.7V) force is also the time to transition to 10% (0.3V). And such a pulse was applied 100,000 times continuously.
  • FIG. 21 is a diagram showing an example of the experimental results of FIGS. 19 and 20.
  • Figure 21 shows the resistance value of the TEG immediately after resetting and the resistance value of the TEG after performing a disturb test in which 100,000 pulses are applied. Conducting the disturb test resulted in an increase in resistance of an order of magnitude or more. After the resistance rises, the voltage required for the set operation increases, and it is difficult to transition to the set state in the normal set operation.
  • the current flowing through the phase change element scale reduces the data retention characteristics of the phase change memory at high temperatures, and the reset state can be easily destroyed, and information can be lost by changing to the set state. is there. Thus, there is a concern that when the bit line BL is driven with a rectangular waveform pulse, the current flows through the non-selected memory cells MC connected to the bit line, thereby reducing the reliability of the phase change memory. Is done.
  • a semiconductor integrated circuit device is controlled by a word line and a bit line, a phase change element (memory element) having one end connected to the bit line, and a word line connected to the other end of the memory element.
  • the memory element is written in a high resistance state, the rise time and fall time of the bit line is longer than that of the word line.
  • disturbance to the non-selected storage elements connected to the same bit line is reduced, and the reliability of the phase change memory can be improved.
  • the memory element is written in a low resistance state, it is possible to improve the reliability of the phase change memory by increasing the rise time and the fall time of the bit line.
  • the force required to quench the memory element can be realized by using the falling edge of the word line.
  • a capacitive element is provided in the write circuit in which the bit line force is also connected via the bit line selection switch (second transistor).
  • a method of generating a CR delay by connecting this capacitive element when writing is used.
  • Another example is a method of designing the writing circuit with a low driving capability. If the latter is used, the circuit area can be reduced compared to the former.
  • the driving capability (eg, gate width) of the write switch (third transistor) that is provided in the write circuit and outputs voltage or current at the time of write is selected by the bit line. It is better to make it smaller than the drive capability (eg gate width) of the switch (second transistor).
  • the driving capability (eg gate width) of the write switch (third transistor) that is provided in the write circuit and outputs voltage or current at the time of write is selected by the bit line. It is better to make it smaller than the drive capability (eg gate width) of the switch (second transistor).
  • the disturbance to the non-selected memory element becomes more obvious when a capacitive interface layer for increasing the thermal efficiency is formed at the connection portion on the first transistor side of the memory element. It becomes more effective when the above-described configuration is applied to such a configuration.
  • the memory element is put in a high resistance state and a low resistance state.
  • the same voltage toward the bit line A value can be output.
  • currents of different magnitudes may be supplied to the memory element by using different word line voltage values for the high resistance state and the low resistance state.
  • FIG. 1 is a circuit diagram showing a configuration example of a part around a memory cell in a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • FIG. 3 is a main part layout diagram showing a configuration example of a memory cell array including the memory cell of FIG.
  • FIG. 4 is a cross-sectional view of a principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages and showing a configuration example between XX ′ in FIG. 3 in each stage.
  • FIG. 5 shows the manufacturing process of the memory cell array of FIG. 3 step by step, and is a cross-sectional view of the main part showing a configuration example between XX ′ of FIG. 3 in each step.
  • FIG. 6 is a cross-sectional view of the principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages, and showing a configuration example between XX ′ in FIG. 3 in each stage.
  • FIG. 7 is a cross-sectional view of a principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages, and showing a configuration example between XX ′ in FIG. 3 in each stage.
  • FIG. 8 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 9 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • FIG. 12 shows a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. It is a circuit diagram which shows an example.
  • FIG. 13 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • FIG. 14 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
  • FIG. 15 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.
  • FIG. 16 is a circuit diagram showing a configuration example around the memory cell in a semiconductor integrated circuit device studied as a premise of the present invention.
  • 17 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • FIG. 18 is an equivalent circuit diagram showing a storage element in an amorphous state.
  • FIG. 19 is a diagram for explaining the contents of an experiment conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells.
  • FIG. 20 is a diagram for explaining the contents of experiments conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells.
  • FIG. 21 is a diagram showing an example of the experimental results of FIGS. 19 and 20.
  • the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate.
  • the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally.
  • the reset state is a low level 'L' (or '0,')
  • the set state is a noise level ' ⁇ ' (or '1,').
  • the reset state is 'H' and the set state is It can also be 'L'.
  • the cause of the disturbance of the unselected memory cells is that when the voltage of the bit line changes, the current flows in the memory cells connected to the same bit line and having different word lines.
  • the first embodiment extends the charge / discharge time of the capacitance component included in the phase change element by reducing the speed of the voltage change of the bit line. This Therefore, the peak current can be reduced, so that the heat generation of the non-selected memory cells is reduced by thermal diffusion, and the influence of disturbance can be reduced.
  • FIG. 1 is a circuit diagram showing a configuration example of a part around a memory cell in the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • the semiconductor integrated circuit device includes a bit line BLO, a plurality of word lines WLO and WL1 corresponding to the BLO, and memory cells MCOO and MC01 arranged at the intersections of these word lines and bit lines. Is included.
  • the memory cell MCOO includes a selection element SWOO and a phase change element ROO.
  • the phase change element ROO is connected between the selection element SWOO and the bit line BLO.
  • the phase change element ROO is connected to the source line SLO that is one end of SWOO via the ROO.
  • a current path is formed.
  • the memory cell MC01 includes a selection element SW01 and a phase change element R01, which is connected between the selection element SW01 and the bit line BLO, and the selection element SW01 is controlled by the word line WL1.
  • FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • the case where the memory cell MCOO is operated is taken as an example.
  • the bit line BLO and the word line WLO are driven, and the other bit lines and the word line remain fallen.
  • reset operation is performed, first the bit line BLO is turned on.
  • the rise time trb at this time is made longer than the rise time trw of the word line WLO described later.
  • the word line WLO is raised and a current is passed through the phase change element ROO to melt it. After that, the word line WLO falls to rapidly cool the ROO and make it amorphous.
  • the falling time tfw of the word line WLO needs to be shortened for convenience of rapid cooling. After that, the bit line BLO falls.
  • the fall time tfb at this time is longer than the fall time tfw of the word line WLO. Because the phase change element is not rapidly cooled by lowering the bit line, the bit line has a short fall time and is not necessary!
  • the charge / discharge current IBLO 1 flowing through the phase change element RO 1 of the non-selected memory cell MCO 1 can be reduced. It becomes possible.
  • the rapid cooling required for the reset operation is performed using the fall of the word line WLO, the reset operation can be performed without problems even if the fall time of the bit line BLO is lengthened. Therefore, it is possible to reduce the influence of disturb while guaranteeing reliable memory operation. The reliability of the phase change memory can be improved.
  • the current that flows through the bit line BLO is the largest during the reset operation. Therefore, it is necessary to increase the rise time Z fall time of the BLO during the reset operation. The force that is most effective Of course, it is also beneficial to increase the rise and fall times during set operation.
  • the rise time Z fall time of the bit line BLO is longer than the rise time Z fall time of the word line WLO during the set operation.
  • the timing at which a voltage is applied to the phase change element ROO along with the set operation may be defined by the word line WLO or the bit line BLO.
  • the voltage value applied to the phase change element ROO is determined here by the voltage value of the bit line BLO.
  • FIG. 3 is a main part layout diagram showing a configuration example of a memory cell array including the memory cell of FIG.
  • a plurality of word lines WL are arranged in parallel, and a plurality of bit lines BL are arranged in parallel in a direction perpendicular thereto.
  • a plug electrode PLG is provided on one side across a word line WL, and a source line SL is provided on the other side.
  • the plug electrode PLG is located below the bit line BL in the cross-sectional structure, and a phase change element (not shown) is connected to the plug electrode PLG.
  • the optimum distance between the source line SL and the bit line BL is selected according to the drive current of the memory cell.
  • FIG. 4 to 7 show the manufacturing process of the memory cell array of FIG. 3 step by step, and are principal part cross-sectional views showing a configuration example between X and X ′ of FIG. 3 in each step.
  • the structure shown in the cross-sectional view of the main part of FIG. 4 is fabricated using a normal semiconductor manufacturing process.
  • the diffusion layer DF is separated by the field oxide film ISL 1.
  • the gate electrode GT is in contact with the gate insulating film ISL2, the sidewall SDW, and the metal silicide SS.
  • An adhesion layer (barrier layer) BR1 is formed to improve the adhesion between the contact CNT1 and the interlayer insulation film ISL3 and prevent peeling.
  • a metal wiring layer Ml is formed on the contact CNT1.
  • Plug electrode PLG is a material that forms non-omic contact with chalcogenide. select.
  • a plug material with high thermal resistance it is possible to prevent the diffusion of Joule heat, which is a plug force, and to reduce the power required for rewriting.
  • TiN titanium nitride
  • W tungsten
  • an interface layer L may be formed between the plug electrode PLG and the adhesion layer BR 2 and the chalcogenide CN.
  • the interface layer L has a higher electric resistance than the plug electrode PLG, and efficiently converts current to Joule heat as a heater during the rewriting operation.
  • the interface layer L can also be used as an adhesive layer.
  • Interfacial layer L has good adhesive strength with interlayer insulating film IS L3, plug electrode PLG and chalcogenide CN. Can be prevented. As a result, the manufacturing yield and the reliability associated with rewriting are improved.
  • the interface layer L for example, Ta O
  • Examples include capacitive materials such as 25 (tantalum oxide).
  • a chalcogenide CN serving as a phase change element and an upper electrode U are formed by sputtering or vacuum evaporation to form an interlayer insulating film ISL4.
  • a composition of chalcogenide CN for example, a Ge—Sb—Te alloy having a wide track record in a recordable optical disk, or an alloy containing an additive in the alloy is suitable.
  • a contact hole is formed, and an adhesion layer BR3 and a contact CNT2 with the bit line are formed by chemical vapor deposition (CVD). Further, as shown in FIG. 7, an adhesion layer BR4 is formed, and a bit line BL is formed by sputtering. Subsequently, by forming an interlayer insulating film ISL5 and further forming an upper wiring, a desired memory can be manufactured.
  • CVD chemical vapor deposition
  • Such a manufacturing method can be manufactured in accordance with a normal CMOS logic mixed design rule, and is also suitable for manufacturing a logic embedded memory. Further, as described in FIG. 5, when the interface layer L is formed, the charge / discharge current flowing through the phase change element of the non-selected memory cell described above may be larger. Therefore, a more beneficial effect can be obtained by applying the operation of increasing the rise / fall time as described in FIG. 2 to the configuration having such an interface layer. As described above, by using the semiconductor integrated circuit device of the first embodiment, the reliability of the phase change memory can be improved. In particular, when the phase change memory includes an interface layer between the chalcogenide and the plug electrode, it is possible to improve the reliability of the phase change memory.
  • FIG. 8 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention.
  • the semiconductor integrated circuit device shown in FIG. 8 includes a memory array unit ARY, an X-system address decoder X—DEC, a Y-system address decoder Y—DEC, and a read / write circuit RWC.
  • the memory array unit ARY also includes a plurality of word lines WLO to WLn, a plurality of bit lines BLO to BLm, and a plurality of memory cells MCO 0 to MCnm provided at the intersections of the word lines and the bit lines. .
  • a force that may include a plurality of source lines SLO to SLm paired with a plurality of bit lines BL 0 to BLm may be omitted. Ground as ground!
  • the memory cell MCOO includes a selection element MNOO and a storage element ROO.
  • the memory element R 00 is a phase change element, and has a low resistance of, for example, lk Q to 10 kQ in the crystalline state, and has a high resistance of, for example, 10 (3 ⁇ 4 ⁇ to 100 ⁇ ).
  • the selection element MNOO is The gate electrode of the selection element MNOO is connected to the word line WL 0, the drain electrode is connected to one end of the storage element ROO, and the source electrode is connected to the source line (ground GND).
  • Each word line WL0 to WLn is connected to an X system address decoder X—DEC, and one word line WL is selected by an X system address signal generated by X—DEC.
  • bit line BL is connected to a Y-system address decoder Y-DEC, and one of the bit line selection switches YS0 to YSm is selected by the Y-system address signal generated by the Y-DEC.
  • Bit line BL is connected to RWC, which will be described later, via node N1.
  • RWC read / write circuit
  • RWC may be provided for each memory array unit ARY.
  • a plurality of RWCs may be provided. In that case, since multiple bits can be written and read simultaneously, there is an effect that high-speed operation is possible.
  • Read 'Write circuit RWC includes a read current source Ird and a read switch R SW, a set current source Iset and a set switch SS—SW, a reset current source Irst and a reset switch RS—SW, and a sense Includes amp SA.
  • the RWC includes a capacitance Cwt, a capacitance addition switch WC-SW, and a ground switch GSW! RSW, SS—SW, and RS—SW are switches that connect Ird, Iset, and Irst to nodes NI, respectively, and this node N1 is connected to the corresponding bit line when the bit line selection switch YS is selected. Is done.
  • the voltages Vrd, Vset and Vrst are supplied to one end different from the switch side of Ird, Iset and Irst, respectively.
  • the sense amplifier SA amplifies the read signal of the selected bit line by comparing it with the reference voltage REF and outputs it to the data output line D.
  • the capacity addition switch WC-SW is a switch for connecting the capacity Cwt to the node N1.
  • C wt is formed using a MOS transistor, for example.
  • the ground switch GSW connects node N1 to ground GND.
  • WC-SW, Cwt, and GSW are means for increasing the rise and fall times of the bit line BL, as will be described later.
  • FIG. 9 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • the reset operation is performed as follows. Read switch RSW, set switch SS—SW, and ground switch GSW are turned off. First, turn on the additional switch WC—SW, Select BLO by Y—DEC and YSO, then turn on reset switch RS—SW. As a result, electric charge is accumulated in the capacitor Cwt in addition to the wiring capacitance such as BLO, so that the voltage of BLO does not rise instantaneously and the rise time can be made longer than the word line WLO described later.
  • RESET reset operation
  • the memory element RnO of the memory cell MCnO is hardly affected by the voltage change because the voltage change speed of the bit line BLO to which it is connected is slow. As a result, the current IcelnO flowing through RnO can be reduced.
  • the set operation is performed as follows. Read switch RSW and reset switch RS- SW are turned off. First, the capacity addition switch WC-SW is turned on, and BLO is selected by Y-DEC and YSO. Next, turn on the set switch SS-SW. Then, charges are accumulated in the capacitor Cwt in addition to the wiring capacitance such as BLO. Therefore, the voltage of BLO does not rise instantaneously, and the rise time can be made longer than the word line WLO described later.
  • the read operation is performed as follows.
  • the reset switch RS-SW, ground switch GSW, set switch SS— SW, and capacitance addition switch WC— SW are turned off.
  • the memory cell MCOO is selected by X—DEC and Y—DEC, and the read switch RSW is turned on. After a certain time, the read switch RSW is turned off. At this time, a current corresponding to the resistance value flows in the memory element ROO. That is, if the storage element ROO is in a high resistance state (amorphous state), the bit line BLO is charged at a higher voltage than in the low resistance state (crystalline state).
  • the sense amplifier enable signal SE By turning on the sense amplifier enable signal SE, this potential difference is amplified by the sense amplifier SA, and data can be obtained from the data output line D.
  • the capacitance addition switch WC-SW is off, the bit line capacitance is small and high-speed and power-saving reading is possible. That is, in the read operation, the voltage used is low unlike the set operation or the reset operation. Therefore, even if the capacitor addition switch WC-SW is turned off, the storage element of the non-selected memory cell is not easily affected. Information is not easily destroyed.
  • the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it.
  • the area overhead is less affected. That is, as shown in FIG. 8, if a single capacitance Cwt is provided for a plurality of bit lines BLO to BLm, the capacitance can be covered to some extent by the wiring capacitance.
  • the provision of the capacitance Cwt in the read / write circuit RWC has the effect of stabilizing the bit line capacitance during writing.
  • the capacity of the memory cell in terms of bit line strength is larger in the memory cell in the reset state than in the set state. Therefore, comparing the case where a large number of reset state memory cells are connected to the bit line and the case where a large number of set state memory cells are connected, the former has a larger bit line capacity.
  • the change in bit capacity depending on the storage state of each memory cell affects the transition timing of the bit line at the time of writing, so that stable writing becomes difficult. So, by using the capacity Cwt, As a result, it is possible to keep the bit line capacity above a certain value, and to reduce relative changes in the bit line capacity. As a result, stable writing can be performed regardless of the storage state of the memory cell.
  • FIG. 10 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention.
  • the semiconductor integrated circuit device shown in FIG. 10 includes a memory array unit AR Ya, an X-system address decoder X-DECa, a Y-system address decoder Y-DECa, and a read / write circuit RWCa.
  • the memory array unit ARYa has the same configuration as that of FIG. 8 described above, and includes a plurality of sub word lines SWL0 to SWLn, a plurality of bit lines BL0 to BLm, and intersections of the sub word lines and the bit lines.
  • a plurality of memory cells MC00 to MCnm provided respectively. Again, as in Figure 8, the source line is omitted and is grounded.
  • Each of the memory cells MCOO to MCnm has the same configuration as that in FIG. 8, for example, MCOO includes a selection element MNOO and a storage element R00, and the selection element MN00 is, for example, an NMOS transistor.
  • the gate electrode of the selection element MN00 is connected to the sub word line SWL0, the drain electrode is connected to one end of the storage element R00, and the source electrode is connected to the source line (ground GND).
  • the other end of the storage element R00 is connected to the bit line BL0.
  • Each sub word line SWL0 to SWLn is connected to an X system address decoder X-DECa.
  • X— DECa turns on sub word line drivers XDRO to XDRn that drive sub word lines SWL0 to SWLn, main word lines M WLl to MWLp that control ON / OFF of XDRO to XDRn, and XDRO to XDRn, respectively.
  • FX drivers FXDR1 to FXDR8, which set the drive voltage of SWLO to SWLn at the time, are also configured. For example, when XDRO is turned on, the output voltage FXO of FXDR1 is output to SWLO via the word line drive transistor XTR in XDRO.
  • the output voltage FXO of FXDR1 becomes the power supply voltage VDD corresponding to the control signal FXI, and becomes the ground GND corresponding to the control signal FXB.
  • Each bit line BLO ⁇ : BLm is connected to a Y-system address decoder Y—DECa.
  • Y—DE Ca includes bit line selection switches YSO to YSm that select and connect any of the plurality of bit lines BLO to BLm to node N1.
  • YSO includes a bit line connection transistor YTR 0, and this YTRO connects BLO and N 1 when the bit line selection signal BLSWO is activated.
  • YTRO is composed of, for example, a MOS transistor.
  • a bit line connection transistor (not shown) in YSm connects BLm and N1 when the bit line selection signal BLSWm is activated.
  • a read / write circuit RWCa is connected to the node N1.
  • RWCa includes a reset current source Irst and reset switch RS—SW, a set current source Iset and set switch SS—SW, and a readout circuit.
  • the read circuit includes a voltage source Vpre for bit line precharge, a precharge switch PRE and a read switch TG for connecting Vpre to a node N1, and a sense amplifier SA connected to a node between TG and PRE. Is included. Note that the voltage V rst and the voltage Vset are supplied to one end different from the switch side of the Irst and Iset, respectively.
  • RS-SW and SS-SW are composed of, for example, MOS transistors.
  • the rise time Z fall time of the bit line during the write operation is reduced by reducing the drive capability of the reset switch RS-SW and the set switch SS-SW. Make it longer.
  • the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the word line drive transistor XTR in the sub word line driver XDR.
  • the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.
  • FIG. 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • a case where operation is performed on the memory cell MCOO will be described as an example.
  • RESET reset operation
  • the reset switch RS— SW and bit line selection switch YSO turns on the bit line connection transistor YTRO to select and start the bit line BLO.
  • the drive time of RS-SW is low, so the rise time of BLO becomes long. Therefore, for example, the memory cell MC10 connected to the same bit line BLO The current IcellO flowing through the storage element RIO can be reduced.
  • control signal FXI and the main word line MWL1 for the FX driver FXDR1 are selected and the control signal FXB is deselected to start up the sub word line SWLO.
  • FXI and MWL1 are deselected and SWLO is lowered by selecting the control signal FXB.
  • each transistor in the sub word line driver XDRO including the word line drive transistor XTR is designed to have high driving capability, and SWLO can be rapidly lowered.
  • the storage element ROO is rapidly cooled to be in an amorphous state.
  • turn off RS- SW and YT RO to bring down BLO.
  • the LB-SW drive capability is designed to be low, so the BLO fall time is long. Therefore, for example, the current IcellO flowing through the memory element RIO can be reduced.
  • the bit line BLO is selected and started by turning on the bit line connection transistor YTRO in the set switch SS-SW and the bit line selection switch YSO.
  • the rise time of BLO becomes long, and for example, the current IcellO flowing through the storage element RIO can be reduced.
  • the sub word line SWLO is started in the same manner as in the reset operation, and after passing a smaller current to the storage element ROO than in the reset operation for a longer time than in the reset operation, the SWLO is lowered. . Also, with the fall of SWLO, turn off SS- SW and YTRO to bring down BLO.
  • the fall time of BLO becomes long.
  • the storage element ROO is in a crystalline state, and further, for example, the current IcellO flowing through the storage element RIO can be reduced.
  • the bit line BLO is selected by turning on the read switch TG, the precharge switch PRE, and the bit line connection transistor YTRO, and the voltage source Vpre is applied to the BLO. Is precharged. At this time, since the precharge voltage is low, for example, the current IcellO flowing as a disturb in the storage element RIO is small, and the influence of the disturb on the unselected memory cell is small. Then, turn off PRE and start up the sub word line SWLO in the same way as during reset operation. As a result, the voltage of BLO is maintained almost at the precharge voltage when the storage element ROO is in an amorphous state. In the crystal state, it is discharged toward the ground GND. Therefore, reading can be performed by sensing the difference in the voltage of the BLO with the sense amplifier SA. After the read data is confirmed, turn TG and YTRO off.
  • the drive capability (gate width) of the reset switch RS-SW or set switch SS-SW is designed to be somewhat large in order to supply the current or voltage to the bit line BL at high speed.
  • the RS-SW gate width must be made sufficiently large in a method that realizes rapid cooling in the reset operation by stopping the current to the bit line BL.
  • the bit line connection transistor YTR must be provided for each bit line unlike the RS-SW or SS-SW, and the number of transistors increases. Designed with a smaller gate width than SW.
  • bit line connection transistor YTR having a gate width as large as possible within the allowable circuit area is designed.
  • Design RS-SW or SS-SW so that the gate width is smaller than that.
  • the bit line connection transistor YTR is designed to have a certain gate width, so that a high-speed read operation is possible.
  • the gate width of RS-SW or SS-SW is designed to be small, so that the transition time of the bit line during write operation can be lengthened, and disturbance to unselected memory cells can be prevented. The influence can be reduced. Even when the gate width of RS-SW is designed to be small, there is no problem because the rapid cooling during the reset operation is performed by the fall of the word line WL.
  • the gate width of the word line drive transistor XTR in the sub word line driver XDR is set to the reset switch RS-SW or set switch SS— Designed to be smaller than the gate width of SW. This is because the number of only one RS-SW or SS-SW in the plurality of bit lines BL is smaller than XTR existing in each sub-word line SWL.
  • the XTR gate width sufficient to perform the rapid cooling of the reset operation by the falling of the word line WL is secured, and the gate width is smaller than this XTR! RS-SW or SS-SW is provided to reduce the influence of disturb on unselected memory cells. . That is, the magnitude relationship can be opposite to that of the general configuration described above.
  • the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it.
  • the transistor size of the reset switch RS-SW or set switch SS-SW can be reduced, the reliability of the phase change memory can be improved with a small circuit area.
  • FIG. 12 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
  • the semiconductor integrated circuit device shown in FIG. 12 includes a memory array unit AR Yb, an X-system address decoder X-DECb, a Y-system address decoder Y-DECb, and a read / write circuit RWCb.
  • the configuration example shown in FIG. 12 is a modification of the configuration example shown in FIG. 10 described in the third embodiment, and the following description will be made with a focus on differences from the configuration example shown in FIG.
  • ARYb and Y-DECb shown in FIG. 12 have the same configuration as ARYa and Y-DECa shown in FIG. X-DECb in Fig. 12 differs from X-DECa in Fig. 10 in the configuration of the FX driver, and is otherwise the same. That is, the FX driver FXDR in Fig. 10 is a driver that outputs two values of the power supply voltage VDD or ground GND, whereas the FX driver FXbDR in Fig. 12 has the power supply voltage for setting VWset or the power supply voltage for resetting VW rst or It is a driver that outputs three values of ground GND.
  • the output voltage FXO of FXbDR becomes VWset corresponding to the control signal FXSET, becomes VWrst corresponding to the control signal FXRST, and becomes ground GND corresponding to the control signal FXB.
  • This output voltage FXO is supplied to the sub word line dry DR as in FIG. 10, and when the main word line MWL is selected, the sub word line SWL is driven via the word line drive transistor XTR in the XDR. Voltage.
  • the read' write circuit RWCb shown in Fig. 12 has a write transistor controlled by the write control signal WT.
  • the configuration includes a star WTR, a read transistor RTR controlled by a read control signal RD, and a sense amplifier SA.
  • the RWCb in Figure 12 is different from the RWCa in Figure 10 in that it has a switch and current source for reset operation and a switch and current source for set operation. It is characterized by having a source Vw t.
  • the WTR is composed of, for example, a MOS transistor.
  • the rise time Z fall time of the bit line during the write operation is increased by lowering the drive capability of the WTR.
  • the gate width of the WTR is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.
  • FIG. 13 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.
  • the operation of FIG. 13 differs from the operation of FIG. 11 in that the drive voltage of the sub word line is changed by the set operation and the reset operation.
  • RESET reset operation
  • WTR is turned on by the write control signal WT and the bit line connection transistor YTRO in the bit line selection switch YSO is turned on.
  • supply voltage Vwt to BLO.
  • the rise time of BLO becomes long. Therefore, for example, the current IcelnO flowing through the storage element RnO of the memory cell MCnO connected to the same bit line BLO can be reduced.
  • control signal FXRST and the main word line MWL1 for the FX driver FXbDRl are selected, and the control signal FXB is deselected to start up the sub word line SWLO.
  • the reset power supply voltage VWrst is output by FXbDRl, and this voltage becomes the drive voltage of the sub word line SWLO via the lead line drive transistor XTR.
  • FXRST and MWL1 are deselected and SWLO is lowered by selecting the control signal FXB.
  • each transistor in the sub word line dry transistor XDRO including the word line drive transistor XTR is designed to have high drive capability, and SWLO can be rapidly lowered.
  • the storage element ROO is rapidly cooled to be in an amorphous state.
  • WTR and YTR Turn off 0 to bring down BLO.
  • the fall time of the BLO is long because the drive capability of the WTR is low. Therefore, for example, the current IcelnO flowing through the storage element RnO can be reduced.
  • the read transistor RTR is turned on by the read control signal RD, and the bit line connection transistor YTRO is turned on to select the bit line BLO and read to the BLO. Apply voltage Vrd.
  • the sub word line SW LO is raised using the control signal FXRST, for example, as in the reset operation.
  • the storage element ROO generates a discharge corresponding to its state, and the difference in the discharge state is sensed and amplified by the sense amplifier SA.
  • the sub-word line SWLO is lowered and the read transistors RTR and YTR 0 are turned off.
  • the gate width of the write transistor WTR is designed to be smaller than that of the bit line connection transistor YTRO, so that the read operation can be performed at high speed.
  • the disturbance to unselected memory cells during reset operation or set operation can be reduced.
  • the write circuit is shared between the set operation and the reset operation by changing the drive voltage of the sub word line SWL, the circuit area can be further reduced compared to the configuration example of FIG. It becomes possible.
  • the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it. Further, the circuit area can be further reduced as compared with the semiconductor integrated circuit device of the third embodiment.
  • FIG. 14 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the fifth embodiment of the present invention.
  • the memory cell MC of FIG. 14 includes a diode D in addition to a selection element SW and a storage element (phase change element) scale.
  • the selection element SW is, for example, an NMOS transistor, and has a gate connected to the word line WL, a source connected to the source line SL, and a drain connected to one end of the phase change element R.
  • the other end of phase change element R is connected to the force sword of diode D, and the anode of diode D is connected to bit line BL.
  • the diode D can be formed using a diffusion layer, for example.
  • FIG. 15 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the sixth embodiment of the present invention.
  • the memory cell MC shown in FIG. 15 includes two selection elements SWa and SWb, and a storage element change element (R) connected therebetween.
  • the selection elements S Wa and SWb are, for example, NMOS transistors.
  • SWa has a gate connected to word line WL, a drain connected to bit line BL, and a source connected to one end of phase change element R.
  • the SWb has a gate connected to word line WL, a drain connected to the other end of phase change element R, and a source connected to source line SL.
  • the selection element SWa is designed to have a threshold voltage lower than that of the selection element SWb, and the leakage current is large, but it has sufficient driving force. Therefore, the current flow during writing is actually adjusted by the SWb design.
  • the semiconductor integrated circuit device of the present invention is a high-density integrated memory circuit including memory cells using a phase change material, or a logic mixed memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate. It is even more useful when such products are used under high temperature conditions.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

Si l'élément à changement de phase dans une cellule mémoire formée à l'intersection, par exemple, d'une ligne de mots (WL0) et d'une ligne de bits (BL0) doit être réinitialisé de façon à mettre l'élément à changement de phase à l'état amorphe, il est fait en sorte que les temps de montée et de descente (trb, tfb) de la ligne de bits (BL0) soient plus longs que les temps de montée et de descente (trw, tfw) de la ligne de mots (WL0). Le changement d'état de l'élément à changement de phase requis pour cette réinitialisation est réalisé en utilisant le temps de descente (tfw) de la ligne de mots (WL0). De cette manière, il est possible de limiter un courant parasite (IBL01) pour l'élément à changement de phase dans une cellule mémoire non sélectionnée qui est formée à l'intersection de la ligne de bits (BL0) et d'une ligne de mots (WL1), améliorant de ce fait la fiabilité de la mémoire à changement de phase.
PCT/JP2006/318481 2006-09-19 2006-09-19 Dispositif de circuit intégré à semi-conducteur WO2008035392A1 (fr)

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JP2009252253A (ja) * 2008-04-01 2009-10-29 Renesas Technology Corp 半導体装置
WO2010041325A1 (fr) * 2008-10-09 2010-04-15 株式会社 東芝 Mémoire à résistance variable de type points de croisement
WO2011004448A1 (fr) * 2009-07-06 2011-01-13 株式会社日立製作所 Dispositif d’enregistrement semi-conducteur et son procédé de fabrication
CN102543170A (zh) * 2012-02-17 2012-07-04 北京时代全芯科技有限公司 一种实现相变存储器低功耗的方法
JP2012212477A (ja) * 2011-03-30 2012-11-01 Toshiba Corp 抵抗変化メモリ
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JP2020155166A (ja) * 2019-03-19 2020-09-24 株式会社東芝 抵抗変化型メモリ及びその駆動方法
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TWI873720B (zh) * 2022-07-15 2025-02-21 新加坡商發明創新暨合作實驗室有限公司 半導體記憶體結構

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WO2005112118A1 (fr) * 2004-05-14 2005-11-24 Renesas Technology Corp. Mémoire de semi-conducteur
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JP2009252253A (ja) * 2008-04-01 2009-10-29 Renesas Technology Corp 半導体装置
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WO2010041325A1 (fr) * 2008-10-09 2010-04-15 株式会社 東芝 Mémoire à résistance variable de type points de croisement
JP5198573B2 (ja) * 2008-10-09 2013-05-15 株式会社東芝 クロスポイント型抵抗変化メモリ
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TWI413120B (zh) * 2008-10-09 2013-10-21 Toshiba Kk Resistance change memory
WO2011004448A1 (fr) * 2009-07-06 2011-01-13 株式会社日立製作所 Dispositif d’enregistrement semi-conducteur et son procédé de fabrication
JP2012212477A (ja) * 2011-03-30 2012-11-01 Toshiba Corp 抵抗変化メモリ
US8760942B2 (en) 2012-02-14 2014-06-24 Samsung Electronics Co., Ltd. Resistive memory device capable of blocking a current flowing through a memory cell for fast quenching
CN102543170A (zh) * 2012-02-17 2012-07-04 北京时代全芯科技有限公司 一种实现相变存储器低功耗的方法
CN102543170B (zh) * 2012-02-17 2014-10-29 北京时代全芯科技有限公司 一种实现相变存储器低功耗的方法
JP2020155166A (ja) * 2019-03-19 2020-09-24 株式会社東芝 抵抗変化型メモリ及びその駆動方法
US10923190B2 (en) 2019-03-22 2021-02-16 Toshiba Memory Corporation Memory device
TWI873720B (zh) * 2022-07-15 2025-02-21 新加坡商發明創新暨合作實驗室有限公司 半導體記憶體結構

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