WO2008026545A1

WO2008026545A1 - Moving image encoding system, switching apparatus and video encoder

Info

Publication number: WO2008026545A1
Application number: PCT/JP2007/066561
Authority: WO
Inventors: Maiko Taruki; Masatoshi Matsuo; Ikuo Fuchigami
Original assignee: Panasonic Corporation
Priority date: 2006-08-28
Filing date: 2007-08-27
Publication date: 2008-03-06

Abstract

A plurality of image signals generated by a plurality of cameras are switched by a switching apparatus and then outputted to a video encoder. The video encoder has an input interface, which comprises a synchronization signal input part and an image signal input part. The switching apparatus stores the image signals from the cameras into a plurality of buffers and then switches buffers, which are to be read, to output the image signals to the image signal input part of the video encoder. In addition, the switching apparatus outputs a switching control signal, which is indicative of timings at which the image signals are switched, to the synchronization signal input part of the video encoder. The video encoder then distinguishes, based on the switching control signal, the image signals inputted to the image signal input part to encode the image signals.

Description

Specification

Video coding system, switching device, video encoder

[0001] The present invention relates to a moving image encoding system that inputs image signals from a plurality of cameras to one input interface of a video encoder and encodes them.

Background art

A technique for compressing and transmitting image signals of a plurality of cameras for each camera is used particularly for surveillance camera systems and the like. Patent Document 1 listed below discloses an image processing system including a plurality of cameras and a video encoder corresponding to each camera on a one-to-one basis. In recent years, as the performance of video encoders has improved, it has become possible to encode images from a plurality of cameras with a single video encoder. However, in general, if the same number of input interfaces as the number of cameras is provided on the video encoder side (a set of synchronization signal input terminals and image signal input terminals), an increase in the number of pins is unavoidable, and the circuit scale Must be large. For this reason, the number of input interfaces provided in a video encoder is often smaller than the number of cameras.

[0003] Therefore, a switching device is provided outside the video encoder, and an image signal input to one input interface of the video encoder is switched at a predetermined cycle by the switching device, thereby encoding image signals of a plurality of cameras. Is going.

For example, in Patent Document 2 below, the camera is sequentially switched during the vertical blanking period by the switching circuit operating based on the vertical synchronization signal. In Patent Document 3, a camera designation signal superimposing circuit is provided to indicate which camera the image signal is, and an image pattern for identifying the camera is superimposed on the vertical blanking period of the image signal. .

Patent Document 1: Japanese Patent Publication No. 2003-101992

Patent Document 2: Japan Patent Publication No. 2003 230076

Patent Document 3: Japanese Patent Laid-Open No. 9 266571

Disclosure of the invention Problems to be solved by the invention

[0004] When a plurality of image signals are input to one input interface of the video encoder, in order to encode each image signal, each image signal is distinguished after being input to one input interface. It must be possible. In Patent Document 2, the switching order of cameras is determined in advance, and each image signal is distinguished by managing the synchronization timing of each camera or separating the vertical synchronization signal from the input image signal. In Patent Document 3, the image pattern for identifying the camera is superimposed on the vertical blanking period of the image signal as described above, and the image pattern superimposed on the blanking period is detected on the image signal receiving side. The above distinction is made.

As described above, the techniques described in Patent Documents 2 and 3 all distinguish image signals based on the vertical blanking period and the vertical synchronization signal. Therefore, each image signal is taken into the video encoder in units of frames or fields and stored in a memory such as a buffer. Then, even if the number of lines that is the minimum unit of encoding is smaller than the number of lines that make up one frame or one field, the image signal for one frame or one field is not stored in memory once. The video encoder cannot start encoding the image signal. As a result, a delay occurs in frame units or field units.

[0006] Therefore, in the present invention, when a plurality of image signals are input to one input interface of the video encoder, each image signal is distinguished and encoded, and the image signal is converted into a frame or field unit. Video encoding system, method, switching device, video encoder, integrated circuit, program, which enables faster start of encoding by handling in smaller units, thereby reducing the delay compared to conventional units Means to solve the problem

In order to solve the above problems, the present invention provides a moving image encoding system for encoding a plurality of moving images, and a signal receiving means for receiving image signals generated by imaging by a plurality of cameras. And a temporary storage means for storing a plurality of image signals received by the signal receiving means, and a plurality of image signals are cyclically switched for each camera so as to perform image encoding. Image signals for a predetermined number of lines consisting of the number of lines as a small unit or a multiple of the number of lines are read out from the temporary storage means and output, and a switching control signal indicating the timing at which the plurality of image signals are switched is generated. Output control means and encoding means, and the encoding means includes one input interface comprising a synchronization signal input part and one image signal input part, and is switched by the output control means. Each of the output image signals for the predetermined number of lines and the switching control signal are received by the one input interface, and each of the received image signals for the predetermined number of lines is indicated in the switching control signal. The video encoding system is characterized in that encoding is performed in accordance with the timing.

The invention's effect

Here, it is assumed that the “predetermined number of lines” is a number smaller than the number of lines constituting one field.

In the moving picture coding system having the above-described configuration, each picture signal is cyclically switched every time a predetermined number of lines are outputted and outputted to the coding means. A switching control signal indicating the timing at which the image signal is switched is output from the output control means to the encoding means. Here, the order of the circulation is usually known in the encoding means. Therefore, the encoding means can detect the timing at which the image signal is switched based on the switching control signal. In other words, in the above-described configuration, the encoding unit can detect that the image signal is switched every time the image signal is received for the predetermined number of lines, and thereby can distinguish each image signal.

Therefore, according to the configuration described above, the encoding means can distinguish each image signal every time it receives image signals for a predetermined number of lines, so that each image signal is represented by a line smaller than the field. Numbers can be imported as units. As a result, the start of encoding can be made earlier than in the prior art, and the delay can be reduced compared to the prior art.

In the above configuration, the input interface includes a synchronization signal input unit and one image signal input unit, and such an input interface is provided in any encoding means (for example, a video encoder). is there. Therefore, the above-described configuration can be achieved without any special modification such as adding a pin or the like to the input interface in the encoding means. It is possible to realize switching of image signals in units of lines.

[0010] Further, in the above configuration, an image signal is captured every predetermined number of lines, but this is the minimum unit of image signal encoding or a multiple thereof, so that overhead associated with switching of image signals is reduced. Thus, encoding can be performed efficiently.

In addition, the above-described moving image coding system is roughly divided into a switching device and a video encoder. Therefore, the present invention is a switching device that switches a plurality of moving images and outputs the same to one input interface comprising a synchronization signal input unit and one image signal input unit of a video encoder. A signal receiving means for receiving image signals generated by imaging for a plurality of cameras, a temporary storage means for storing a plurality of image signals received by the signal receiving means, and a plurality of image signals cyclically for each camera. The image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or a multiple of the number of lines is read out from the temporary storage means and output to the one input interface, and the plurality of images Output control means for generating a switching control signal indicating the timing at which the signal is switched and outputting the switching control signal to the first input interface. It is also a switching device to.

[0011] In such a switching device, the following may be performed.

That is, the plurality of image signals are generated synchronously at a timing according to a predetermined synchronization signal composed of a vertical synchronization signal and a horizontal synchronization signal, and the output control means has a timing based on the predetermined horizontal synchronization signal. Thus, the image signal may be switched and output.

In the above-described configuration, each image signal is generated synchronously. Therefore, it is possible to switch the image signal at the timing based on the synchronization signal of 1, and the processing is simplified.

Yes

[0012] Here, specifically, the output control means detects data based on the predetermined horizontal synchronizing signal that the image signal for the predetermined number of lines has been received by the signal receiving means. The control unit cyclically transmits the image signals for the predetermined number of lines stored in the temporary storage means within a period required for receiving the image signals corresponding to the predetermined number of lines for each detection. Buffer selection control to read and output to each It is good to include.

[0013] According to the configuration described above, every time a signal for a predetermined number of lines is received, the image signal is read cyclically and each image signal is output for the predetermined number of lines, so that the video encoder is excellent in real time. Encoding processing can be performed.

In such a configuration, the temporary storage means is a plurality of FIFO type buffer memories provided corresponding to each image signal, and each of the buffer memories includes two storage units, and the temporary storage means Each of the image signals received by the signal receiving means is stored in a corresponding buffer memory, and each of the buffer memories is selectively switched between the two storage units, and the received image signal is one of them. Is written and stored, and the data capture control unit switches the storage unit every time it detects that the signal reception unit has received the image signals for the predetermined number of lines, and performs the buffer selection control. The image signal from the one of the two storage units that has already been written for the predetermined number of lines. You may want to and be carried out of the read-out.

[0014] This eliminates the need for memory address management in the temporary storage means and simplifies the processing. In this case, each of the two storage units constituting the buffer memory writes an image signal in one of them and reads an image signal from the other in a certain period. Therefore, each storage unit has a sufficient storage capacity if it can store a predetermined number of lines of image signals. Therefore, it is possible to reduce the size of a circuit or switching device that does not need to have a storage capacity sufficient to store an image signal for one field or one frame.

Here, each camera performs imaging in synchronization with the timing indicated by the synchronization signal output from one of the cameras, and the output control means inputs the synchronization signal output from the one camera. A synchronization signal input unit is included, and the predetermined synchronization signal may be a synchronization signal received by the synchronization signal input unit.

According to this, since the synchronization signal of 1 camera is received and the switching is performed based on this synchronization signal, an output unit for outputting the synchronization signal to the camera on the switching device side, etc. It is necessary to provide [0016] It should be noted that the number of lines as the minimum unit of image encoding is preferably the number of lines for a macroblock.

As a result, the number of lines for the macroblock can be encoded as a unit.

Further, the present invention is a video in which a plurality of image signals switched and output by a switching device are received by one input interface including a synchronization signal input unit and one image signal input unit, and each image signal is encoded. An encoder comprising the input interface of 1

Each of the image signals switched and output every predetermined number of lines by the switching device and a switching control signal indicating the switching timing of the image signal are received by the image signal input unit and the synchronization signal input unit. The video encoder further comprises encoding means for distinguishing and encoding each received image signal according to the timing indicated by the switching control signal.

[0017] In such a video encoder, the following may be performed.

That is, the encoding means may encode the image signal for the predetermined number of lines received each time the switching timing indicated by the switching control signal is reached. Coding can be started by receiving line-by-line image signals, and delay can be reduced.

[0018] In such a configuration, the image signal is stored in one memory area having a storage area for storing a predetermined number of lines of image signals in the video encoder! Each of the image signals is stored in a different memory area, and the encoding means generates an interrupt at each switching timing indicated by the switching control signal to perform reception processing of the image signal, and the predetermined line When the image signals for several minutes are received, the reception process is ended, and the memory area for storing the image signals is switched at each switching timing.

[0019] Thereby, since the memory area is different for each image signal, each image signal can be distinguished by referring to the memory area.

In the above-described configuration, the image signal is cyclically switched. However, the present invention is as follows. That is, the present invention is a moving image encoding system that encodes a plurality of moving images, and includes a signal receiving unit that receives image signals generated by imaging by a plurality of cameras and the signal receiving unit. Temporary storage means for storing a plurality of image signals, and switching a plurality of image signals for each camera, and images corresponding to a predetermined number of lines composed of the number of lines as a minimum unit of image encoding or a multiple of the number of lines. A signal is read from the temporary storage means, a set of the read image signal and an additional signal for identifying the image signal is output, and a superposition timing signal for distinguishing the additional signal from the image signal is generated. Output control means and encoding means, and the encoding means includes one input interface comprising a synchronization signal input section and one image signal input section. Each of the predetermined number of image signals switched and output by the output control means, the additional signal, and the superimposition timing signal are received by the input interface of 1, and the received number of the predetermined lines. The image signal and the additional signal are distinguished from each other by the received superposition timing signal, and the received image signals for the predetermined number of lines are identified by using the additional signal, thereby distinguishing each of the image signals. This is a video encoding system characterized by encoding.

[0020] According to the configuration described above, the output control means outputs the additional signal for identifying each image signal together with the image signal. In the encoding means, the additional signal and the image signal can be distinguished from each other by the superposition timing signal, and the image signal can be identified based on the additional signal. Therefore, even if the image signals are not generated synchronously, each image signal can be identified by the additional signal. Therefore, the encoding means is provided when a plurality of image signals are input to one input interface. In addition, even if the image signals are not generated synchronously, the image signals can be distinguished and encoded in units of lines. Further, it is not necessary to add a new pin or the like to the input interface.

[0021] This moving image coding system is also roughly divided into a switching device and a video encoder. Therefore, the present invention is a switching device that switches a plurality of moving images and outputs them to one input interface comprising a synchronization signal input unit and one image signal input unit of a video encoder. Signal receiving means for receiving generated image signals for a plurality of cameras, and storing a plurality of image signals received by the signal receiving means The temporary storage means and a plurality of image signals are switched on a camera-by-camera basis, and image signals for a predetermined number of lines consisting of the minimum number of lines for image coding or a multiple of the number of lines are read from the temporary storage means. And outputting a set of the read image signal and an additional signal for identifying the image signal to the input interface 1 and generating a superposition timing signal for distinguishing the additional signal from the image signal. It is also a switching device comprising output control means for outputting to one input interface.

[0022] In such a switching device! /, The following should be done! /.

That is, the output control means includes a synchronization signal receiving unit that receives a synchronization signal for generating an image signal for each of the image signals, and based on each of the synchronization signals received by the synchronization signal receiving unit! / The switching output of the set of the image signal and the additional signal and the output of the superimposition timing signal may be performed. Specifically, the output control means outputs the image signals for the predetermined number of lines for each of the plurality of image signals based on the horizontal synchronization signals of the respective synchronization signals received by the synchronization signal receiving unit. A data capturing control unit that detects that the signal has been received by the signal receiving unit, an additional information generating unit that generates an additional signal, and image signals for a predetermined number of lines in the order detected by the data capturing control unit. It is preferable to include a selection unit that reads out from the temporary storage means and outputs the read image signals for a predetermined number of lines and the additional signal generated by the additional information generation unit for the image signal.

[0023] According to the configuration described above, the switching device detects, for each image signal, the reception of the image signals for a predetermined number of lines based on the horizontal synchronization signal of the image signals, and the images are sequentially detected. Since the signals are switched and output, image signals can be output even when the image signals are asynchronous. In addition, even if the image signal data amount differs because each image signal has a different image size, each image signal is output even if the line size or image size of the image signal is different, because they are output in the order of detection. can do.

[0024] The additional signal may include identification information of an image signal. Further, the additional signal includes at least one of macro block line information indicating which line in the image of the image signal is one line, or line size information indicating the size of one line. And as good.

As a result, the video encoder can acquire which line of the image the image signal corresponds to by the additional signal, so the video encoder receives each image signal, for example, up to which line. This eliminates the need to manage these and simplifies processing on the video encoder side.

[0025] Further, according to the present invention, a plurality of image signals that are switched and output by the switching device are received by one input interface including a synchronization signal input unit and one image signal input unit, and each image signal is encoded. A video encoder including the input interface of 1 and a set of each of the image signals switched and output every predetermined number of lines by the switching device, and an additional signal for identifying the image signal, and The superimposition timing signal for distinguishing the additional signal from the image signal is received by the input interface of 1 and the received image signal and the additional signal for the predetermined line are received. Each image signal is distinguished by identifying the received image signal for the predetermined line using the additional signal. Is also a video encoder, characterized in that it comprises coding means for No. of.

[0026] The present invention also provides a video encoder having one input interface comprising a synchronization signal input unit and one image signal input unit, and a plurality of moving images switched to the one input interface for output. A moving image encoding method for encoding a plurality of moving images in a moving image encoding system including a switching device, the signal receiving step for receiving image signals generated by imaging of a camera for a plurality of cameras, and the signal The temporary storage step of storing a plurality of image signals received by the reception step by the temporary storage means of the switching device, and the number of lines as a minimum unit of image encoding by cyclically switching the plurality of image signals for each camera. Alternatively, a predetermined number of lines of image signals consisting of multiples of the lines are read out from the temporary storage means and output, and An output control step for generating and outputting a switching control signal indicating the timing at which the image signal is switched, and the switching control signal for each of the predetermined number of image signals to be switched and output by the output control step. Each of the received image signals is distinguished by the timing indicated by the switching control signal. And a coding step for coding.

[0027] Further, the present invention provides a video encoder having one input interface including a synchronization signal input unit and one image signal input unit, and a plurality of moving images switched to the one input interface for output. A moving image encoding method for encoding a plurality of moving images in a moving image encoding system including a switching device, the signal receiving step for receiving image signals generated by imaging of a camera for a plurality of cameras, and the signal A temporary storage step for storing a plurality of image signals received by the reception step by the temporary storage means of the switching device; and a number of lines or a multiple thereof as a minimum unit for image encoding by switching the plurality of image signals for each camera. A predetermined number of image signals consisting of the number of lines is read from the temporary storage means, and the read image signal and the image signal are A pair of additional signals for separation is output, and an output control step for generating and outputting a superimposition timing signal for distinguishing between the additional signal and the image signal, and switching output by the output control step are output. Each of the image signals for the predetermined number of lines, the additional signal, and the superposition timing signal are received by the input interface of 1, and the received image signals for the predetermined number of lines and the additional signal are received. An encoding step of distinguishing and encoding each of the image signals by identifying the received image signals for the predetermined number of lines using the additional signal. It is also a featured video encoding method.

[0028] Further, the present invention is an integrated circuit used in a switching device that switches a plurality of moving images and outputs to a single input interface including a synchronization signal input unit and a single image signal input unit of a video encoder. A signal receiving unit for receiving image signals generated by imaging by a plurality of cameras, a temporary storage unit for storing a plurality of image signals received by the signal receiving unit, and a plurality of image signals for each camera. The image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or a multiple of the number of lines is read out from the temporary storage unit and output to the input interface 1. An output control unit that generates a switching control signal indicating a timing at which the plurality of image signals are switched and outputs the switching control signal to the first input interface. It is also the integrated circuit that features and. [0029] Further, according to the present invention, a plurality of image signals that are switched and output by the switching device are received by one input interface including a synchronization signal input unit and one image signal input unit, and each image signal is encoded. Each of the image signals received by the input interface and switched by the switching device every predetermined number of lines and output from the switching device. It is also an integrated circuit characterized by including an encoding unit that distinguishes and encodes by a switching control signal indicating the switching timing of an image signal received by one input interface.

[0030] Further, the present invention is an integrated circuit used in a switching device that switches a plurality of moving images and outputs to a single input interface including a synchronization signal input unit and a single image signal input unit of a video encoder. A signal receiving unit for receiving image signals generated by imaging by a plurality of cameras, a temporary storage unit for storing a plurality of image signals received by the signal receiving unit, and a plurality of image signals for each camera. In order to distinguish between the read image signal and the image signal by reading from the temporary storage unit the image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or a multiple of the number of lines. Are output to the input interface 1 and a superposition timing signal for distinguishing the additional signal from the image signal is generated to generate the superposition timing signal. And an output control unit that outputs to one input interface.

[0031] Further, according to the present invention, a plurality of image signals switched and output by the switching device are received by one input interface including a synchronization signal input unit and one image signal input unit, and each image signal is encoded. An integrated circuit used in a video encoder for identifying an image signal for each image signal that is switched and output every predetermined number of lines and received by the one input interface. The additional signal and a superimposition timing signal for distinguishing the additional signal and the image signal are used to distinguish the additional signal from the predetermined number of lines of the image signal by the superimposition timing signal, and An integrated circuit comprising: an encoding unit that distinguishes and encodes each image signal by identifying the image signal using the additional signal. But there is.

[0032] Further, the present invention switches a plurality of moving images, and switches a process of outputting to one input interface including a synchronization signal input unit and one image signal input unit of the video encoder. A control program for causing the apparatus to perform a signal reception step of receiving image signals generated by imaging of a camera for a plurality of cameras, and a plurality of image signals received by the signal reception step to temporarily store the switching device. A temporary storage step to be stored in the storage means and a plurality of image signals are switched cyclically for each camera, and a predetermined number of lines consisting of the number of lines that are the minimum unit of image encoding or a multiple of the number of lines. An output control step of reading out an image signal from the temporary storage means and outputting the image signal to the first input interface, and generating a switching control signal indicating timing at which the plurality of image signals are switched and outputting the switching control signal to the first input interface; It is also a control program characterized by including.

[0033] Further, according to the present invention, a plurality of image signals that are switched and output by a switching device to a video encoder having one input interface including a synchronization signal input unit and one image signal input unit are output to the 1 A control program for performing a process of encoding each image signal by being received by the input interface, and is output by being switched by the switching device every predetermined number of lines and received by the input interface of 1. And a coding step of distinguishing and coding each image signal by a switching control signal indicating the switching timing of the image signal, which is output from the switching device and received by the input interface of 1. It is also a control program.

[0034] Further, the present invention allows a switching device to perform a process of switching a plurality of moving images and outputting to one input interface including a synchronization signal input unit and one image signal input unit of a video encoder. And a signal receiving step for receiving image signals generated by imaging by a plurality of cameras, and a plurality of image signals received by the signal receiving step are stored in a temporary storage unit of the switching device. Temporary storage step and switching a plurality of image signals for each camera, and reading out from the temporary storage means image signals for a predetermined number of lines consisting of the number of lines as a minimum unit of image encoding or a multiple of the number of lines. A set of the read image signal and an additional signal for identifying the image signal is output to the input interface 1 described above. It is also a control program, characterized in that it comprises an output control step of generating a superimposed timing signal for discriminating the additional signal and the image signal output to the first input interface. [0035] Further, according to the present invention, a plurality of image signals that are switched and output by a switching device to a video encoder having one input interface including a synchronization signal input unit and one image signal input unit are output to the 1 A control program for performing processing for encoding each image signal received by the input interface of the image signal, the image signal being switched and output every predetermined number of lines by the switching device, and the predetermined number of lines A combination of an additional signal for identifying the image signal and a superimposition timing signal for distinguishing the additional signal from the image signal for the predetermined number of lines are received by the input interface of 1 and received. The predetermined number of lines of image signals and the additional signal are distinguished by the received superimposition timing signal, and the received images of the predetermined number of lines are received. No. and by identifying using said additional signal is also a control program characterized in that it comprises a coding stearyl-up for encoding and distinguish each of the image signals.

Brief Description of Drawings

FIG. 1 is a functional block diagram showing a configuration of a moving picture coding system 100 according to a first embodiment.

FIG. 2 is a diagram showing a detailed configuration of a control circuit 6.

FIG. 3 is a flowchart showing processing performed by an interrupt handler in processor 13

Yes

FIG. 4 is a timing chart showing the operation of the video encoding system 100.

FIG. 5 is a diagram showing the start timing of encoding processing in the video encoder 3;

FIG. 6 is a functional block diagram showing a configuration of a moving picture coding system 200 according to Embodiment 2.

FIG. 7 is a diagram showing a detailed configuration of a control circuit 56.

FIG. 8 is a diagram showing V-SYNC9 and H-SYNC10 output by a synchronization signal generation unit 73.

FIG. 9 is a flowchart showing processing performed by an interrupt handler in processor 13 in the second embodiment.

FIG. 10 is a timing chart showing the operation of the video encoding system 200.

FIG. 11 is a diagram showing the start timing of the encoding process in the video encoder 53.

FIG. 12 is a diagram showing a configuration of a moving picture coding system 300 according to Embodiment 3 of the present invention. is there.

Explanation of symbols

100 video encoding system la, lb, lc, ID camera

2 Switching device

4 Sync signal

5a, 5b, 5c, 5α

6 Control circuit

7 Selection circuit

8 Camera input section

9 V- SYNC

10 H-SYNC

11 DATA

12 Interrupt controller

13 processor

14 Data transfer section

15 Image encoder

16 memory

17 Input image area

18 Encoded data area

19a, 19b, 19c, 19d Image signal

22 Interrupt signal

31 Camera data capture controller

32 Noffer selection control section

33 Sync signal generator

34 counter

200 Video coding system 51 a, 51b, 51c, 51d camera

52

53 Video encoder

55

56 Control circuit

58 Image switching section

71 a Camera # 0 Data acquisition controller

71b Camera # 1 data acquisition controller

71c Camera # 2 Data acquisition control unit

71 d Camera # 3 Data acquisition control unit

72 Buffer selection controller

73 Sync signal generator

74 counter

75 Additional information generator

81 Camera identification number information

82 Macroblock line information

83 Line size information

300 Video coding system

91 a, 91b, 91c, 91d camera

92 Encoder device

93

94 Network

95

96 coater equipment

97 Moyuta

BEST MODE FOR CARRYING OUT THE INVENTION

1 Embodiment 1

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a moving image coding system that is effective in the present invention will be described with reference to the drawings. 1.1 Configuration

FIG. 1 is a functional block diagram showing the configuration of the moving picture coding system 100 according to the first embodiment.

As shown in FIG. 1, the moving picture coding system 100 includes a plurality of cameras (cameras la, lb, lc, and Id), a switching device 2, and a video encoder 3. The cameras la, lb, lc, and ld (hereinafter, cameras la, lb, lc, and Id may be collectively referred to as “camera 1”), the switching device 2, and the video encoder 3 will be described in order.

1. 1. 1 Camera 1

Camera 1 captures image signals 19a, 19b, 19c, 19d (hereinafter image signals 19a, 19b, 1

9c and 19d are collectively referred to as “image signal 19”), and the generated image signal 19 is output. The image signal 19 generated by the camera 1 is output to the switching device 2.

[0040] Each of the cameras la, lb, lc, and Id outputs image signals 19a, 19b, 19c, and 19d in synchronization with each other. For example, one of the cameras 1 (for example, camera la) outputs the synchronization signal 4 (vertical synchronization signal and horizontal synchronization signal) to the other camera and the switching device 2, and the other camera It receives synchronization signal 4 output from the camera and operates in synchronization with this synchronization signal 4. In addition, the image sizes of the moving images taken by the cameras la, lb, lc, and Id are assumed to be the same in the cameras la, 1b, lc, and Id.

[0041] 1. 1. 2 Switching device 2

The switching device 2 receives the image signal 19 from the camera 1 and outputs the received image signal 19 to the input interface of the video encoder 3 (image signal and synchronization signal input terminal).

Note that image signals from a plurality of cameras are input to the input interface 1 of the video encoder 3. In this embodiment, four image signals generated by the four cameras la, lb, lc, and Id are input to one input interface of the video encoder 3. Therefore, the switching device 2 sequentially switches a plurality of image signals received from the camera 1 and outputs them to the video encoder 3. At this time, the switching device 2 switches the output image signal every time it outputs an image signal of 16 lines (hereinafter referred to as “macro-block line”). The macroblock line is the number of lines that are the minimum unit of encoding by the video encoder 3.

As shown in FIG. 1, the switching device 2 includes buffers 5a, 5b, 5c, 5d (hereinafter referred to as buffers 5a, 5b,

5c and 5d are collectively referred to as “buffer 5”), a control circuit 6 and a selection circuit 7.

1. 1. 2. 1 Noffer 5

The notfer 5 is a FIFO (First In First Out) type buffer memory that temporarily stores the image signal 19 output from the camera 1. As shown in the figure, notches 5a, 5b, 5c, and 5d are provided corresponding to the cameras la, lb, lc, and Id, respectively. The image signals 19a, 19b, 19c, and 19d output from the cameras l a, lb, lc, and Id force are recorded in the corresponding buffers 5a, 5b, 5c, and 5d.

[0043] Also, it is assumed that the buffers 5a, 5b, 5c, and 5d each include two buffer memories that can store image signals of macroblock lines. Of the two buffer memories, at one timing, one is used for storing the image signal 19 from the camera 1 (that is, writing the image signal 19), and the other is output to the video encoder 3 (that is, the image). Used to read signal 19). Each time the image signal 19 of the macroblock line is processed, the buffer memory used for writing and the buffer memory used for reading are switched. That is, the image signal 19 is read from the buffer memory that has been written, and the image signal 19 is written to the buffer memory that has been read.

[0044] 1. 1. 2. 2 Control circuit 6

The control circuit 6 cyclically switches the buffer from which the image signal is to be read out of the buffer 5 and outputs the image signal to the video encoder 3, and the switching control signal indicating the timing at which the image signal to be output is switched. And processing for outputting a switching control signal to the synchronization signal input terminal of the video encoder. In response to the output of the switching control signal, the video encoder 3 distinguishes each image signal and captures the image signal on the assumption that the input image signal is switched.

Specifically, the control circuit 6 receives the synchronization signal 4 for synchronizing the cameras la, lb, lc, and Id from one camera, and based on this synchronization signal, receives the image signal in the buffer 5. read out Switches the target buffer in order.

FIG. 2 is a diagram showing a detailed configuration of the control circuit 6. As shown in FIG. 2, the control circuit 6 includes a camera data capture control unit 31, a buffer selection control unit 32, and a synchronization signal generation unit 33.

[0046] (Camera Data Import Control Unit 31)

The camera data capture control unit 31 controls switching between writing and reading in each buffer memory provided on the two surfaces. This switching between writing and reading is called bank switching. That is, from the state where one of the two-surface buffer memories is used for writing and the other is used for reading, the buffer memory for writing is switched to reading by switching the bank, and the buffer memory for reading is used for writing. Switch.

As shown in FIG. 2, the camera data capture control unit 31 receives the synchronization signal 4 from one camera. In Figure 2, the camera pixel clock is CAM_PCLK4p, the vertical sync signal is CAM_V_SYNC4v, and the horizontal sync signal is CAM_H_SYNC4h!

The timing at which the field switches in the image signal output from each camera can be detected by CAM_V_SYNC4v. Line switching can be detected by CAM.H-S YNC4h. Therefore, the camera data capture control unit 31 can detect field switching by CAM_V_SYNC4v, and can detect how many lines of image signals have been received by CAM_H_SYNC 4h.

[0048] When CAM_H-SYNC4h detects that switching device 2 has received a macroblock line image signal, the macroblock line image signal is stored in one of the two buffer memory surfaces of buffer 5. Therefore, bank switching is required. The camera data capture control unit 31 outputs a buffer control signal to the buffer 5 to switch the bank of the buffer 5. At this time, the buffer control signal is also output to the buffer selection control unit 32.

[0049] (Buffer selection control unit 32)

The noffer selection control unit 32 controls the selection circuit 7 by outputting a read control signal for designating a buffer to be read to the selection circuit 7, and sequentially reads out the image signal from each buffer and outputs the video encoder 3 Output to the 1 input interface. The noffer selection control unit 32 receives the buffer control signal from the camera data capture control unit 31. Accept. As a result, since the image signals of the macro block lines are stored in the notifiers 5a, 5b, 5c, and 5d, the buffer data is read out by switching the bank by the camera data capturing control unit 31. It is the power to open the reading from the buffer memory.

In the present embodiment, first, reading from the buffer 5a is performed, and then reading is performed from the buffers 5b, 5c, and 5d. After that, when a buffer control signal is received from the camera data capture control unit 31, reading from the buffer memory used for reading by bank switching is performed in order from the buffer 5a to the buffer 5b, the buffer 5c, and the buffer 5d. Let's go. That is, the order of reading image signals from the buffer 5 is determined in advance, and reading is performed cyclically. The macroblock line image signals are read out and output in order from the buffers 5a, 5b, 5c, and 5d, but this reading is completed within the period in which the switching device 2 receives the macroblock line image signals. .

[0051] Note that the buffer selection control unit 32 monitors the amount of data stored in the buffer memory, for example, starts reading the buffer 5b after the reading of the buffer 5a is completed, and reads the macroblock line from the buffer memory. A read control signal designating the buffer to be read is output to the selection circuit 7 so that the next buffer is read each time image signal reading is completed.

By the way, the output of the readout control signal means that the image signal output from the switching device 2 to the video encoder 3 is switched. Therefore, a switching control signal to be output to the video encoder 3 may be generated based on the timing at which the readout control signal is output. The buffer selection control unit 32 outputs a predetermined signal to the synchronization signal generation unit 33 at the timing of outputting the read control signal.

[0053] (Synchronization signal generator 33)

The synchronization signal generation unit 33 generates a switching control signal based on the switching timing of the image signal output from the switching device 2 to the video encoder 3 and outputs the switching control signal to the 1 input interface of the video encoder 3.

As shown in FIG. 2, the synchronization signal generation unit 33 includes a counter 34, and the counter 34 receives an input of a system clock (system CLK). Synchronization signal generator 33 When the above-mentioned predetermined signal is received from the node selection control unit 32, the buffer selection control unit 32 adjusts the number of clocks required for switching the buffer 5 to be read out to adjust the high (HI) level signal. And the output of the low (LO) level signal.

[0054] The output of the switching control signal will be specifically described. When the image signal is output to one input interface of the video encoder 3, the synchronization signal generation unit 33 is connected to the synchronization signal input terminal of the video encoder 3, that is, the vertical synchronization signal input terminal and the horizontal synchronization signal. Both output high level signals to the input terminals. When the image signal is not output, a low level signal is output. In FIG. 1, among the switching control signals, the signal output to the vertical synchronization signal input terminal of the video encoder 3 is V-SYNC9, and the signal output to the horizontal synchronization signal input terminal is H-SYNC10. .

[0055] When the buffer 5 to be read is switched by the noffer selection control unit 32, the sync signal generation unit 33 receives a predetermined signal output from the buffer selection control unit 32, and receives V-SYNC9 and H-SYNC10. Set both levels to low level. When the counter 34 counts the predetermined number of clocks required to switch the buffer to be read, the level of the output V-SYNC 9 and H-SYNC 10 is made high.

In short, the synchronization signal generation unit 33 outputs a high-level signal while the image signal is read from the buffer and output to the video encoder, and while the buffer 5 to be read is switched. Outputs a low level signal.

1. 1. 2. 3 Selection circuit 7

The selection circuit 7 receives the read control signal output from the buffer selection control unit 32 of the control circuit 6, and connects to the buffer designated as the read control signal among the buffers 5a, 5b, 5c, and 5d.

[0057] The selection circuit 7 reads an image signal from the buffer memory that is used for reading by bank switching of the connected buffer. The read image signal is output to the image signal input terminal of the video encoder 3 input interface. In FIG. 1, the signal output from the switching device 2 to the image signal input terminal of the video encoder 3 is DATA11.

1. 1. 3 Video encoder 3 The video encoder 3 receives a plurality of image signals through one input interface and encodes each received image signal. As described above, V-SYNC 9 and H-SYNC 10 are output from the switching device 2 to the input terminal of the synchronization signal of the 1 input interface of the video encoder 3. DATA11 is output to the image signal input terminal. With this V-SYNC9, the video encoder 3 distinguishes which of the cameras 1 has generated the image signal input as DATA11. Each distinct image signal is encoded.

As shown in FIG. 1, the video encoder 3 includes a camera input unit 8, a harmful ij insertion controller 12, a processor 13, a data transfer unit 14, an image encoding unit 15, and a memory 16. Prepare. The memory 16 includes an input image area 17 and an encoded data area 18.

1. 1. 3. 1 Camera input section 8

The camera input unit 8 includes a synchronization signal input terminal and an image signal input terminal, and detects switching of the image signal camera by the V-SYNC 9 and H-SYNC 10 output from the switching device 2.

[0059] Specifically, the camera input unit 8 operates in synchronization with PCLK21 which is the pixel clock of the video encoder 3, and changes from low to high of V-SYNC9 input to the vertical synchronization signal input terminal. When the edge rises, the interrupt signal 22 is output to the interrupt controller 12. In addition, DATA11 input to the image signal input terminal is temporarily recorded as fe.

1. 1. 3. 2 Harmful ij penetration controller 12

The interrupt controller 12 receives the interrupt signal 22 output from the camera input receiving means, causes the processor 13 to generate an interrupt, and activates the interrupt handler.

[0060] 1. 1. 3. 3 Processor 13

The processor 13 controls the processing of the video encoder 3 by operating based on a predetermined program. For example, the processor 13 activates an interrupt handler by the harmful ij interrupt controller 12 and performs a process of determining a storage area in the memory 16 of the image signal received by the camera input unit 8.

[0061] 1. 1. 3. 4 Data transfer unit 14 The data transfer unit 14 transfers the image signal received as DATA 11 in the camera input unit 8 to the memory 16 according to the storage area determined by the interrupt handler of the processor 13.

1. 1. 3. 5 Image encoder 15

The image encoding unit 15 encodes the image signal stored in the memory 16.

[0062] 1. 1. 3. 6 Memory 16

As shown in FIG. 1, the memory 16 includes an input image area 17 and an encoded data area 18. The memory 16 stores the image signal captured from the switching device 2 in the input image area 17 under the control of the processor 13. The encoded data obtained by encoding the image signal is stored in the encoded data area 18.

[0063] In the input image area 17 and the encoded data area 18, a storage area is predetermined and secured for each image signal. In other words, the image signal and the storage area in the memory are associated with each other! /.

1.2 Operation

Next, the operation of the moving picture coding system 100 will be described.

The operation of the switching device 2 is as described in the configuration of the control circuit 6 described above.

Therefore, the operation of the video encoder 3 will be described.

As described above, when the camera input unit 8 outputs the interrupt signal 22, the interrupt controller 12 generates an interrupt to the processor 13 and activates the interrupt handler. The interrupt handler calculates the storage area in the memory 16 of the image signal related to the generation of the interrupt signal 22.

FIG. 3 is a flowchart showing processing performed by the interrupt handler in the processor 13.

Harm | J The handler inserts cam_number and Lines from the register (step S 101). Cam_number is used to specify the camera, and Lines is used to specify the position of the image signal for the macroblock line in the image. In the register, information indicating the position of the camera and the image signal already captured by the video encoder in the image is stored as cam_number and Lines. [0066] Here, cam_number corresponds to the number of cameras, and in this embodiment, there are four cameras. Therefore, the cameras la, lb, lc, and Id are specified by four values from 0 to 3. ing. That is, if the cam-number force is “0”, it indicates the ίί camera la. Similarly, if the cam-number force is “(camera lb, cam-number force is“ 2 ”, the camera lc, cam-number force is S "3" indicates the camera Id, and the image signal is divided for each field by the vertical sync signal, so that one field is 240 lines, and in this embodiment, Lines is "1" to "15". For example, if the value read from the register by the harmful IJ handler in step S 101 is cam.number = 1, Lines = 1, the image of camera lb is 1 macroblock line (16 lines) indicates that it has already been captured, that is, in this state, the harmful IJ insertion handler sends the image signal of 16 lines of Decide which storage area to save and save.

[0067] When cam_number and Lines are read from the register, the harmful ij entry handler calculates and updates the value of cam_number (step S103). Specifically, the value of cam_number read from the register in step S101 is incremented. If the cam_number read from the register is “3”, the cam_number is set to “0.” This allows the camera of the image signal to determine the value storage area of the cam_number. It becomes corresponding

Yes

[0068] The interrupt handler calculates and updates the value of Lines (step S105). Since the image signal is cyclically switched in the order of the camera la to Id as described above, the value of Lines is updated when the value of cam_number updated in step S103 is 0 ". Specifically, the harmful ij entry handler increments the value of Lines read from the register in step S101 if the value of cam_number updated in step S105 is 0 ". When the read Lines value is “15”, that is, when the upper limit value of Lines is possible, the Lines value is updated to “1”. As a result, the value S of Lines and the position of the image signal for one macroblock whose storage area is to be determined are indicated in the image.

[0069] Based on the updated values of cam_number and Lines, the harmful ij insertion handler calculates the address range in the input image area 17 of the memory 16 (step S107). ). For example, a storage area address range is assigned to each camera, and a storage area for a predetermined number of frames is assigned to each camera. Furthermore, in the storage area for each camera, the address range of the storage area is defined in units of frames. Based on the value of Lines, an address range for storing the image signal for the macroblock line is calculated from the address range of the storage area determined in units of frames. In short, by referring to the memory address, it is preferable to be able to specify which camera the image signal corresponds to and which line of the image signal.

[0070] The harmful ij entry handler uses the address range calculated in step S107 as the data transfer unit.

Set to 14 (step S109).

Further, the interrupt handler sets information necessary for encoding the image signal in the image encoding unit 15 (step S111). The information necessary for encoding the image signal is, for example, a storage area of the encoded data area 18 after the encoding process, a frame rate, a reference image address, and the like.

[0071] In order to use the values of cam_number and Lines at the next interrupt, the harmful ij entry handler saves the values of cam_number and Lines in a register (step SI 13), and ends the interrupt. The data transfer unit 14 transfers the image signal captured by the camera input unit 8 to the address range calculated in step S107 by the harmful ij insertion handler in the input image region 17.

The image encoding unit 15 starts encoding processing when an image signal for one macroblock line is transferred to the input image area 17 by the data transfer unit 14. Based on the information set in step SI 11 by the interrupt handler, the encoding process is performed, and the encoded data after encoding is stored in the encoded data area 18. Then, in synchronization with the camera input switching timing, the image signal to be encoded is switched for each macroblock line. Similar to the case where the image signal of each camera is distinguished by the address range of the input image area 17, the encoded data after encoding is stored in the encoded data area 18 for each camera. I will do it. As a result, the encoded data after encoding can be easily distinguished for each camera.

[0073] FIG. 4 shows a timing chart of the moving picture coding system 100 that operates in this manner. In the figure, the image signals 19a, 19b, 19c, and 19d are CAM-DATA0, CAM-DATA1, CAM_DATA2, and CAM_DATA3, respectively. Cameras la, lb, lc, and Id are camera # 0, camera # 1, camera # 2, camera # 3, and the numbers below camera # 0 indicate the position of the image signal for the macroblock line in the image. Show. That is, in the figure, the number “1” under the camera # 0 etc. indicates an image signal of;! To 16 lines, and the number “2” indicates an image signal of 17 to 32 lines. This image signal is input to the camera input unit 8 as DATA11.

FIG. 5 shows the start timing of the encoding process in the video encoder 3.

As shown in FIG. 5, the image signal of each camera is input as DATA 11 in the camera input unit 8 for each macroblock line as shown in “video encoder input” in FIG. Then, the input image signal is started to be encoded as shown in “Encoding process” in FIG. In this embodiment, the video encoder 3 inputs four macro block line image signals for each camera while each camera generates a macro block line image signal. As a result, the image signal of each camera can be encoded in real time.

[0075] 1. 3 Summary

According to the above configuration, the video encoder 3 can switch and capture images from a plurality of cameras without adding a special signal line. In addition, by performing switching control with a frame size smaller than the frame unit, the buffer size can be reduced, and the coding delay can be reduced.

[0076] 2 Embodiment 2

Hereinafter, another embodiment of the moving picture coding system according to the present invention will be described.

Yes

2.1 Overview

In the present embodiment, it is assumed that the cameras are not always synchronized with each other. That is, in the first embodiment, each camera operates based on the same synchronization signal. In this embodiment, the operation is performed based on the same synchronization signal! /, ! / Also, the image size of each camera may be different. Accordingly, as in the first embodiment, the macroblock line image signals are output from the switching device 52 in the order in which each camera outputs the macroblock line image signals instead of cyclically switching the cameras. . At this time, information relating to the image signal, such as which camera generated the image signal, is output as an additional signal from the switching device 52 to the image signal input terminal of the video encoder 53 as an additional signal. Then, the superimposition timing signal is output from the switching device 52 to the synchronization signal input terminal of the video encoder 53 so that the additional signal and the image signal can be distinguished.

[0078] Note that, in the following description, differences from Embodiment 1 will be mainly described.

2.2 Configuration

FIG. 6 is a functional block diagram showing the configuration of the moving picture coding system 200 according to the second embodiment.

2.2.1 Camera 51

In the second embodiment, the cameras 51a, 51b, 51c, and 51d are not controlled to operate synchronously with each other.

[0079] Further, it is assumed that the image sizes of the moving images captured by the cameras are not the same but include different ones. For example, all cameras may record moving images of different image sizes! /, And V, some cameras may have large image sizes, moving images (some! / , Moving image) is also good.

Further, each camera outputs synchronization signals 4a, 4b, 4c, and 4d, which are output to the control circuit 56 of the switching device 52, and the synchronization signal power of each camera.

Also, as shown in FIG. 6, camera 51a is camera # 0, camera 51b is camera # 1, camera 51c is camera # 2, and camera 51d is camera # 3.

2.2.2 Switching device 52

The switching device 52 includes a buffer 55, a control circuit 56, and a selection circuit 7.

2. 2. 2. 1 Noffer 55

The koffa 55 (55a, 55b, 55c, 55d) is arranged corresponding to each camera. Each buffer is a two-sided buffer memory as in the first embodiment, but the buffer memory can store a macroblock line image signal having a line size corresponding to each camera. Let's say.

[0081] 2.2.2.2 Control circuit 56

FIG. 7 is a diagram showing a detailed configuration of the control circuit 56. As shown in FIG. 7, the control circuit 56 includes a camera # 0 data capture control unit 71a, a camera # 1 data capture control unit 71b, a camera # 2 data capture control unit 71c, and a camera # 3 data capture control unit. 71d, a buffer selection control unit 72, a synchronization signal generation unit 73, a counter 74, and an additional information generation unit 75. Hereinafter, the camera # 0 data capture control unit 71a, the camera # 1 data capture control unit 71b, the camera # 2 data capture control unit 71c, and the camera # 3 data capture control unit 71d are collectively shown. a call and power ^s referred to as a "camera # 0 data capture control unit 71a, etc.".

[0082] (Camera # 0 data capture control unit 71a, etc.)

In FIG. 7, the camera # 0 data acquisition control unit 71a corresponds to the camera # 0. The camera # 1 data acquisition control unit 71b corresponds to the camera # 1. Similarly, the camera # 2 data capture control unit 71c corresponds to the camera # 2, and the camera # 3 data capture control unit 71d corresponds to the camera # 3.

[0083] Similar to the camera data capture control unit 31 of the first embodiment, the camera # 0 data capture control unit 71a and the like store the buffer control signal in the corresponding buffer each time the image signal of the macroblock line is stored. Output and perform bank switching. At this time, the camera # 0 data capture control unit 71a and the like also output a buffer control signal to the buffer selection control unit 72. Therefore, the buffer selection control unit 72 receives buffer control signals from the camera # 0 data capture control unit 71a, the camera # 1 data capture control unit 71b, the camera # 2 data capture control unit 71c, and the camera # 3 data capture control unit 71d. .

[0084] Also, in FIG. 7, the synchronization signal 4 of each camera is used. For the camera # 0, the pixel clock 4a — p is CAM—PCLK0, the vertical synchronization signal 4a—v is CAM—V_SYNC0, and the horizontal synchronization signal 4a—h Is CAM_H-SYNCO. Similarly, for other cameras, refer to “—P” for the pixel clock, “—v” for the vertical sync signal, and “—h” for the horizontal sync signal. It is added to the reference numerals (4b, 4c, 4d).

[0085] (Buffer Selection Control Unit 72) The buffer selection control unit 72 receives buffer control signals from the camera # 0 data acquisition control unit 71a and the like. A read control signal is output to the selection circuit 7 so as to select a buffer to be output from the buffer 55 in the order received.

As in the first embodiment, the buffer selection control unit 72 monitors the amount of data stored in the buffer memory, and whenever reading of the image signal of the macroblock line from the buffer memory is completed, the buffer selection control unit 72 A read control signal is output to the selection circuit 7 by designating a buffer to be read so that reading is performed. In addition, a predetermined signal is output to the synchronization signal generation unit 73 at the timing when the read control signal is output.

It should be noted that the buffer selection control unit 72 receives the buffer control signal from each camera, and the horizontal after the camera # 0 data capture control unit 71a receives the vertical synchronization signal 4a-V from the camera. Based on the number of times the synchronization signal 4a—h is received, it is managed for each camera how many lines of the image signal in one field are input to the buffer 55. Based on the managed information, the additional information generation unit 75 generates an additional signal. Specifically, the buffer selection control unit 72 is responsive to the image signal read from the buffer 55 by the read control signal at the timing when the read control signal is output to the selection circuit 7. The additional information generation unit 75 includes information indicating which camera the image signal is generated, information indicating which line the image signal is in one field, and information indicating the line size of the image signal. Output to.

[0087] (Additional Information Generation Unit 75)

The additional information generation unit 75 generates an additional signal based on each piece of information received from the buffer selection control unit 72. The additional signal includes camera identification number information 81 indicating which camera generated the image signal, macroblock line information 82 indicating which line the image signal is for, and the line size of the image signal. Line size information 83 is included. The camera identification number information 81 identifies the camera by four values from 0 to 3 corresponding to the number of cameras. The macro block line information 82 divides the image into 16 lines and specifies which portion of the image of the image signal indicates one field. Since it is divided into 16 lines, the macro block line information 82 specifies which part of the image is indicated by “!” To “16” being “1”, “17 to 32” being “2”, etc. Size information 83 Stores, for example, a value equivalent to the line size. For example, if the line size is 720 pixels, the line size is indicated as “720”.

The additional information generation unit 75 outputs the generated additional signal to the selection circuit 7.

(Synchronization signal generator 73)

The synchronization signal generation unit 73 generates a superimposition timing signal based on the timing at which the image signal output from the switching device 2 to the video encoder 3 is switched, and the synchronization signal input terminal of the 1 input interface of the video encoder 3 by the H-SYNC 10 Output to.

As shown in FIG. 7, the synchronization signal generator 73 includes a counter 74, and the counter 74 accepts an input of a system clock (system CLK). When the synchronization signal generation unit 73 receives the above-described predetermined signal from the filter selection control unit 72, the synchronization signal generation unit 73 switches the output signal between high and low at the timing when the selection circuit 7 outputs the additional signal. Specifically, since the additional signal includes camera identification number information, macroblock line information, and line size information, the signal is switched between low and high so that these pieces of information can be distinguished. FIG. 8 is a diagram showing V-SYNC9 and H-SYNC10 output by the synchronization signal generation unit 73. As shown in FIG. DATA11 is output from the switching device 2 to the video encoder 3 including camera identification number information 81, macroblock line information 82, and line size information 83 as additional signals before the image signal. At the timing of the boundary between the camera identification number information 81, the macroblock line information 82, and the line size information 83 in the DATA 11, the synchronization signal generation unit 73 switches between a low signal and a high signal output as H-SYNC10. In the present embodiment, V-SYNC9 falls when the output of a certain image signal to the video encoder 3 is finished, and then V-SYNC9 rises at the timing when the image signal is switched. Then, during the period when this V-SYNC9 is speaking, H-SYNC10 is set to low or high as shown in Fig.8. As a result, the output timing of the additional signal can be notified to the video encoder 3 by V-SYNC9 and H-SYNC10.

[0090] Since the image signal is output during the period when both V-SYNC9 and H-SYNC10 are rising, the image signal has not been output yet, and when output is newly started, V-SYNC9 Both SYNC9 and H-SYNC10 are falling. Therefore, as shown in Figure 8, with V-SYNC9 falling, H-SYNC10 is brought high and then HS The additional signal starts when YNC10 falls.

[0091] 2. 2. 2. 3 Selection Circuit 7

The selection circuit 7 receives the read control signal output from the buffer selection control unit 32 of the control circuit 56, and connects to the buffer specified by the read control signal. Further, it is connected to the additional information generation unit 75 and receives additional information.

The selection circuit 7 outputs the additional signal received from the additional information generation unit 75 and the image signal read from the connected buffer memory to the video encoder 3 as DATA11. At this time, the selection circuit 7 outputs the additional signal first and then outputs the image signal.

[0092] 2.2.3 Video encoder 53

Next, the configuration of the video encoder 53 will be described.

2. 2. 3. 1 Image selector 58

As shown in FIG. 6, the image switching unit 58 is included in the camera input unit 8. Based on V-SYNC9 and H-SYNC10, the image switching unit 58 detects an additional signal superimposed on DATA11, and includes camera identification number information 81, macroblock line information 82, and line size information included in the additional signal. 83 is extracted and stored in the register.

[0093] Specifically, as shown in Fig. 8, the image switching unit 58 detects a change between H-SYNC9 low and high while V-SYNC9 is falling, and detects an additional signal from DATA11. To do. Further, the image switching unit 58 detects the rising edge of V-SYNC 9 and outputs the interrupt signal 22 to the interrupt controller 12.

Since the other components of the video encoder 3 are the same as those in the first embodiment, the description thereof is omitted.

[0094] 2.3 Operation

Next, the operation of the moving picture coding system 200 will be described.

The operation of the switching device 52 is as described in the configuration of the control circuit 56 described above. Therefore, the operation of the video encoder 53 will be described.

As described above, when the image switching unit 58 of the camera input unit 8 outputs the interrupt signal 22, an interrupt is generated in the processor 13 by the interrupt controller 12, and the interrupt handler is started. Move. The interrupt handler has the power to generate the interrupt signal 22 and the address range in the input image area 17 of the memory 16 where the image signal is stored is stored in the camera identification number information 81 and the macro block stored in the image switching unit 58. Calculated based on line information 82 and the like.

FIG. 9 is a flowchart showing processing performed by the interrupt handler in the processor 13 according to the second embodiment.

The interrupt handler reads the camera identification number information 81, macroblock line information 82, and line size information 83 stored in the register by the image switching unit 58 from the register (step S201).

[0096] Based on the read camera identification number information 81, macroblock line information 82, and line size information 83, the interrupt handler determines in which address range the input image area 17 of the memory 16 stores the image signal. Calculate (step S203). For example, as in the first embodiment, it is assumed that the memory address and the image signal correspond to which camera and which line. Since the size of the captured image signal data varies depending on the line size, the line size information 83 is also used to calculate the address range.

The harmful ij entry handler sets the address range calculated in step S203 in the data transfer unit 14 (step S205).

Further, the interrupt handler sets information necessary for encoding the image signal in the image encoding unit 15 (step S207), and ends the interrupt.

Thereafter, as in the first embodiment, the image signal force data transfer unit 14 captured by the camera input unit 8 transfers the image data to the address range calculated in step S203 by the interrupt handler. Further, the image encoding unit 15 starts the encoding process when the image signal for one macroblock line is transferred to the input image area 17 by the data transfer unit 14.

[0098] FIG. 10 shows a timing chart of the moving picture coding system operating in this way. In the figure, first, the video signal of the macro block line is taken into the video encoder 53 in the order of camera # 0, camera # 1, camera # 3, camera # 2,. In the figure, DAT Al 1 includes both an additional signal and an image signal! /, That is! /. V-SYNC9 rises at the boundary between the additional signal and the image signal, and interrupt signal 22 is output. FIG. 11 shows the start timing of the encoding process in the video encoder 53.

As shown in FIG. 11, the image signal of each camera is captured for each macroblock line. The video encoder 3 starts the encoding process as shown in the “encoding process” when the image signal for the macroblock line is taken in as shown in the “video encoder input”.

[0100] 2.4 Summary

According to the above configuration, the position of the additional signal and the position of each information in the additional signal can be obtained by using the combination of the two signals using the vertical synchronization signal input terminal and the horizontal synchronization signal input terminal of the video encoder 53. The boundary can be indicated, and images from multiple cameras can be switched and captured in arbitrary units without adding special signal lines to the video encoder 53. In addition, the above-described image signal can be captured even if each camera is not operating synchronously.

[0101] 3 Embodiment 3

FIG. 12 shows a configuration of moving picture coding system 300 according to Embodiment 3 of the present invention.

The moving image encoding system 300 encodes moving images from a plurality of cameras, transmits them via a network, decodes the encoded data, and displays them on a monitor. For example, a surveillance camera system. Cameras 91a, 91b, 91c, 91d, encoder device 92 that compresses and encodes camera images, transmission device 93 that transmits the compressed and encoded data over network 94, and data that is compressed and encoded from network 94 Receiving device 95, decoding device 96 for decoding the received encoded data, and monitor 97 for displaying the decoded moving image. The encoder device 92 of the moving image coding system 300 has the same configuration as the combination of the switching device 2 and the video encoder 3 shown in FIG. 1 or the combination of the switching device 52 and the video encoder 53 shown in FIG. .

[0102] In such a configuration, every time the image signal of the macroblock line is encoded in the encoder device 92, the transmission device 93 converts the encoded data after encoding into a unit smaller than the frame, for example, the macroblock line. The data is transmitted to the receiving device 95 in units. At this time, The encoded data is transmitted by adding information such as the power that the encoded data is based on which camera data and which line is indicated in the image as a header.

[0103] Receiving device 95 receives encoded data transmitted in units smaller than a frame and outputs the encoded data to decoder device 96.

The decoder device 96 decodes the encoded data received by the receiving device 95. At this time, referring to the information added as a header, the storage area of the decoded data in the memory is determined. For example, the storage area on the memory is determined so that the memory address corresponds to which camera the decoded data belongs to, and which line in the image. The decoder device 96 outputs the decoded data to the monitor 97.

[0104] According to the above-described configuration, since the switching control with a size smaller than the frame unit can be performed, the delay related to encoding can be reduced. Therefore, the delay in image transmission can be reduced with the force S. .

4 Supplement

As described above, the force S described in the embodiment of the present invention, the present invention is not limited to the above-described configuration.

[0105] 4.1 Camera 1

In the first embodiment described above, the camera 1 is described as one camera outputs the synchronization signal 4 to the other camera, so that the cameras la, lb, lc, and Id operate in synchronization with each other. The method of synchronizing the cameras la, lb, lc, and Id is not limited to this. For example, the cameras la, lb, lc, and Id may be synchronized when the camera 1 receives a synchronization signal from an external device (for example, the switching device 2).

[0106] 4.2 Configuration of buffer memory

In the embodiment described above, the force S with the size of the buffer memory having the two-surface configuration of the buffer 5 set to 16 lines (macroblock line) is not limited to this, and may be any size. In addition, although the two-plane configuration is adopted, it is not necessary to limit to such a configuration as long as the input and the output can be controlled simultaneously.

[0107] 4.3 Image signal output unit

In the above-described embodiment, the switching device 2 and the switching device 52 are macros that are units of encoding. The image signal is switched every time the image signal of the block line is output. However, the present invention is not limited to this, and the image signal for an arbitrary line may be output. For example, the image signal may be switched every time an image signal corresponding to a multiple of the macro block line is output. Further, the image signal may be switched with a smaller number of lines than the macroblock lines. However, if the image signal is switched in units smaller than the macroblock line, the processor 13 is interrupted when the image signal is switched, so if the switching frequency increases, the overhead of the processor 13 will increase. Note that the efficiency of

Yes

[0108] 4.4 Switching control signal

In the first embodiment, the synchronization signal generation unit 33 sets both V-SYNC9 and H-SYNC10 to high level or low level, but V-SYNC9 and H-SYNC10 are both set to high level. It is also possible to indicate the switching of the image signal using only one of V-SYNC9 and H-SYNC10. For example, when only the H-SYNC10 is used to indicate the switching of the image signal, the video encoder 3 uses which camera the image signal input as DATA11 is generated by the H-SYN C10. It is good to distinguish.

[0109] 4.5 Other supplements

(1) Each of the above devices is specifically a computer system that includes a microprocessor, ROM, RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like. A computer program is stored in the RAM or the hard disk unit. Microprocessor power Each device achieves its functions by operating according to the computer program. Here, the computer program is configured by combining a plurality of instruction codes indicating instructions to the computer in order to achieve a predetermined function.

[0110] Note that each device is not limited to a computer system including all of a microprocessor, ROM, RAM, hard disk unit, display unit, keyboard, mouse, and the like. Even a system! /

(2) Some or all of the components that make up each of the above devices are made up of a single system LSI (Larg e Scale Integration: large scale integrated circuit). A system LSI is an ultra-multifunctional LSI manufactured by integrating multiple components on a single chip. Specifically, it is a computer system that includes a microprocessor, ROM, RAM, and so on. is there. A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program.

(3) A part or all of the components constituting each of the above devices may be configured as an IC card that can be attached to and detached from each device or a single module. The IC card or the module is a computer system including a microprocessor, ROM, RAM, and the like. The IC card or the module may include the super multifunctional LSI described above. Microprocessor power By operating according to a computer program, the IC card or the module achieves its function. This IC card or module may be tamper resistant! /.

(4) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program! /.

[0111] The present invention also relates to a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD ( It may be recorded on a Blu-ray Disc) or semiconductor memory. Further, the present invention may be the computer program or the digital signal recorded on these recording media.

Further, the present invention may transmit the computer program or the digital signal via an electric communication line, a wireless or wired communication line, a network typified by the Internet, a data broadcast, or the like.

The present invention may also be a computer system including a microprocessor and a memory. The memory may store the computer program, and the microprocessor may operate according to the computer program.

[0113] Further, the program or the digital signal is recorded on the recording medium and transferred. Or may be implemented by another independent computer system by transferring the program or the digital signal via the network or the like.

(5) The above embodiment and the above modifications may be combined! /, Respectively.

Industrial applicability

The present invention is useful for a moving image encoding system that inputs and processes images from a plurality of cameras, and is intended for application to a monitoring system or the like.

Claims

The scope of the claims

[1] A moving image encoding system for encoding a plurality of moving images,

Signal receiving means for receiving image signals generated by camera imaging for a plurality of cameras, temporary storage means for storing a plurality of image signals received by the signal receiving means, and a plurality of image signals cyclically for each camera The image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image coding or a multiple of the number of lines is read out from the temporary storage means and output, and the timing at which the plurality of image signals are switched. Output control means for generating and outputting a switching control signal indicating

Encoding means,

The encoding unit includes one input interface including a synchronization signal input unit and one image signal input unit. Each of the image signals for the predetermined number of lines output by switching by the output control unit The switching control signal is received by the input interface of 1 and the received image signals for the predetermined number of lines are distinguished and encoded by the timing indicated by the switching control signal.

A video encoding system characterized by the above.

[2] A switching device that switches a plurality of moving images and outputs the video encoder to one input interface including a synchronization signal input unit and one image signal input unit of the video encoder,

Signal receiving means for receiving image signals generated by camera imaging for a plurality of cameras, temporary storage means for storing a plurality of image signals received by the signal receiving means, and a plurality of image signals cyclically for each camera The image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or a multiple of the number of lines is read from the temporary storage means and output to the input interface of 1 and Output control means for generating a switching control signal indicating the timing at which a plurality of image signals are switched and outputting the switching control signal to the one input interface.

A switching device characterized by that.

[3] The plurality of image signals are generated in synchronization with timing according to a predetermined synchronization signal including a vertical synchronization signal and a horizontal synchronization signal,

The output control means is an image signal at a timing based on the predetermined horizontal synchronization signal. Switching between issues

The switching device according to claim 2.

[4] The output control means includes a data capturing control section for detecting, based on the predetermined horizontal synchronizing signal, that the image receiving signals for the predetermined number of lines are received by the signal receiving means;

Each time the detection is performed, the image signals corresponding to the predetermined number of lines stored in the temporary storage unit are read out and output within a period required to receive the image signals corresponding to the predetermined number of lines. Including a buffer selection control unit

The switching device according to claim 3.

[5] The temporary storage means is a plurality of FIFO type buffer memories provided corresponding to each image signal, and each of the buffer memories includes two storage units,

The temporary storage means stores each image signal received by the signal receiving means in a corresponding buffer memory, and each of the buffer memories is selectively switched between the two storage units. The received image signal is written and stored,

The data capture control unit switches the storage unit each time it detects that the signal reception unit has received image signals for the predetermined number of lines, and the buffer selection control unit is configured to store the two storage units. 5. The switching device according to claim 4, wherein the reading of the image signal is performed from the one in which the image signals for the predetermined number of lines have already been written.

[6] Each camera captures images in synchronization with the timing indicated by the synchronization signal output by one of the cameras.

The output control means includes

4. The synchronization signal input unit that receives an input of a synchronization signal output from the one camera, wherein the predetermined synchronization signal is a synchronization signal received by the synchronization signal input unit. Switching device.

[7] The number of lines that is the minimum unit of image coding is the number of lines for a macroblock. The switching device according to claim 2.

Multiple image signals switched and output by the switching device are received by one input interface consisting of a synchronization signal input unit and one image signal input unit, and each image signal is encoded.

Each of the image signals that includes the input interface of 1 and that is output by switching by the switching device every predetermined number of lines, and a switching control signal that indicates a switching timing of the image signal are input to the image signal of 1 And a synchronization signal input unit, and encoding means for distinguishing and encoding each of the received image signals according to the timing indicated by the switching control signal

A video encoder characterized by that.

[9] The encoding means includes:

Each time the switching timing indicated by the switching control signal is reached, a predetermined number of received image signals are encoded.

The video encoder according to claim 8, wherein

[10] The image signal is stored in one memory area having a storage area for storing a predetermined number of lines of image signals in the video encoder, and each image signal is stored in a different memory area. And

The encoding means generates an interrupt at each switching timing indicated by the switching control signal to perform reception processing of the image signal, and ends the reception processing when receiving the image signals for the predetermined number of lines. The memory area for storing the image signal is switched at each switching timing.

The video encoder according to claim 8, wherein

[11] A moving image encoding system for encoding a plurality of moving images,

A signal receiving means for receiving image signals generated by imaging of a camera for a plurality of cameras, a temporary storage means for storing a plurality of image signals received by the signal receiving means, and switching the plurality of image signals for each camera. The image signal corresponding to the predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or the number of lines that is a multiple thereof is read from the temporary storage means, and the read image signal and the additional signal for identifying the image signal With Output control means for outputting a set and generating and outputting a superposition timing signal for distinguishing the additional signal and the image signal;

Encoding means,

The encoding unit includes one input interface including a synchronization signal input unit and one image signal input unit. Each of the image signals for the predetermined number of lines output by switching by the output control unit The additional signal and the superposition timing signal are received by the input interface of 1, and the received image signals for the predetermined number of lines and the additional signal are distinguished by the received superposition timing signal and received. By identifying the image signals for the predetermined number of lines using the additional signal, each image signal is distinguished and encoded.

A video encoding system characterized by the above.

[12] A switching device for switching a plurality of moving images and outputting the video encoder to one input interface including a synchronization signal input unit and one image signal input unit of the video encoder,

A signal receiving means for receiving image signals generated by imaging of a camera for a plurality of cameras, a temporary storage means for storing a plurality of image signals received by the signal receiving means, and switching the plurality of image signals for each camera. The image signal corresponding to the predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or the number of lines that is a multiple thereof is read from the temporary storage means, and the read image signal and the additional signal for identifying the image signal Output control means for generating a superposition timing signal for distinguishing an additional signal from an image signal and outputting the generated signal to the input interface. Switching device characterized.

[13] The output control means includes:

A synchronization signal receiving unit that receives a synchronization signal for generating an image signal for each of the image signals;

Based on each synchronization signal received by the synchronization signal receiver, the switching output of the set of the image signal and the additional signal and the output of the superimposition timing signal are performed.

The switching device according to claim 12, wherein: [[1144]] The previously described output force control control means stage is the same synchronization period signal that is received and received by the aforementioned same period signal reception / reception unit. Based on each horizontal horizontal sync signal signal, each of the above-mentioned multiple image signal signals can be connected to each other. In this case, the image signal signals corresponding to the predetermined number of predetermined lines are received and received by the previous receiving signal receiving / receiving means means. A data take-in control unit that detects and detects the event, and

An additional additional information generating section for generating an additional additional signal,

In the order in which the data detection and detection control was made by the data acquisition and control unit, the image signals corresponding to the predetermined number of lines are stored. A signal image is read and read out from the temporary memory storage means, and the image is displayed for a predetermined number of lines. And the signal generated and generated by the previously described additional additional information information generating unit in accordance with the image signal. And a selection / selection part that outputs and outputs an additional signal signal.

The switching device according to claim 1133, wherein this is a special feature. .

[[1155]] The above-mentioned additional additive signal includes the information information for identifying the image signal.

The switching device according to claim 1122, wherein this is a special feature. .

[[1166]] The above-mentioned additional additive signal number indicates which line in the image image signal the image signal signal has in 11 frames. Mamakuro Chloroblock Clarion Information Information, 11 or 11 Including tsutsu

The switching device according to claim 1155, wherein this is a special feature. .

[[1177]] Multiple image signals that are output by the switching device are switched and output to the same period signal input input section. The 11 input image input signals and 11 input image input signals are received and received according to the interface surface. Each image signal is converted into a sign code.

A set of each of the image signals including the input interface of 1 and switched and output every predetermined number of lines by the switching device and an additional signal for identifying the image signal, and the additional signal and the image signal Is received by the input interface of 1 and the received image signal for the predetermined line and the additional signal are distinguished by the received superimposition timing signal, and the received predetermined signal is received. It comprises coding means for distinguishing and coding each of the image signals by identifying the image signals for the lines using the additional signal.

A video encoder characterized by that.

1 input interface consisting of sync signal input section and 1 image signal input section A moving image encoding method for encoding a plurality of moving images in a moving image encoding system comprising a video encoder and a switching device that switches and outputs a plurality of moving images to the first input interface,

A signal receiving step for receiving image signals generated by imaging by a plurality of cameras; a temporary storage step for storing a plurality of image signals received by the signal receiving step by a temporary storage means of the switching device;

A plurality of image signals are cyclically switched for each camera, and image signals corresponding to a predetermined number of lines consisting of the number of lines as a minimum unit of image encoding or a multiple of the number of lines are read from the temporary storage means and output. And an output control step for generating and outputting a switching control signal indicating a timing at which the plurality of image signals are switched;

Each of the predetermined number of image signals switched and output in the output control step and the switching control signal are received by the input interface of 1, and each of the received image signals is indicated in the switching control signal. And a coding step for performing coding separately according to the timing

A video encoding method characterized by the above.

A video encoding system comprising a video encoder having one input interface comprising a synchronization signal input unit and one video signal input unit, and a switching device for switching and outputting a plurality of video images to the one input interface A moving image encoding method for encoding a plurality of moving images in

A plurality of image signals are switched in units of cameras, and image signals for a predetermined number of lines consisting of the number of lines that are the minimum unit of image encoding or a number of lines that is a multiple thereof are read from the temporary storage means, and the read image signals A superimposition timing signal for discriminating between the additional signal and the image signal while outputting a set of the additional signal for identifying the image signal Output control step for generating and outputting

The image signals corresponding to the predetermined number of lines that are switched and output in the output control step, the additional signal, and the superimposition timing signal are received by the input interface of 1, and the number of the received predetermined lines The image signal and the additional signal are distinguished from each other by the received superposition timing signal, and the received image signals for the predetermined number of lines are identified using the additional signal, whereby each of the image signals is identified. Including an encoding step for distinguishing and encoding

A video encoding method characterized by the above.

[20] An integrated circuit used in a switching device that switches a plurality of moving images and outputs the video encoder to one input interface including a synchronization signal input unit and one image signal input unit.

A signal receiving unit that receives image signals generated by the imaging of a camera for a plurality of cameras, a temporary storage unit that stores a plurality of image signals received by the signal receiving unit, and a plurality of image signals that are cyclic for each camera The image signal for a predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or the number of lines that is a multiple thereof is read from the temporary storage unit and output to the input interface of 1 and And an output control unit that generates a switching control signal indicating the timing at which the image signal of the image signal is switched and outputs the switching control signal to the input interface of 1

An integrated circuit characterized by that.

[21] Used for a video encoder that receives a plurality of image signals switched and output by a switching device through one input interface including a synchronization signal input unit and one image signal input unit and encodes each image signal. Integrated circuit

Each of the image signals received by the one input interface and switched and output every predetermined number of lines by the switching device,

An encoding unit that distinguishes and encodes by a switching control signal that indicates the switching timing of an image signal that is output from the switching device and received by the first input interface;

An integrated circuit characterized by that. [22] An integrated circuit used in a switching device that switches a plurality of moving images and outputs the video encoder to one input interface including a synchronization signal input unit and one image signal input unit.

A signal receiving unit that receives image signals generated by camera imaging for a plurality of cameras, a temporary storage unit that stores a plurality of image signals received by the signal receiving unit, and a plurality of image signals that are switched on a camera-by-camera basis. The image signal for the predetermined number of lines consisting of the number of lines that is the minimum unit of image encoding or the number of lines that is a multiple thereof is read from the temporary storage unit, and the read image signal is added to identify the image signal An output control unit that outputs a set of signals to the input interface of 1 and generates a superposition timing signal for distinguishing between the additional signal and the image signal and outputs the signal to the input interface of 1

An integrated circuit characterized by that.

[23] Used for a video encoder that receives a plurality of image signals switched and output by a switching device through one input interface including a synchronization signal input unit and one image signal input unit, and encodes each image signal. Integrated circuit

Each of the image signals that are switched from the switching device every predetermined number of lines and output and received by the input interface of 1 is distinguished from the additional signal for identifying the image signal, the additional signal and the image signal. Using the superimposition timing signal to distinguish the additional signal and the image signal for the predetermined number of lines by the superimposition timing signal, and identify the image signal for the predetermined line using the additional signal. An encoding unit that distinguishes and encodes each of the image signals.

An integrated circuit characterized by that.

[24] A control program for switching a plurality of moving images and causing the switching device to perform a process of outputting to one input interface including a synchronization signal input unit and one image signal input unit of a video encoder. And

A signal receiving step for receiving image signals generated by camera imaging for a plurality of cameras, and a plurality of image signals received by the signal receiving step for temporarily storing the switching device. A temporary storage step to be stored in the memory means;

A plurality of image signals are cyclically switched in units of cameras, and image signals for a predetermined number of lines consisting of the number of lines as a minimum unit of image encoding or a multiple of the number of lines are read from the temporary storage means and the 1 And an output control step of generating a switching control signal indicating a timing at which the plurality of image signals are switched and outputting the switching control signal to the first input interface.

A control program characterized by that.

[25] A video encoder having one input interface composed of a synchronization signal input unit and one image signal input unit receives a plurality of image signals output by the switching device by the switching device, and receives each of the image signals. A control program for performing processing for encoding an image signal,

Each of the image signals that are switched and output every predetermined number of lines by the switching device and received by the input interface of 1,

An encoding step of distinguishing and encoding by a switching control signal indicating a switching timing of an image signal, which is output from the switching device and received by the input interface of 1

A control program characterized by that.

[26] A control program for switching a plurality of moving images and causing the switching device to perform processing to output to one input interface including a synchronization signal input unit and one image signal input unit of the video encoder. And

A plurality of image signals are switched in units of cameras, and image signals for a predetermined number of lines consisting of the number of lines that are the minimum unit of image encoding or a number of lines that is a multiple thereof are read from the temporary storage means, and the read image signals A set of additional signals for identifying the image signal is output to the input interface 1 and the additional signal is separated from the image signal. An output control step of generating a superimposition timing signal for output to the input interface of 1

A control program characterized by that.

A video encoder having one input interface consisting of a synchronization signal input unit and one image signal input unit receives a plurality of image signals switched and output by the switching device through the first input interface to receive each image signal. A control program for performing a process of encoding,

A set of an image signal switched and output every predetermined number of lines by the switching device and an additional signal for identifying the image signal for the predetermined number of lines, and the additional signal and the image for the predetermined number of lines The superimposition timing signal for distinguishing the signal is received by the input interface of 1, and the received image signal for the predetermined number of lines and the additional signal are distinguished by the received superimposition timing signal and received. A coding step of distinguishing and coding each of the image signals by identifying the image signals for the predetermined number of lines using the additional signal;

A control program characterized by that.