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WO2008019574A1 - Interfaces d'e/s pour appareil de traitement de messages de rle, et méthode de communication - Google Patents

Interfaces d'e/s pour appareil de traitement de messages de rle, et méthode de communication Download PDF

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Publication number
WO2008019574A1
WO2008019574A1 PCT/CN2007/002270 CN2007002270W WO2008019574A1 WO 2008019574 A1 WO2008019574 A1 WO 2008019574A1 CN 2007002270 W CN2007002270 W CN 2007002270W WO 2008019574 A1 WO2008019574 A1 WO 2008019574A1
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WO
WIPO (PCT)
Prior art keywords
information
downlink
dual audio
dtmf
area network
Prior art date
Application number
PCT/CN2007/002270
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English (en)
Chinese (zh)
Inventor
Yibing Wang
Xiaohang Wang
Original Assignee
Yibing Wang
Xiaohang Wang
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Filing date
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Application filed by Yibing Wang, Xiaohang Wang filed Critical Yibing Wang
Publication of WO2008019574A1 publication Critical patent/WO2008019574A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Definitions

  • the invention relates to an input/output (I/O) interface of an information processing device between a local area network and a metropolitan area network, and a communication method for a local area network user and a metropolitan area network, and more particularly, a local area network and a metropolitan area
  • the information processing performance of information processing equipment (computer) in today's society is developing rapidly, and the computing speed is getting higher and higher, but the input and output (I/O) interface of the device and the structural state of the network have severely restricted its performance.
  • the input/output (I/O) interface is closely related to the technical structure of the external device and the network.
  • the time consumed in the execution of the system program is ignored as an overhead of the external device and is therefore ignored.
  • the input and output system and network structure only account for a small part of the information processing speed, it has a great impact on the entire system. For example, a device input and output system accounts for 10% of the total processing time.
  • the total processing speed is the reciprocal of the execution time
  • the metropolitan area network has also completed the fiber-optic ultra-wideband update, but the input/output (I/O) interface of information processing equipment, especially the LAN structure.
  • the publication number is CN1758584 and The patent titled "Frequency-allocated users access to the LAN system and the uplink and downlink transmission methods" patent application structure, no intermediate interface and interface protocol technology, and a new type of address coding and uplink and downlink transmission methods (protocols), The line scheduling in the heavy information communication of the LAN information processing device can be eliminated.
  • the invention invents a two-terminal input/output (I/O) interface of an information processing device between a local area network and a metropolitan area network, and a communication method between a local area network user and a metropolitan area network system. It can fully utilize the information processing performance of information processing equipment and the advantages of high-speed and large-capacity input and output data, so that information processing equipment and data communication can fully utilize the information high-speed processing performance, reduce configuration, save investment, and greatly improve communication operation efficiency.
  • I/O input/output
  • the present invention provides an input/output (I/O) interface of an information processing device of a node between a local area network and a metropolitan area network, and a communication method for a user terminal of the local area network and a metropolitan area network system,
  • I/O input/output
  • the information processing performance of the information processing equipment and the advantages of high-speed and large-capacity input and output data can be fully utilized, so that information processing equipment and data communication can fully utilize the information high-speed processing performance, reduce configuration, save investment, and greatly improve communication operation efficiency.
  • an input/output interface between an information processing center and a local area network including: a plurality of digital DTMF dual audio address coding trigger controllers; and a plurality of data buffer register modules, wherein The plurality of digital DTMF Han audio address encoding trigger controllers are in one-to-one correspondence with the plurality of data buffer register modules, and the plurality of digital DTMF dual audio address encoding trigger controllers receive downlink information from the information processing center, the downlink information Having a header and a trailer, with a binary DTMF dual audio address encoding in the header of the downlink information, with a binary DTMF dual audio off encoding in the end of the downlink information, the plurality of digital DTMF dual audio
  • Each of the address code trigger controllers decodes the above binary DTMF dual audio address encoding and binary DTMF dual audio off encoding into decimal DTMF dual audio address encoding and decimal DTMF dual audio off encoding, and
  • the punch register module outputs downlink information
  • the plurality of data buffer register modules respectively receive downlink information from the corresponding digital DTMF dual audio address code trigger controller, and output a downlink digital baseband signal according to the information format requirement
  • the downlink digital baseband signal has Letterhead and letterhead
  • DTMF dual audio address coding and information class coding are carried in the header of the digital baseband signal
  • DTMF dual audio off coding is carried in the signal tail of the digital baseband signal
  • the plurality of data buffer register modules are respectively
  • the uplink digital baseband signal with the user DTMF dual audio address code is received from the local area network, and the information processing center reads the uplink digital baseband signal from the plurality of data buffer register modules and processes the same.
  • an input and output interface between an information processing center and a metropolitan area network including: a plurality of digital DTMF Han audio address coding trigger controllers; and a plurality of data buffer register modules, The plurality of digital DTMF dual audio address encoding trigger controllers corresponding to the plurality of data buffer register modules, wherein the plurality of digital DTMF dual audio address encoding trigger controllers receive downlink information from the metropolitan area network,
  • the downlink information has a header and a signal tail, and has a binary DTMF dual audio address code in the header of the downlink information, and a binary DTMF dual audio off code in the end of the downlink information, the multiple numbers
  • Each of the DTMF dual audio address encoding trigger controllers decodes the above binary DTMF dual audio encoding into decimal DTMF dual audio encoding, and receives the downlink from the metropolitan area network according to the decoded DTMF dual audio encoding of the decimal header.
  • the information is output to the corresponding data buffer register module or the downlink information is not output, and if According to the buffer register module outputting the downlink information received from the metropolitan area network, the downlink information is stopped and outputted to the corresponding data buffer register module under the action of the DTMF dual audio off unified coding, the plurality of data buffer register modules Downstream information is received from a respective digital DTMF dual audio address encoding trigger controller, and the information processing center reads the downlink information from the plurality of data buffer register modules.
  • the plurality of data buffer register modules respectively receive uplink information from the information processing center, and output the received uplink information to the metropolitan area network, the uplink information having a header and a tail, and the user and the called party in the header
  • the DTMF dual audio address code of the LAN where the party is located has a unified identification code at the end of the signal, and the uplink information is used as downlink information when it arrives at the called party's local area network via the metropolitan area network and the wide area network.
  • a downlink communication method between an information processing center and a local area network including: a) receiving downlink information from an information processing center, the downlink information having a header and a tail, and the downlink information
  • the header of the header has a binary DTMF dual audio address encoding, and has a binary DTMF dual audio off encoding in the end of the downlink information; b) triggers the output of the received downlink information under the action of the header encoding, And under the action of the signal, the output of the downlink information is turned off; c) buffering the downlink information, and outputting the downlink digital baseband signal according to the information format requirement.
  • an information processing center and a local area network are provided The uplink communication method includes: a) receiving an uplink digital baseband signal with a user DTMF dual audio address code from the uplink of the local area network; b) buffering the received uplink digital baseband signal; and c) receiving the buffered uplink of the information processing center Digital baseband signal.
  • a downlink communication method between an information processing center and a metropolitan area network including: a) receiving downlink information from a metropolitan area network, the downlink information having a header and a trailer, where The header of the downlink information carries a binary DTMF dual audio address code, and has a binary DTMF dual audio off coding in the end of the downlink information; b) triggers the downlink of the output output under the action of the letter header coding Information, and under the action of the signal, the output of the downlink information is turned off; c) the downlink information of the buffer storage output; and d) the information processing center receives the buffered downlink information.
  • an uplink communication method between an information processing center and a metropolitan area network including: a) receiving uplink information from an information processing center; b) buffering and storing received uplink information; and c The buffered uplink information is sent to the metropolitan area network.
  • FIG. 1 is a circuit block diagram of a communication method of a two-terminal input/output (I/O) interface and a communication method between a local area network user and a metropolitan area network of an information processing device between a local area network and a metropolitan area network according to the present invention
  • FIG. 2 is a flow chart of downlink channel information of an input/output (I/O) interface between an information processing center and a local area network of the present invention
  • FIG. 3 is a flow chart of uplink channel information of an input/output (I/O) interface between an information processing center and a local area network of the present invention
  • Figure 4 is a circuit diagram of the digital DTMF dual audio address coded trigger controllers Kyl, Ky2 and Kyn for downlink information transmission of Figure 1;
  • FIG. 5 is a circuit schematic diagram of the digital DTMF dual audio address encoding trigger controllers Kbl, Kb2, and Kbn for the input signal transmission of the metropolitan area network;
  • FIG. 6A and FIG. 6B are circuit schematic diagrams of the user receiving end information classification and recognition trigger controllers Gtl and Gtn in FIG. 1;
  • Figure 7 is a circuit diagram of the digital decoders F1, F2 and Fn of the user's dual audio address encoding output of Figure 1;
  • 8 is a flow chart of an uplink communication method between an information processing center and a metropolitan area network
  • 9 is a flow chart of a method of downlink communication between an information processing center and a metropolitan area network.
  • FIG. 1 is a circuit block diagram of a communication method of a two-terminal input/output (I/O) interface and a communication method between a local area network user and a metropolitan area network of an information processing device between a local area network and a metropolitan area network according to the present invention.
  • I/O input/output
  • Cz is the information processing center
  • Cx is the I/O bus
  • Hx is the high-speed hub connected to Cx.
  • Kyl, Ky2, Kn, and Kbl, Kb2, and Kbn are digital DTMF dual audio address encoding trigger controllers.
  • Gyl, Gy2, Gyn, and Gbl, Gb2, and Gbn are data buffer (upstream, downstream) registers.
  • Each of the data buffer registers Gyl, Gy2, Gyn, and Gbl, Gb2, and Gbn can include multiple buffer registers to be used separately.
  • Fam is a frequency-distribution user accessing a LAN circuit module. The detailed structure of the circuit module can be seen in the circuit shown in Fig. 1 of the patent application with the publication number CN1758584.
  • Ml, M2, Mn are metropolitan area network lines.
  • Hjl, Hj2, and Hjn are user hubs, and branch lines Ftl, Ft2, and Ftn are branched.
  • Fl, F2, Fn are user-side uplink DTMF dual audio digital address decoding circuits.
  • Gtl and Gtn are classification and recognition trigger control input circuits for various types of information on the user side.
  • Each branch line Ftl is connected to Fl, F2, and Fn, and each branch line Ft2 and Ftn are connected to Gtl and Gtn, respectively.
  • Information Processing Center The information processed by Cz is branched into multiple channels when it reaches the high-speed hub Hx via the I/O bus.
  • the high-speed hub Hx branches out multiple branch lines, which are connected to the data buffer registers Gyl, Gy2, Gyn, Gbl, Gb2, Gbn and digital DTMF dual audio address encoding trigger controllers Kyi, Ky2, Kyn, Kbl, Kb2, Kbn.
  • the input of the LAN user downlink information in the data buffer registers Gyl, Gy2, Gyn is controlled by Kyl, Ky2, Kyn, respectively.
  • Kyi, Ky2, and Kyn trigger control, and the user downlink information can be input to the data buffer registers Gyl, Gy2, and Gyn.
  • the transmission of this time period (chip) ends, the input information is stopped under the action of the DTMF encoding at the end of the letter.
  • the data buffer registers Gyl, Gy2, Gyn output headers have the address encoding and information class coding of the DTMF dual audio and the digits with DTMF dual audio off coding in the trailer
  • the baseband signal enters the high frequency digital modems T1 ⁇ Tn (not shown) in the Fam module.
  • the digital baseband signal is modulated into a digital high-frequency broadband signal and then transmitted to each user's digital high-frequency demodulator via a local area network, and the digital baseband signal of each user is selected and frequency-modulated by the digital high-frequency demodulator to be transmitted to
  • the hubs Hjl, Hj2, Hjn set by each user end are respectively connected to the identification control circuits Gtl ⁇ Gtn of different signal classifications set by the user end via the branch lines Ft2 and Fto, respectively, and respectively supply the pre-data of the user display devices of different categories.
  • Buffer register processing (not shown) is provided for different categories of user display circuit processing (not shown).
  • An uplink DTMF dual audio address codec demodulator Fl, F2, Fn is set at each client.
  • the DTMF dual audio address code sent by the Icl in FIG. 6 in the patent application with the publication number CN1758584 is demodulated into digital DTMF number header information by F1, F2, Fn, and is transmitted through the Fam module together with the user's uplink digital baseband information.
  • the digital high frequency modulator is modulated into a high frequency digital wideband signal.
  • the high-frequency digital wideband signal is transmitted and demodulated by the uplink local area network into a digital baseband signal with a DTMF dual-audio user address coded header, and transmitted to the data buffer registers Gyl, Gy2, and Gyn of each user channel.
  • the flush register is used by the information processing center to process the identification of the user address code and process the user information during the user time period (slice).
  • a time division wheeled static processing method is employed to process local area network user uplink information.
  • the information processing center Cz only data from the user channel corresponding to the user time period (slice) among the data buffer registers Gyl, Gy2, and Gyn of each user channel.
  • the buffer register reads the uplink information and performs corresponding processing, and in this way, sequentially reads the uplink information from the data buffer registers of each user channel and performs corresponding processing.
  • the first user uplink information has been transmitted to the data buffer register Gyl through the LAN uplink.
  • the information processing center Cz only buffers data from the data buffer registers Gyl, Gy2, Gyn.
  • the register Gyl reads the first user uplink information and performs corresponding processing.
  • the second user uplink information has been transmitted to the data buffer register Gy2 through the local area network uplink.
  • the information processing center Cz only receives data from the data buffer registers Gyl, Gy2, and Gyn.
  • the buffer register Gy2 reads the second user uplink information and performs corresponding processing.
  • the nth user uplink information has been transmitted to the data buffer register Gyn through the LAN uplink, and during the nth user time period (chip), the information processing center Cz is only from the data buffer registers Gyl, Gy2, Gyn.
  • the data buffer register Gyn reads the nth user uplink information and performs corresponding processing.
  • the information processing center Cz After receiving and processing the user's uplink information, the information processing center Cz will correspondingly go to the local area network.
  • the user sends a downlink message.
  • the transmission of the downlink information may be performed during the same user time period (slice) as the user uplink information, or may be performed at another time.
  • the information processing center CZ receives the first user uplink information. Then, the information processing center Cz processes the first user uplink information and correspondingly transmits the downlink information to the first user according to the processing result.
  • the operation of transmitting the downlink information to the first user may be performed during the first user time period (slice), or may be performed in addition to the factors such as the time required to process the first user uplink information. Execution at a time other than a user time period (slice).
  • the input from the metropolitan area network (i.e., the downlink information between the information processing device and the metropolitan area network) is controlled by the DTMF dual audio address encoding control circuits KM, Kb2, Kbn.
  • the data buffer registers Gbl, Gb2, and Gbn are respectively connected to the lines M1, M2, and Mn of the telecommunications, broadcasting, internet, government, and business networks of the metropolitan area network.
  • the header of the message carries the DTMF dual audio address code of the LAN where the user and the called party are located and has a unified identification code at the end of the message.
  • the information can be input to the data buffer register for information processing.
  • Device processing under the action of DTMF close encoding at the end of the signal, stop serving the local area network and continuously input information to the local area network of another DTMF encoding header, and support intensive multi-address and high-efficiency group communication communication for sharing information.
  • the time division spinning static processing method is used to process the downlink information of the metropolitan area network. Specifically, during a certain period of time (slice), the information processing center Cz reads only the downlink information from one of the data buffer registers Gb1, Gb2, Gbn in the multiple downlink channels of the metropolitan area network, and performs corresponding processing, and presses In this manner, the downlink information is read and sequentially processed from the data buffer registers Gb1, Gb2, and Gbn in the respective downlink channels.
  • the first metropolitan area network downlink information has been transmitted to the data buffer register Gb1, and during the first time period (slice), the information processing center Cz reads only from the data buffer register Gbl among the data buffer registers Gb1, Gb2, Gbn. Take the downlink information of the first metropolitan area network and process it accordingly.
  • the second metropolitan area network downlink information has been transmitted to the data buffer register Gb2, and during the second period (chip), the information processing center Cz only receives the data buffer registers from the data buffer registers Gb1, Gb2, Gbn.
  • Gb2 reads the downlink information of the second metropolitan area network and performs corresponding processing.
  • the nth metropolitan area network downlink information has been transmitted to the data buffer register Gbn, during the nth time period (slice), the information processing center Cz only from the data buffer registers Gbl, Gb2
  • the data buffer register Gbn in Gbn reads the nth metropolitan area network downlink information and performs corresponding processing.
  • 2 is a flow chart of downlink channel information of an input/output (I/O) interface between an information processing center and a local area network of the present invention.
  • step S210 information from the information processing center is received, with an output (I/O) interface code of the DTMF dual audio address in the header, and DTMF dual audio off unified coding in the end of the letter.
  • step S220 under the action of the header encoding, a signal is input to the (I/O) interface data buffer register, and is turned off by the end of the signal.
  • step S230 the (I/O) data buffer register outputs a digital baseband signal in accordance with the information format, and the DTMF dual audio coding classification information identification and information closing code of the information category are carried in the header.
  • step S240 the downlink of the local area network is transmitted to the user's hub and branched into multiple signals.
  • step S250 the information is input under the information category header encoding trigger control, and the information input is turned off under the action of the signal tail.
  • Figure 3 is a flow chart showing the uplink channel information of the input/output (I/O) interface between the information processing center and the local area network of the present invention.
  • step S310 the user's dual audio address is encoded and decoded into two sets of digital binary DTMF dual audio address codes.
  • step S320 the digital baseband uplink information with the user digital DTMF address coded header is sent to the local area network uplink.
  • step S330 the uplink user information with the user address coded header is input to the uplink data buffer register in the (I/O) interface of the information processing center via the LAN uplink.
  • step S340 according to the static processing method of the time division wheel, the information processing center identifies the user address in each user time period (slice) and processes the corresponding user uplink information.
  • Figure 4 is a circuit diagram of the digital DTMF dual audio address coded trigger controllers Kyl, Ky2 and Kyn for downlink information transmission of Figure 1.
  • the digital DTMF dual audio address encoding trigger controllers Kyi, Ky2, and Kyn include: power supply V+, integrated circuit Ic CD4514, resistors R1 to R5, capacitor Cl, normally closed relay K, thyristors D1 to D6, and transistor G .
  • Resistors R1 and R2 function as a step-down protection.
  • the integrated circuit Ic CD4514 is a decoding chip with a logic decoding circuit that demodulates the binary digital DTMF signal into a decimal Chinese audio signal. Its 1 pin and 24 pin are connected to the power supply V + via the resistor R1, and the 12 pin is grounded.
  • Each DTMF coded digital binary information Txl, ⁇ 2, ⁇ 3, ⁇ 4 is divided into two groups, which are input to Ic CD4514, 2 pin, 3 pin, 21 pin, 22 pin, which are decoded by internal logic circuit and then at 20 feet and 9 feet respectively.
  • the output number is A, Decimal two-tone signals of B, C, D, 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
  • Thyristors Dl, D2, D3, D4 are connected in series with the positive and negative poles to form a header trigger circuit.
  • the trigger poles are connected to the 5th, 13th, 4th, and 15th pins of CD4514 to form 2638 (here, "2638" refers to
  • the dual audio user address coding trigger control circuit is output from the 5th, 13th, 4th, and 15th feet of the decimal binary audio signals of 2, 6, 3, and 8 respectively.
  • the positive and negative poles of the thyristors D5 and D6 are connected in series, and the trigger poles are respectively connected to the 8th and 7th pins of the CD4514 to form D and 0 (here, "D and 0" refer to the numbers output from the 8th and 7th pins respectively.
  • the coded tail of the D and 0 decimal diphonic signals triggers the shutdown circuit.
  • One end of the control coil of the normally closed relay K is connected to the normally closed contact 2 pin and the resistor R2, and the other end is connected to the positive pole of D5.
  • the normally closed contact 1 of the normally closed relay K is connected to the power supply V + .
  • the cathode of D6 is connected to the anode of D1 and is connected to the normally closed contact 2 of K via a step-down protection resistor R2.
  • G is a crystal switch transistor
  • R3 is the base bias resistor of G and is connected to the negative pole of D4
  • capacitor C1 is the coupling capacitor and is connected to the base of G
  • resistor R5 is the emitter resistance of G
  • R4 is the collector load resistance of G. .
  • the DTMF binary digit code with 2638 comes from the header of the information from the information processing center
  • the DTMF binary digit code with 2638 is input from pins 2, 3, 21, and 22 of the CD4514, respectively.
  • the 2638 DTMF dual-tone coded address decimal signals sequentially output at 5 feet, 13 feet, 4 feet, and 15 feet respectively trigger the thyristors D1 to D4 to be turned on, so that the power supply V + passes through the 1 and 2 feet of K.
  • the resistor R2, the thyristor Dl-D4, and the resistor R3 are applied to the base of G, and the G is biased to be turned on, so that the information is input through the base of C1 to G, and the information Vgy is outputted at the emitter.
  • the time delay for triggering conduction can be synchronized by software.
  • the thyristors D5 and D6 are turned on. Due to the action of the step-down resistor R2, a larger current flows from the control coil of K, causing the normally-closed relay K to operate, causing the normally-closed contacts 1 and 2 to be disconnected instantaneously, thereby thyristors D1 to D6, and transistors The base of G is de-energized and cut off. Then, K quickly returns to the normally closed state, and the entire circuit is in the standby state, waiting for the next time information to arrive.
  • the different output codes of CD4514 can form different (I/O) I/O interface address codes, which can form up to 10,000 address codes.
  • Figure 5 is a circuit diagram of the digital DTMF dual audio address encoding trigger controllers Kbl, Kb2 and Kbn for the input signal transmission of the metropolitan area network in Figure 1.
  • the trigger poles of D3 and D4 are connected to the 4th, 17th, 5th, and 16th pins of Ic CD4514, respectively.
  • 3527 refers to the local area code of the local area code encoded by the decimal coded signals of numbers 3, 5, 2, and 7 which are output from 4 feet, 17 feet, 5 feet, and 16 feet, respectively.
  • the first 4 bits of the 8-bit address code of the telecom metropolitan area network user are used as the address code of the local area network, and the last 4 bits are the (I/O) input and output of the information processing device. Interface address code.
  • the digital binary code of 3527 in the header is sequentially input from the pins 2, 3, 21, and 22 of the Ic CD4514.
  • the decimal 3527 encoded dual audio signals outputted at the 4th, 17th, 5th, and 16th pins respectively trigger the thyristors D1 to D4 to be turned on, thereby causing the power supply V+ to pass the 1st and 2nd pins of the K, and the resistor R2.
  • the thyristors D1-D4 and the resistor R3 are applied to the base of G, so that G is biased to the base and is turned on.
  • the information input by the metropolitan area network is input to the base of G via C1, and the information Vgb is output to the data buffer register at the emitter.
  • the delay in controlling conduction can be synchronized by software.
  • the thyristors D5 and D6 are turned on by the binary digital DTMF coded signals with D and 0 in the end of the signal. Due to the action of the resistor R2, a larger current flows from the control coil of K, and the normally-closed relay K is operated to open the normally closed contact 1 and 2, and the thyristors D1 to D6 and the transistor G are The base is de-energized and cut off. Then, K quickly returns to the normally closed state, and the entire circuit is in the standby state, waiting for the next time information to arrive.
  • the last 4 user address codes and information in the header are input into the data buffer register for identification and processing by the information processing center.
  • 6A and 6B are circuit schematic diagrams of the user receiving end information classification and recognition trigger controllers Gtl, Gtn in Fig. 1.
  • the user receiving end information classification and recognition trigger controllers Gtl and Gtn include: a power supply V+, an integrated circuit Ic CD4514, a resistor R1 to R5, a capacitor C1, a normally closed relay K, thyristors D1 to D6, and a crystal switch. Transistor 0.
  • the integrated circuit Ic CD4514 is a decoding chip with a logic decoding circuit and a binary number.
  • the DTMF signal is demodulated into a decimal two-tone signal. Its 1 pin and 24 pin are connected to the power supply V + via the resistor R1, and the 12 pin is grounded.
  • Each DTMF coded digital binary information Txl, ⁇ 2, ⁇ 3, ⁇ 4 is divided into two groups, which are input to Ic CD4514, 2 feet, 3 feet, 21 feet, 22 feet, which are decoded by internal logic circuit and then divided into 'J at 20 feet. , 9-pin, 10-pin, 8-pin, 7-pin, 6-pin, 5-pin, 4-pin, 18-pin, 17-pin, 13-pin, 16-pin, 15-pin, and 11-pin output numbers 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D decimal audio signals.
  • the trigger poles of the thyristors D1, D2, and D3 are respectively connected to the 13-pin, 9-pin, and 6-pin of the CD4514 to form A15 (here, "A15” refers to the output from the 13-pin, 9-pin, and 6-pin, respectively.
  • the interphase tubes D1, D2, and D3 are connected in series with the positive and negative electrodes, and the trigger poles are respectively connected to the 16th, 10th, and 7th pins of the CD4514, thereby forming B24 (here, "B24" refers to 16 from respectively.
  • the positive and negative poles of the thyristors D4 and D5 in Fig. 6A and Fig. 6B are connected in series, and the trigger poles are respectively connected to the 11th and 20th pins of the CD4514, thereby forming a unified coded tail termination trigger circuit of D and 0.
  • the classification information trigger control circuit of various information categories can be formed.
  • One end of the control coil of the normally closed relay K in Figs. 6A and 6B is connected to the normally closed contact pin 2 and the resistor R2, and the other end is connected to the anode of D4.
  • the normally closed contact of the normally closed relay K is connected to the power supply V + .
  • the negative pole of D5 is connected to the positive pole of D1 and is connected to the normally closed contact 2 of K via a protective resistor R2.
  • G is the crystal switching transistor
  • R3 is the base biasing resistor of G and is connected to the negative pole of D3.
  • Capacitor C1 is the coupling capacitor and is connected to the base of G.
  • R4 is the collector load resistance of G
  • R5 is the emitter resistance of G.
  • the two-tone binary digital code with A15 or B24 is respectively from the 2 pin, 3 pin, 21 of the CD4514. Foot, 22 feet input.
  • the decimal or two-digit coded signals of A15 or B24 sequentially output in the 13th, 9th, and 6th pins of the A picture or the 16th, 10th, and 7th pins of the B picture respectively trigger the thyristors D1 to D3 to be turned on.
  • the power supply V+ is applied to the base of G via pin 1 and pin 2 of K, resistor R2, thyristor D1-D3, and resistor R3, so that G is biased by the base and turned on. Accordingly, the information is coupled to the base input of G via C1 and outputs information Vgl or Vgn at the emitter.
  • the time delay for triggering conduction can be synchronized by software.
  • the thyristors D4 and D5 are turned on by the binary digital DTMF coded signals with D and 0 in the end of the signal. Due to the action of the step-down resistor R2, a larger current flows from the control coil of K, causing the normally-closed relay K to operate, so that the normally-closed contacts 1 and 2 are momentarily disconnected, thereby thyristors D1 to D3, and transistors The base of G is de-energized and cut off. Then, K quickly returns to the normally closed state, leaving the entire circuit in standby, waiting for the next message to arrive. Therefore, the classification is recognized by using the user receiving end information in FIGS. 6A and 6B.
  • the controllers Gtl and Gtn enable different types of information to be classified and identified.
  • Figure 7 is a circuit diagram of the digital decoders F1, F2 and Fn of the user's dual audio address coded output of Figure 1.
  • the digital decoder Fl, F2 and Fn of the user's dual audio address encoding output include: power supply V + , integrated circuit Ic YN9101, crystal oscillator Hd, coupling capacitor (3.
  • the YN9101 has a logic decoding circuit and a signal amplifying circuit.
  • Integrated circuit Ic YN9101 3 pin, 4 pin, 5 pin, 6 pin power supply V + , 7 pin is DTMF dual audio decimal signal input, 8 pin ground, 9 pin, 10 pin crystal oscillator Hd for clock synchronization.
  • 2 feet, 1 foot, 14 feet, 13 feet are binary digital DTMF dual audio coded outputs, which sequentially output two sets of digital binary signals Txl, Tx2, Tx3, ⁇ 4.
  • the decimal DTMF dual audio signal is input to pin 7 of the YN9101 via the coupling capacitor C and processed by the internal circuit.
  • two sets of binary digits of the dual audio signal are output on the 2 feet, 1 foot, 14 feet, and 13 feet, and are added to the header of the user uplink information, and input to the input/output (I/O) interface of the information processing device via the LAN.
  • the upstream data buffer register is identified and processed by the information processing center.
  • FIG. 8 is a flow chart of an uplink communication method between an information processing center and a metropolitan area network.
  • step S810 uplink information is received from an information processing center, where the uplink information has a header and a trailer, and the DTMF dual audio address code of the local area network where the user and the called party are located is in the header, at the end of the signal There is a unified identification code, and the uplink information is used as downlink information when it arrives at the called party's local area network via the metropolitan area network and the wide area network.
  • the (I/O) interface data buffer register buffers the received uplink information.
  • step S830 the (I/O) interface data buffer register transmits the buffered uplink information to the metropolitan area network.
  • 9 is a flow chart of a method of downlink communication between an information processing center and a metropolitan area network.
  • step S910 downlink information is received from the metropolitan area network, where the downlink information has a header and a trailer, and a binary DTMF dual audio address code is included in the header of the downlink information, at the end of the downlink information.
  • DTMF dual audio off encoding with binary.
  • the digital DTMF dual audio address coding trigger controller triggers the downlink information outputted to the (I/O) interface data buffer register, and turns off the downlink information under the action of the signal tail. Output.
  • step S930 the (I/O) interface data buffer register buffers the downlink information output.
  • step S940 according to the time division wheel static processing method, the information processing center reads the buffered downlink information from the corresponding (I/O) interface data buffer register and processes it in each time period (slice).
  • I/O Input/output connection at both ends of an information processing device between a local area network and a metropolitan area network
  • the port and the communication method for the LAN user and the metropolitan area network realize the static authorization management of the information processing input/output (I/O) interface of the information processing device, and overcome the restriction of the information processing capability of the input/output (I/O) interface. Basically, it does not occupy processing time (about 0.3%), which eliminates the complicated IP address encoding and communication protocol in data communication and heavy line scheduling burden, and improves information processing efficiency.
  • the WAN that connects the communications between the metropolitan area networks can use the original zone or code.
  • the nodes in the LAN, metropolitan area network, and WAN data communication can no longer use traditional data switches, routers, hubs, etc., and the configuration of the LAN information processing equipment can be greatly reduced under the same transmission performance requirements. System investment costs.
  • a safer data communication mechanism can be established.
  • Each user in the LAN shares an information processing host, shares high-level software support, and shares high-level configuration of main peripheral storage (hard disk), which greatly improves device utilization and enables widespread adoption of computer applications. Establish a new generation of computer applications and data communication systems.
  • LAN static authorization communication system is established, the problem of information congestion in LAN data communication can be better solved.
  • LAN communication is the foundation, which can improve the overall status of network communication.
  • the three networks are integrated, the user terminal is set up, and the high-efficiency comprehensive utilization is realized.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention porte sur un procédé relative à deux interfaces d'E/S d'extrémité d'un dispositif de traitement d'informations permettant: des communications entre des utilisateur d'un RLE et d'un réseau métropolitain, une exploitation complète des performances du dispositif, et offrant l'avantage de données d'E/S de vitesse et capacité élevée, et permettant donc de tirer le meilleur parti des possibilités du dispositif de traitement à grande vitesse d'informations et des données de communication, réduisant les réglages, économisant les investissements et augmentant largement l'efficacité des transmissions.
PCT/CN2007/002270 2006-08-11 2007-07-27 Interfaces d'e/s pour appareil de traitement de messages de rle, et méthode de communication WO2008019574A1 (fr)

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CN1905568A (zh) * 2006-08-11 2007-01-31 华瑞龙腾（北京）信息技术有限公司 局域网的信息处理设备的输入输出接口及通讯方法
CN103310621A (zh) * 2012-03-13 2013-09-18 周治江 智能抄表系统设备地址处理方法

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JPS63316555A (ja) * 1987-06-18 1988-12-23 Nec Corp 交換機の短縮ダイヤル
JPH09186717A (ja) * 1995-12-28 1997-07-15 Nec Corp ファクシミリメール装置
CN1758584A (zh) * 2005-09-29 2006-04-12 王亦兵 频率分配用户接入局域网的系统及上、下行传输方法
CN1784844A (zh) * 2003-05-07 2006-06-07 摩托罗拉公司(在特拉华州注册的公司) 用于通信设备的上行链路调度中的缓冲区占用量
CN1905568A (zh) * 2006-08-11 2007-01-31 华瑞龙腾（北京）信息技术有限公司 局域网的信息处理设备的输入输出接口及通讯方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316555A (ja) * 1987-06-18 1988-12-23 Nec Corp 交換機の短縮ダイヤル
JPH09186717A (ja) * 1995-12-28 1997-07-15 Nec Corp ファクシミリメール装置
CN1784844A (zh) * 2003-05-07 2006-06-07 摩托罗拉公司(在特拉华州注册的公司) 用于通信设备的上行链路调度中的缓冲区占用量
CN1758584A (zh) * 2005-09-29 2006-04-12 王亦兵 频率分配用户接入局域网的系统及上、下行传输方法
CN1905568A (zh) * 2006-08-11 2007-01-31 华瑞龙腾（北京）信息技术有限公司 局域网的信息处理设备的输入输出接口及通讯方法

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