WO2008015499A1

WO2008015499A1 - Method and apparatus for improving probing of devices

Info

Publication number: WO2008015499A1
Application number: PCT/IB2006/054087
Authority: WO
Inventors: Michel Zecri; Cindy Goldberg; Mathieu Fer; Ruth Scott
Original assignee: STMicroelectronics SA; Freescale Semiconductor Inc
Current assignee: STMicroelectronics SA; NXP USA Inc
Priority date: 2006-08-01
Filing date: 2006-08-01
Publication date: 2008-02-07
Anticipated expiration: 2009-02-01

Abstract

A semiconductor device capable of sustaining a probing test of the type carried out during semiconductor device manufacture the device comprising a plurality of semiconductor layers (104) formed in accordance with a predetermined purpose of the device, the device comprising: a passivation layer (110) formed over the uppermost of the plurality of semiconductors layers; a metallic layer (120) to which bonds (126) may be attached and which includes at least one probing region (118) for carrying out said probing tests; characterised in that the metallic layer includes one or more discontinuities (122) in the surface thereof which act to dissipate any forces generated by a probe being applied thereto, such that the effective area over which the force is dissipated is greater than the area of the probe in contact therewith.

Description

Title : Method and apparatus for improving probing of devices

Description

Field of the invention

This invention relates to a method and apparatus for improving the probing tests of chips and other devices, particularly but not exclusively in the domain of Nanometre technology.

Background of the invention

When a chip is produced or manufactured it is normal at a certain point to carry out a probe of the chip to test various aspects of the chip. Normally this probing is carried out by means a metallic probe which is pushed into contact with the probing region of the chip. The probing region is generally in close proximity with the bonding region in the Aluminium (AL) layer above the passivation layer. This probing is known as probe over passivation (POP).

The probing generally includes applying a force to the top Aluminium layer. This may result in cracking in the passivation layer below and sometimes may cause other mechanic (and then electrical) faults in this or other parts of the chip. This type of problem is often exacerbated as the size of the technology and chips continues to diminish.

This problem has been discussed in the domain of micro technology (i.e size -10^" ⁶m) by a number of citations.

US 6563226 B2 (Motorola) describes the use of POP, chip but none of the details relating to the present invention. Similarly US 6717270 (Motorola) describes bond over passivation (BOP) and bond of a activated layer (BOA) and makes reference to probe over a passivation but discloses other POP, BOP and BOA processes than the present invention. US 200005/0121803 A1 relates to an internally reinforced bond pad. The reinforced bond pad has a non planar dielectric structure and a metallic bond layer which conforms with this non-planar dielectric structure. This invention requires a dual inlaid bonding surface (which needs a very complex process with many steps). In addition, this would not reduce any stresses relating to the mismatch in Young's modulus between the bonding surface and the unpatterned underlying dielectric that are caused when probing occurs. In addition, there are suggestions of leaving the dielectric residue on the bonding service which is not a good practice for fine pitch wirebonding as is found in Nanotechnology chips in accordance with the present invention. The ring of dielectric material 26 is provided to prevent the probe from removing other metallic bond layer below, to provide a hard stop to the probe. As there is a hard stop there is much more likelihood of a high pressure being applied. This would mean that this invention actually does not prevent the problem of cracking a passivation layer (which layer is not actually present in this invention). In addition since this is the domain of micro-technology as opposed to nanotechnology there are many different and varied problems and solutions which would be not applicable in order to pattern the waves rings and non planar structures in a nanotechnology environment.

US 6531384 B1 (KOBAYASHI) discloses a so called "armoured" bond pad. This patent teaches a structure having a number of islands of cooper metal 18 extending above the insulation 14. In addition this invention deals with bonding and probing in the same area. This suggests the metal dielectric pattern is an uppermost metal e.g. aluminium would not be compatible with the fine-pitch bond pads and limits bond over activation (BOA) the compatibility because the bonding surface must be electrically connected by underlying metal layers. The alternation of copper islands and passivation provides vertical connectivity. In order to make this alternance of Copper Island And passivation layer requires a number of additional steps of processing which add to the cost and time for making the device. Summary of the invention

One object of the present invention is to provide semiconductor device and a method for making and operating the device as described in the accompanying claims.

Brief description of the drawings

Reference would not be made by other example to the accompanying figures in which:

- Figure 1 a is a cross-sectional diagram of the first embodiment of a chip in accordance with one embodiment of the present invention;

- Figure 1 b is a plan view of figure 1 a in accordance with one embodiment of the present invention;

- Figure 2a is a cross-sectional diagram of a second embodiment of a chip in accordance with one embodiment of the present invention;

- Figure 2b is a plan view of figure 2a in accordance with one embodiment of the present invention; - Figure 3a is a cross-sectional diagram of a third embodiment of a chip in accordance with one embodiment of the present invention;

- Figure 3b is a plan view of figure 4a in accordance with one embodiment of the present invention;

- Figure 4 is cross-sectional diagram of a fourth embodiment of a chip in accordance with one embodiment of the present invention;

- Figure 4b is a plan view of figure 5a in accordance with one embodiment of the present invention;

- Figure 5 is a graph showing details of the impacts of numbers of vias relative to the stress applied to the chip during the probing process in accordance with one embodiment of the present invention.

Referring to figure 1 a, a 45 mm technology active device is shown 100. The device could be produced in on a silicon base and be something such as a MOSFET, a diode, etc. The silicon layer is shown as 102. The device is made up of a plurality of layers of metal and insulator 104, formed with vias and other connections 106 there between as appropriate. The nature and design of the layers would be dependant on the specific nature of the device. The layers of metal would typically be of copper or any other appropriate metal and the layers of insulator would be of any dielectric material as is appropriate to the process and device required metal. The uppermost metal layer or 108 is formed in accordance with the final design of the chip. Then a passivation layer 110 is applied over the surface of the chip and patterned as appropriate to allow bonding to occur in a wire bound region 112. In addition there are patterns 114 and 116 in the region of the probe area 118. An aluminium layer 120, is applied and in the surface of the probe area or probe region 118, a number of passivation vias 122 are patterned. The aluminium layer 120 could be of copper or any other appropriate metal. As can be seen in figure 1 b, the wires may be a plurality of points or situated in grid- like matrix over the probe region.

The probe 124 makes contact with the probing region and a force is applied. Due to the fact that the vias exist underneath the probe not all the stress of the probing is concentrated on one particular point, in fact the maximum stress of the probe is spread overall the areas around the vias. The patterned vias on the probe over passivation space effectively distributes the stress of probing. After the probing process has been carried out and the chip has passed all the necessary test, the wire bond 126 may then be attached to the wire bond region 112.

Referring now figures 2a and 2b, where common reference numbers refer to common elements a further embodiment of the invention is shown. In this embodiment the vias are pattered over both the probe and wire bond regions. This can be useful if any tests are carried out over the wire bond region. Also the pattering is the same for the whole or all a layer 120 which means less complex making of fabrication process may be adopted.

The vias can be shaped in any manner, for example, squares honeycomb, circular etc. The shape size of the holes are configured in such a way that the hole is smaller than the probe tip and so that the tip cannot catch on the edge of the hole. The holes may have for example chamfered or similar edges. In addition, if the general design requirements set out above are met for different shapes of hole, there is no limit to the shape orientation, number etc of the vias.

Figures 3 a and b and figure 4 a and b show two different orientations of a bar passivation via 128 and 130 respectively, formed in the aluminium layer 120. The different orientations are shown as one running transverse 128 and the other longitudinally 130 relative to layer 120. It would also be possible to have bars running in diagonal directions or even in a spiral.

Referring now to figure 5, two graphs 200 and 210 are shown. The first is a graph showing the relationship of width of lines (0,5 - 1 ,5) to maximum stress 212 (dotted line) and average stress 214 (full line) which can appear in the probing process. Similarly the second graph 210 shows the relationship between numbers of vias on the considered area (0-10) and the maximum 212 or average 214 stress appearing in the probing region. It can be clearly seen that the higher the density of vias, the higher the stress sustainable. The aluminium layer 120 may be processed in any appropriate manner on the underside thereof in order to be appropriate to the required function thereof for example, the lower side of the aluminium layer may be of the form shown in co- pending application.

It will be appreciated that the present invention has a number of noteworthy differences from the cited prior art. The present invention relates to nanotechnology and smaller. The problems and solution associated with nano- and smaller technologies are hugely different from micro-technology and other earlier technologies as described in the cited prior art. At different scales of technology the same processes cannot be used as they simply do not work, for example etching and patterning are very much harder for nanotechnology. In addition a probing process in a layer chip could automatically sustain considerably higher intrinsic stresses than the fragile nanotechnology devices. In other words, the lowest attainable stress in probing could be supported by the layer devices but not in the smaller nanotechnology devices. As such one would not encounter the same problems in the two technologies. More fragile devices will need careful management of the forces applied thereto during probing unlike the bigger stronger micro-technology devices.

The invention provides a solid but nonplanar surface of the bond metal layer as a consequence of vias in the underlying dielectric and the improved mechanical integrity of replacing a solid layer of dielectric with these vias. These vias give rise to a spread of any load introduce during probing and therefore give rise to less maximum stress or load at any given point. These results in a stronger more robust chip this is less likely to fracture under the pressure of the probing process. The invention further provides a specific improvement to enable probe over passivation or bond over passivation in a bond over activation technique and give rise to later chip without compromising probe yield and inducing probe damage which may give rise to later chip failures.

It will be appreciate that variations of the invention would remain within the present invention, for example the discontinuities, vias or holes on the upper surface could be formed in many different ways. Also the vias, holes or discontinuities may be made in different layers if appropriate and if the probe test will not impact layers there above.

Claims

1. A semiconductor device capable of sustaining a probing test of the type carried out during semiconductor device manufacture the device comprising a plurality of semiconductor layers (104) formed in accordance with a predetermined purpose of the device, the device comprising:

- a passivation layer (110) formed over the uppermost of the plurality of semiconductors layers;

- a metallic layer (120) to which bonds (126) may be attached and which includes at least one probing region (118) for carrying out said probing tests;

- characterised in that the metallic layer includes one or more discontinuities (122) in the surface thereof which act to dissipate any forces generated by a probe being applied thereto, such that the effective area over which the force is dissipated is greater than the area of the probe in contact therewith.

2. The semiconductor devices of claim 1 , further characterised in that the discontinuities are in the form of vias.

3. The semiconductor device of claim 1 or claim 2, further characterised in that the discontinuities are formed in a grid like pattern.

4. The semiconductor device of anyone of claims 1 to 3, further characterised in that the passivation layer is a dielectric layer.

5. The semiconductor device of anyone of claims 1 to 4, further characterised in that the metallic layer is of aluminium,

6. The semiconductor device of anyone of claims 1 to 5, further characterised in that the probing region is separate from a bonding region to which the bonds may be attached.

7. A method of manufacturing a semiconductor device capable of sustaining a probing test of the type carried out during semiconductor device manufacture the device comprising a plurality of semiconductor layers (104) formed in accordance with a predetermined purpose of the device, the method comprising:

- forming a passivation layer (110) over the uppermost of the plurality of semiconductors layers;

- forming a metallic layer (120) to which bonds (126) may be attached and which includes at least one probing region (118) for carrying out said probing tests;

characterised in that the method comprises forming metallic layer includes one or more discontinuities (122) in the surface thereof which act to dissipate any forces generated by a probe being applied thereto, such that the effective area over which the force is dissipated is greater than the area of the probe in contact therewith..

8. A method of manufacturing a semiconductor device of claim 7, further characterised in that the method comprises forming the discontinuities in the form of vias.

9. A method of manufacturing a semiconductor device of claim 7 or claim 8, further characterised in that the method comprises forming the discontinuities in a grid like pattern.

10. A method of manufacturing a semiconductor device of claim 7 to 9, further characterised in that the method comprises forming the passivation layer as a dielectric layer.

11. A method of manufacturing a semiconductor device of claim 7 to 10, further characterised in that the method comprises forming the metallic layer of aluminium,

12. A method of manufacturing a semiconductor device of claim 7 to 11 , further characterised in that the method comprises forming the probing region separate from a bonding region to which the bonds may be attached.