WO2007123093A1 - Single crystal sapphire substrate - Google Patents
Single crystal sapphire substrate Download PDFInfo
- Publication number
- WO2007123093A1 WO2007123093A1 PCT/JP2007/058299 JP2007058299W WO2007123093A1 WO 2007123093 A1 WO2007123093 A1 WO 2007123093A1 JP 2007058299 W JP2007058299 W JP 2007058299W WO 2007123093 A1 WO2007123093 A1 WO 2007123093A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- sapphire substrate
- single crystal
- crystal sapphire
- heating step
- heating
- Prior art date
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 206
- 229910052594 sapphire Inorganic materials 0.000 title claims abstract description 171
- 239000010980 sapphire Substances 0.000 title claims abstract description 171
- 239000000758 substrate Substances 0.000 title claims abstract description 169
- 238000000034 method Methods 0.000 claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 claims abstract description 46
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims description 190
- 239000000463 material Substances 0.000 claims description 16
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 16
- 230000003746 surface roughness Effects 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 230000007547 defect Effects 0.000 abstract description 12
- 238000010420 art technique Methods 0.000 abstract 2
- 238000004020 luminiscence type Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 24
- 238000005498 polishing Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 16
- 239000010408 film Substances 0.000 description 16
- 239000010410 layer Substances 0.000 description 16
- 238000005259 measurement Methods 0.000 description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 10
- 238000001228 spectrum Methods 0.000 description 10
- 239000010409 thin film Substances 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- 238000005520 cutting process Methods 0.000 description 8
- 238000001459 lithography Methods 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 229910021529 ammonia Inorganic materials 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 238000000348 solid-phase epitaxy Methods 0.000 description 5
- 238000000927 vapour-phase epitaxy Methods 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- -1 and in principle Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 235000005811 Viola adunca Nutrition 0.000 description 2
- 240000009038 Viola odorata Species 0.000 description 2
- 235000013487 Viola odorata Nutrition 0.000 description 2
- 235000002254 Viola papilionacea Nutrition 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 150000003839 salts Chemical class 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 150000003682 vanadium compounds Chemical class 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- YBNMDCCMCLUHBL-UHFFFAOYSA-N (2,5-dioxopyrrolidin-1-yl) 4-pyren-1-ylbutanoate Chemical compound C=1C=C(C2=C34)C=CC3=CC=CC4=CC=C2C=1CCCC(=O)ON1C(=O)CCC1=O YBNMDCCMCLUHBL-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910005900 GeTe Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910002665 PbTe Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241001315609 Pittosporum crassifolium Species 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910007657 ZnSb Inorganic materials 0.000 description 1
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229940058905 antimony compound for treatment of leishmaniasis and trypanosomiasis Drugs 0.000 description 1
- 150000001463 antimony compounds Chemical class 0.000 description 1
- ROTPTZPNGBUOLZ-UHFFFAOYSA-N arsenic boron Chemical compound [B].[As] ROTPTZPNGBUOLZ-UHFFFAOYSA-N 0.000 description 1
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229940065285 cadmium compound Drugs 0.000 description 1
- 150000001662 cadmium compounds Chemical class 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 229910052792 caesium Inorganic materials 0.000 description 1
- 229910000019 calcium carbonate Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- LBJNMUFDOHXDFG-UHFFFAOYSA-N copper;hydrate Chemical compound O.[Cu].[Cu] LBJNMUFDOHXDFG-UHFFFAOYSA-N 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 150000002259 gallium compounds Chemical class 0.000 description 1
- UPWPDUACHOATKO-UHFFFAOYSA-K gallium trichloride Chemical compound Cl[Ga](Cl)Cl UPWPDUACHOATKO-UHFFFAOYSA-K 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 150000002291 germanium compounds Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 150000004679 hydroxides Chemical class 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 150000002472 indium compounds Chemical class 0.000 description 1
- 238000004969 ion scattering spectroscopy Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002611 lead compounds Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229940100890 silver compound Drugs 0.000 description 1
- 150000003379 silver compounds Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 150000003568 thioethers Chemical class 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 150000003752 zinc compounds Chemical class 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B19/00—Liquid-phase epitaxial-layer growth
- C30B19/12—Liquid-phase epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
- C30B29/20—Aluminium oxides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
- C30B23/025—Epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
- C30B29/406—Gallium nitride
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
- H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
Definitions
- the present invention is suitable for forming elements such as LEDs (Light Emitting Diodes), LDs (Laser Diodes), HEMTs (High Electron Mobility Transistors), FETs (Field Effect Transistors), and SOS (Silicon-ON-Sapphire).
- the present invention relates to a method for manufacturing a single crystal sapphire substrate having crystal quality and surface condition.
- Gallium nitride (GaN) crystals used for blue and white LEDs are sapphire (Al 2 O 3) and silicon carbide (SiC)
- sapphire substrates have recently become widely used because they have been mass-produced in recent years and are thermally and chemically stable. Single crystal sapphire substrates are also used as substrates for manufacturing various electronic devices, not just LEDs.
- a GaN crystal or the like is grown on a single crystal sapphire substrate, it is generally performed at an angle of about 0.01 to 2.0 degrees with respect to the C plane of the sapphire crystal.
- the resulting GaN crystal becomes a crystal with many crystal defects and unevenness. Therefore, as shown in Fig. 1, by using a single crystal sapphire substrate in which the surface of the sapphire single crystal is inclined at a predetermined angle with respect to the C plane, a GaN crystal having a flat surface with few crystal defects can be obtained. (Patent Document 1).
- the surface of the sapphire substrate is formed in microscopic steps as shown in FIG. The higher the regularity of this step shape, the more powerful GaN crystals grow on the substrate.
- Patent Document 1 JP 2002-293692 A
- Non-Patent Document 1 SASAKI Atsushi, HARA Wakana, MATSUDA Akilumi, AKIBA Shusak u, TATEDA Norihiro, YOSHIMOTO Mamoru, Nucl Instrum Methods Phys Res Sect B, VOL. 232 NO. 1-4; PAGE. 305-311; (2005/05).
- the present invention provides a single crystal sapphire substrate having a step shape and a flatter terrace surface than a conventional single crystal sapphire substrate, and a method for manufacturing the same.
- the first invention is a single crystal sapphire substrate in which a regular step having a terrace surface is formed on the single crystal sapphire surface, and the macro surface roughness (Ra) of the substrate is 0. Inm.
- the terrace surface roughness (Ra) is 0.03 nm or less, the step height is 0.3 Inm or more and 0.3 nm or less, and the difference between the maximum and minimum terrace width is 500 nm or less.
- a single crystal sapphire substrate is provided.
- the second invention provides a single crystal sapphire substrate in which the macroscopic surface of the single crystal sapphire substrate is inclined at an angle of 0.1 to 0.6 degrees with respect to the main surface.
- a third invention provides a single-crystal sapphire substrate configured such that oxygen atoms terminate on a terrace surface to form a monoatomic layer of oxygen.
- a fourth invention includes a vacuum heating step of heating the single crystal sapphire substrate in a vacuum atmosphere, a first atmospheric heating step of heating the sapphire substrate taken out after the vacuum heating step in an atmospheric atmosphere, and a first atmosphere After the heating step, there is provided a method for manufacturing a single crystal sapphire substrate comprising a second atmospheric heating step in which the furnace temperature is raised and further heated. Provide.
- the fifth invention includes a vacuum heating step for heating the single crystal sapphire substrate in a vacuum atmosphere, and a first atmosphere for heating the sapphire substrate taken out after the vacuum heating step at a low temperature in a component atmosphere contained in the atmosphere.
- a method for producing a single crystal difference sapphire substrate comprising: a heating step; and a second atmospheric heating step in which, after the first atmospheric heating step, the furnace temperature is raised and further heated in a component atmosphere contained in the atmosphere. To do.
- the heating temperature in the vacuum heating step is 1000 ° C or higher and 1300 ° C or lower
- the holding time is 2 hours or longer
- the heating temperature in the first atmospheric heating step is 800 ° C or higher.
- Single crystal sapphire having a temperature of 1 ° C or less, a holding time of 2 hours or more and 5 hours or less, a heating temperature of the second atmospheric heating step of 1300 ° C or more and 1600 ° C or less, and a holding time of 1 hour or more and 5 hours or less.
- a seventh invention provides an electronic device manufacturing method for manufacturing an electronic device by epitaxially growing an electronic device material on a surface side including a terrace surface of a single crystal sapphire substrate.
- An eighth invention provides a method of manufacturing an electronic device, wherein the electronic device material is gallium nitride.
- a ninth invention provides an electronic device intermediate structure in which an electronic device material is epitaxially grown on a surface side including a terrace surface using a single crystal sapphire substrate. The invention's effect
- the single crystal sapphire substrate of the present invention By using the single crystal sapphire substrate of the present invention, it is possible to obtain a crystal film having a flatter terrace surface and few crystal defects. Further, it is possible to obtain a GaN crystal film having a flat surface and few crystal defects, and this GaN crystal film exhibits better light emission characteristics when used as a light emitting device. Further, according to the method for producing a single crystal sapphire substrate of the present invention, the tilt angle of the sapphire single crystal surface can be precisely controlled, and a single crystal sapphire substrate suitable for the purpose can be obtained with certainty.
- the first embodiment will mainly describe claims 1, 2 and 3.
- the second embodiment will mainly describe claim 4.
- the third embodiment will mainly describe claims 5, 6, 7, 8, and 9.
- Embodiment 4 will mainly describe claims 10, 11 and 12.
- Embodiment 1 Concept>
- the single crystal sapphire substrate of the present embodiment controls the surface roughness of the substrate, the shape of the steps, etc., and improves the quality of the crystal grown on the substrate.
- FIG. 2 is a diagram schematically showing a macroscopic surface of a single crystal sapphire substrate.
- regular steps having a flat terrace surface (0201) are formed on the single crystal sapphire surface.
- the terrace surface (0201) is the larger part of the flat part of the substrate surface
- the step surface (0202) is the smaller part of the flat part of the substrate surface, that is, one terrace surface and it. It is a surface that connects the following terrace surface. As shown in Fig.
- the vertical distance between one terrace surface and the following terrace surface is the step height (h)
- the horizontal distance between the terrace surface and the subsequent terrace surface is the terrace width (w)
- the angle between the terrace surface and the end line (0203) of the macroscopic surface of the single crystal sapphire substrate is called the offset angle ( ⁇ ).
- the edge (0204) t is the angle at which the glass surface and the step surface meet.
- Single crystal sapphire is made of sapphire (a Al O), ideally sapphire
- FIG. 3 shows a unit cell of a sapphire single crystal.
- a sapphire single crystal has a hexagonal crystal structure. Hexagonal crystal with C-plane (Miller index notation: (0001)) and side-faced (Mira one-index notation: 10-10)) (Miller index minus sign notation method should be written above the number However, here, the minus sign is written in front of the numbers for the sake of simplicity), and the hatched surface is the ⁇ surface (Miller index notation: 11 20)) and R surface (Miller index notation: 10—12) ) [0022]
- the characteristics of the single crystal sapphire substrate of the present embodiment are as follows.
- the surface roughness (Ra) of the substrate is 0.1 nm or less.
- the surface roughness (Ra) is expressed by Equation 1 where f (X) is the height of an arbitrary line (length L) on the substrate surface relative to the average line at X.
- the surface roughness of the substrate is the roughness of the entire substrate surface and is different from the surface roughness of a specific terrace surface described later. In other words, when measuring the surface roughness of the substrate, it is better to measure the surface height in the X direction in Fig. 2.
- the surface roughness (Ra) of the terrace surface is 0.03 nm or less.
- the surface roughness of the terrace surface is the surface roughness of a specific terrace surface. Therefore, when measuring the surface roughness of the terrace surface, the surface height should be measured in the y direction in Fig. 2.
- the step height is 0.1 nm or more and 0.3 nm or less.
- the step height is preferably the distance between the oxygen atomic layer and the adjacent aluminum atomic layer (about 0.22 nm). This height is also the force that becomes the minimum unit of the step height.
- the step height is the distance between the oxygen atomic layer and the adjacent aluminum atomic layer.
- the difference between the maximum value and the minimum value of the terrace width is 500 nm or less. That is, it is necessary that the edge of the terrace surface has a shape close to a straight line.
- the crystal surface of GaN or the like grown on the substrate surface can be flattened and the dislocation density can be reduced.
- the terrace surface is parallel to the main surface.
- the main surface is one of the C-plane, A-plane, M-plane, and R-plane of the sapphire single crystal. This is because the terrace surface is parallel to the main surface because it is the most stable in terms of energy.
- the macroscopic surface force of the single crystal sapphire substrate is preferably inclined at an angle of 0.1 degree force 0.6 degree with respect to the main surface. Further, it is more preferable that the main surface is inclined with respect to a specific direction rather than with respect to an arbitrary direction. For example, when the main surface is the C surface, it is preferable that the 0.1 degree force is inclined at an angle of 0.6 degrees when directed from the C surface toward the A surface direction or the M surface direction.
- FIG. 4 is a diagram illustrating a macroscopic surface. As shown by the dotted line in Fig. 4, the macroscopic surface represents the average surface when the single crystal sapphire substrate is viewed macroscopically. If the tilt angle is 0.1 degrees or less, the step surface and the terrace surface cannot be clearly formed. If the tilt angle is 0.6 degrees or more, the step height is required to be 0.3 nm or more, and the step is good. Not formed.
- Embodiment 1 Example>
- FIG. 5 shows an example of an AFM measurement result of a single crystal sapphire substrate with the C-plane as the main surface of the present embodiment.
- the single crystal sapphire substrate of this embodiment has steps with a uniform shape.
- the surface roughness of the terrace surface was 0.013 nm
- the terrace width was 400 to 600 nm
- the step height was about 0.2 nm.
- an epitaxial film having a flat surface and a low dislocation density can be obtained.
- An epitaxial film with good crystallinity shows good light emission characteristics even when used as a light emitting element.
- Embodiment 2 Overview>
- the sapphire single crystal of this embodiment is characterized in that the substrate surface is composed of oxygen atoms, and the oxygen atoms are regularly arranged. As a result, it is possible to form an epitaxial film with good crystallinity on the sapphire substrate.
- the single crystal sapphire substrate of the present embodiment is configured such that oxygen atoms terminate on the terrace surface to form a monoatomic layer of oxygen.
- the oxygen atom ends here
- the structure in which an oxygen monoatomic layer is formed is considered to form an oxygen monoatomic layer if aluminum atoms are exposed on the surface due to crystal defects or manufacturing errors in the manufacturing process. This is because perfect crystals are theoretically difficult to manufacture industrially. In addition, these crystal defects and the degree of error in the manufacturing process cause the product yield to deteriorate, but if the concept of discarding defective products is used, the defects and defects are within a certain extent within the range of commercial rationality. Permissible.
- the single crystal sapphire substrate of this embodiment is composed of a C-plane (mirror index notation: (0001)) whose terrace surface is a sapphire crystal.
- Figure 6 shows a conceptual diagram of the sapphire crystal. In the figure, aluminum atoms are omitted for the force oxygen atoms indicated by black circles because the figure becomes complicated.
- the sapphire crystal has a regular octahedral structure with oxygen atoms at the apexes as shown in Fig. 6 (a) or (b).
- (A) is a regular octahedral structure composed only of oxygen atoms
- (b) is a regular octahedral structure having aluminum atoms in the regular octahedral structure.
- a large number of sapphire crystals constitute a sapphire crystal.
- the surface indicated by the oblique lines in (c) is a surface constituting a part of the C surface of the sapphire crystal.
- a terrace surface is constituted by the C surface.
- the crystal grown on the sapphire substrate is greatly influenced by the atoms located on the outermost surface of the sapphire crystal. Therefore, first, the outermost surface of the single crystal sapphire substrate was examined.
- Figure 7 shows the atoms on the outermost surface from the top in the C-plane direction, which is the outermost surface of the single crystal sapphire substrate.
- the triangle indicated by the diagonal line in Fig. 7 corresponds to the one side indicated by the diagonal line in the octahedral structure of the sapphire crystal shown in Fig. 6.
- the hexagon (0701) shown in Fig. 7 corresponds to the C-plane part of the hexagonal column shown in Fig. 3.
- FIG. 8 shows a cross-sectional view taken along the line A—B (0702) shown in FIG. 7 (that is, the A plane (Miller index notation: (11 20))) and viewed from the direction of the arrow.
- the atomic layer on the outermost surface also has a monoatomic layer force consisting of only oxygen atoms.
- Figure 9 shows a cross-sectional view of the terrace surface and steps formed in the same direction as in Fig. 8.
- the edge of the step has an obtuse angle, an acute angle, or a right angle, as shown in (a), (b), or (c), depending on the cutting angle and the conditions during polishing and heat treatment. Also, as shown in (d) May have either an obtuse angle or a right angle.
- the surface composed of straight lines connecting only oxygen atoms is assumed to have oxygen atoms terminated or outermost in any case. Therefore, in the single crystal sapphire substrate of the present embodiment, the terrace surface is formed by the C surface, and the surface is composed only of oxygen atoms.
- the step surface is also composed of oxygen atoms, and in principle, aluminum atoms are not arranged on the surface.
- Embodiment 2 Example>
- LEISS low-energy ion scattering spectroscopy
- LEISS can measure the composition and arrangement of surface atoms of a crystal and is an analytical technique used for crystal evaluation.
- LEISS irradiates the sample surface with a low-energy ion beam, detects scattered ions, and measures changes in the energy spectrum.
- By changing the energy spectrum of the scattered ions detected by changing the incident angle and the incident direction of the ion beam and changing the atomic arrangement as seen from the irradiation direction of the ion beam Measure the atomic arrangement of the material.
- Scattered ions are detected by a time-of-flight measuring device installed coaxially with the ion source.
- the time-of-flight measurement device qualifies atoms to be irradiated.
- measurement was performed by irradiating a helium ion pulse as an incident ion beam.
- the spectrum measured by LEISS is compared with the simulation result obtained by calculation based on the atomic arrangement in the ideal form of the crystal, and the arrangement position of the atom is estimated and evaluated by the position and intensity where the peak appears. Is done.
- Fig. 10 shows the spectrum results of measuring the single crystal sapphire substrate with the main surface of the present embodiment as the C-plane by LEISS.
- the spectrum shown at the bottom is the simulation result obtained based on the ideal atomic arrangement of the C-plane of the sapphire crystal. Comparing the spectrum obtained from the single crystal sapphire substrate force of this embodiment with the spectrum obtained by simulation, the spectrum and peak detection position force of the incident azimuth angle ranged from 30 degrees to 360 degrees. Crystal sapphire substrate and spatter obtained by simulation Are detected at almost the same angle.
- the “shoulder” of the peak seen in the simulation results is detected as a small peak or “shoulder” in the single crystal sapphire substrate of this embodiment. It can be seen that a single crystal sapphire substrate having an atomic arrangement very close to the ideal shape is obtained.
- Fig. 25 shows the spectrum results of the single crystal sapphire substrate measured by LEISS when the principal surface is the A-plane.
- the LEISS measurement Heon is irradiated at an angle of 15 degrees to the substrate, and the sapphire substrate to be measured is rotated 360 degrees. In this case, if it is an ideal A-plane, the measurement results have a periodic peak every 180 degrees.
- peaks (c) and (d) appear at an angle shifted by 180 degrees with respect to peaks (a) and (b), which are periodic peaks every 180 degrees. .
- these results show the same spectrum as when the LEISS measurement was performed on the orientation flat of the substrate, and the results for the substrate with the sapphire substrate force A surface shown in Fig. 25 as the main surface. It shows that there is.
- an epitaxial film having a flat surface and a low dislocation density can be obtained.
- An epitaxial film with good crystallinity shows good light emission characteristics even when used as a light emitting element.
- the present embodiment relates to a heat treatment method for a single crystal sapphire substrate of Embodiment 1 or 2.
- heat treatment methods There are two types of heat treatment methods: a heat treatment method that has a three-step force of a vacuum heating step, a first atmospheric heating step, and a second air heating step, and a heat treatment method that has a two-step force of a vacuum heating step and an atmospheric heating step. is there.
- the heat treatment method includes a heat treatment method having three steps of a vacuum heating step, a first atmospheric heating step, and a second atmospheric heating step, and a vacuum heating step.
- a heat treatment method consisting of two steps, an atmospheric heating step.
- FIG. 11 and FIG. 12 show an example of a heating furnace that performs the heat treatment of the present embodiment.
- Fig. 11 shows a vacuum heating furnace that performs the vacuum heating step of the heat treatment method with three-stage and two-stage power.
- the heating furnace (1101) is heated by the heating element (1102).
- the sample is carried into and out of the heating furnace as the sample stage (1103) moves up and down from below the sample carry-in / out port (1104).
- the heated sample is set on the sample table while the sample table is lowered, and the sample table is moved in the direction of the arrow and is carried into the heating furnace. Conversely, when unloading, move the sample table in the direction opposite to the arrow and unload it.
- a cryopump (1105) and a vacuum pump (1106) are attached to the heating furnace, and the inside of the heating furnace is depressurized by the vacuum pump. In order to raise the degree of vacuum, a cryopump for cooling is provided. These controls are performed by the control device (1107).
- FIG. 12 shows an atmospheric heating furnace that performs a first atmospheric heating step and a second atmospheric heating step of a heat treatment method having a three-stage force, and an atmospheric heating step of a heat treatment method having a two-stage force.
- the Karo heating furnace (1201) is heated by the heating element (1202).
- the sample is loaded and unloaded from the sample loading / unloading port (1203).
- a control device (1204) for temperature control and the like is provided to the right of the sample loading / unloading port.
- the first and second air heating steps of the heat treatment method with a three-stage force, and the air heat step of the heat treatment method with a two-step force are performed in an air atmosphere or a component atmosphere contained in the air.
- a flow meter (1205) is provided to check the flow rate of the incoming air.
- heat treatment is first performed in the vacuum heating furnace of FIG. 11, and after the heat treatment is completed, heat treatment is performed in the air atmosphere of the air heating furnace of FIG. I do.
- FIG. 13 is a diagram illustrating the flow of heat treatment that also has a three-stage force according to this embodiment.
- the heat treatment method for the single crystal sapphire substrate according to the present embodiment also includes a vacuum heating step (S1301), a first atmospheric heating step (S1302), and a second atmospheric heating step (S1303). These heat treatments are performed after manufacturing the single crystal sapphire ingot, followed by slicing and polishing, in order to secure a complete crystal layer on the surface of the single crystal sapphire substrate.
- the vacuum heating step (S1301) the single crystal sapphire substrate is heated in a vacuum atmosphere.
- the purpose of the vacuum heating step is to remove excess oxygen before the alumina sublimation temperature and to vaporize impurities such as sulfides, chlorides and hydroxides mixed during the polishing operation above the melting point.
- the heating temperature in the vacuum heating step is preferably 1600 ° C or more and 2000 ° C or less, and the holding time is preferably 2 hours or more. This is because when the heating temperature is 1600 ° C or lower or the holding time is less than force time, the single crystal sapphire substrate is greatly deformed when the heating temperature is 2000 ° C or higher, at which impurities are not sufficiently removed.
- the atmospheric pressure in the vacuum atmosphere is preferably 10 " 5 Torr or less U. If the atmospheric pressure is higher than this, the effect of removing impurities is reduced.
- the sapphire substrate taken out after the vacuum heating step (S 1301) is heated at a low temperature in an atmospheric atmosphere or a component contained in the atmospheric air.
- the purpose of the first atmospheric heating step is to acidify and remove carbon as diacid carbon. Low-temperature heating in the atmosphere and components contained in the atmosphere is sufficient if the atmosphere contains sufficient oxygen to oxidize carbon to carbon dioxide.
- the heating temperature of the first atmospheric heating step is preferably 800 ° C. or higher and 1000 ° C. or lower, and the holding time is 2 hours or longer and 5 hours or shorter.
- the furnaces used for the vacuum heating step (S1 301) and the first atmospheric heating step (S1302) are preferably different furnaces.
- the furnace temperature is raised and further heated.
- the second air heating step is performed in an air atmosphere or in a component contained in the air. In this step, the steps on the surface of the single crystal sapphire substrate can be regularly arranged.
- the heating temperature in the second atmospheric heating step is preferably 1000 ° C. or higher and 1300 ° C. or lower, and the holding time is preferably 1 hour or longer and 5 hours or shorter.
- the steps do not align when the calo heat temperature is 1000 ° C or less or the holding time is 1 hour or less, and the single crystal sapphire substrate is deformed when the calo heat temperature is 1300 ° C or more or the holding time is 5 hours or more. .
- the first atmospheric heating step (SI 302) and the second atmospheric heating step (SI 303) since the temperature distribution depending on the loading position occurs when the substrate is affected by the air flow, the substrate is fixed in the holder. Above, it is better to seal with a sapphire block.
- the temperature and holding time are varied within the above range according to the tilt angle of the substrate. If the temperature and holding time are out of the above ranges, the step height uniformity and straightness, the flatness of the terrace surface will be impaired, and aluminum atoms will be associated with each other. The correct arrangement may be lost.
- FIG. 14 is a diagram illustrating the flow of heat treatment that also has a two-stage force in the present embodiment.
- the heat treatment method for the single crystal sapphire substrate of the present embodiment consists of a vacuum heating step (S1401) and an atmospheric calorie heating step (S1402). These heat treatments are performed after slicing and polishing after the production of the single crystal sapphire ingot.
- the single crystal sapphire substrate is heated in a vacuum atmosphere.
- the heating temperature in the vacuum heating step is preferably 1600 ° C or more and 2000 ° C or less, and the holding time is preferably 2 hours or more.
- the pressure of the vacuum atmosphere is preferably 10 _ 5 Torr or less, as in the heat treatment method with three-stage force.
- the sapphire substrate taken out after the vacuum heating step (S 1401) is heated in an air atmosphere or a component contained in the air.
- the heating temperature in the atmospheric heating step is preferably 1200 ° C to 1400 ° C, and the holding time is 1 hour to 5 hours.
- the heat treatment in the air atmosphere and the components contained in the air may be performed in an atmosphere containing sufficient oxygen to oxidize carbon to diacid-carbon.
- the atmospheric heating step is performed in an air atmosphere or in a component contained in the air, and regularly arranges steps on the surface of the single crystal sapphire substrate.
- FIG. 15 shows an example of a specific example of the heat treatment method having a three-stage force according to this embodiment.
- a three-stage heat treatment method will be described.
- the vacuum heating step Raise the temperature from room temperature (RT) to 1700 ° C over 7 hours. Hold the temperature at 1700 ° C for 2 hours after raising the temperature, and then lower the temperature to room temperature over 12 hours after holding.
- the superheating furnace is changed from the vacuum heating furnace to the atmospheric heating furnace.
- the temperature is raised from room temperature to 900 ° C over 4 hours and held at 900 ° C for 3 hours. Allow to cool to room temperature over 6 hours after holding.
- the heating furnace may be changed to another atmospheric heating furnace, or the same heating furnace may be used as it is.
- the second heating step first, the temperature is raised from room temperature to 1200 ° C over 5 hours and held at 1200 ° C for 2 hours. After holding, the temperature is lowered to room temperature over 10 hours to complete the heat treatment.
- the temperature of the second atmospheric heating step may be started after the temperature is once lowered to room temperature (RT) as shown in (a). Then, as shown in (b), after the first atmospheric heating step, the temperature increase in the second atmospheric heating step may be started without lowering the temperature.
- FIG. 16 shows an example of a specific example of the heat treatment method having a two-step force according to this embodiment.
- the temperature is raised from room temperature (RT) to 1700 ° C over 7 hours. After raising the temperature, hold it at 1700 ° C for 2 hours and let it cool down to room temperature over 12 hours.
- the vacuum calorie heat step the superheater is changed from a vacuum furnace to an atmospheric furnace.
- the atmospheric heating step the temperature is raised from room temperature to 1300 ° C over 5 hours and held at 1300 ° C for 4 hours. After holding, the temperature is lowered to room temperature over 10 hours to complete the heat treatment.
- the temperature increase rate and the temperature decrease rate are changed according to the performance of the heating furnace to be used.
- FIG. 17 shows an AFM measurement image of the surface of the single crystal sapphire substrate obtained by the three-stage heat treatment method of the present embodiment.
- a) is a single crystal sapphire substrate before heat treatment.
- the edge of the terrace surface is a curve where the interval between the terrace surfaces is not constant.
- b) is obtained.
- the terrace surface has almost constant intervals, and the edge of the terrace surface is also composed of a linear force.
- c) shows an image of the surface of the single-crystal sapphire substrate obtained by the conventional technique described in Non-Patent Document 2.
- the edge of the terrace surface is curved and the interval between the terrace surfaces is not constant.
- the surface is the same as that of the single crystal sapphire substrate before the bright heat treatment method. Therefore, by carrying out the heat treatment method of the present embodiment, a single crystal sapphire substrate having a straight line and step surfaces with a constant interval could be obtained by a method suitable for mass production.
- Embodiment 4 Overview>
- an electronic device or an intermediate structure of an electronic device is manufactured by epitaxially growing an electronic device material on the single crystal sapphire substrate.
- the electronic device manufacturing method of this embodiment manufactures an electronic device by epitaxially growing an electronic device material on the surface side including the terrace surface of the single crystal sapphire substrate.
- Epitaxial growth is a method of forming a new crystal layer by aligning the crystal direction with the crystal on the surface of a single crystal substrate, which has been intensively produced in the thin film growth technology. . Since crystal growth by epitaxy can be performed at a temperature lower than the melting point of the crystal, it is used as a means for producing a high-purity crystal with few impurities.
- a target crystal film is epitaxially grown using a crystal of a base substrate as a single crystal sapphire substrate.
- Epitaxial growth methods include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and solid phase epitaxy (SPE). There are methods such as Phase Epitaxy).
- Unit elements include silicon (Si), germanium (Ge), and selenium (Se), and compounds include zinc compounds (ZnO, ZnS, ZnSb), barium oxide (BaO), and cadmium compounds (CdS).
- CdSe gallium compounds (GaN ⁇ GaAs), indium compounds (InP, InAs, InSb), germanium compounds (GeTe), lead compounds (PbS, PbSe, PbTe), vanadium compounds (VO), antimony compounds (Sb Te ), Bismuth
- SiC silver compounds
- AgSbTe AgBiS
- These electronic device materials are epitaxially grown on a single crystal sapphire substrate, and diodes (LEDs and LDs), transistors (such as HEMDTs and FETs), ICs, LSIs, photoelectric devices, and rectifiers as shown in Figure 18 Processed into elements, hot cathodes, piezoelectric elements, lasers, Hall elements, thermoelectric elements, varistors, thermistors, etc. It is also possible to manufacture SOS (silicon-ON-Sapphire).
- gallium nitride is attracting attention as it is used for blue-violet diodes and white diodes.
- gallium nitride semiconductors blue-violet diodes have been put into practical use, and full-color displays using light-emitting diodes have been born.
- it is expected to be used as a light source with low power consumption to replace ultraviolet lamps by emitting ultraviolet light and combining with white phosphors.
- This gallium nitride is the same semiconductor as the gallium arsenide (GaAs), which has been put to practical use as an ultra-high frequency transistor, and has the same group 3 and 5 elemental power. For this reason, in addition to ultrahigh frequency transistors that have made the most of the high carrier mobility of gallium arsenide and gallium nitride, gallium nitride is being considered for use in devices capable of high power operation.
- An electronic device is generally manufactured by a process as shown in FIG.
- Electronic device manufacturing consists of four processes: a substrate manufacturing process (1901), a mask manufacturing process (1902), a wafer process (1903), and a thread-and-stand process (1904).
- the substrate manufacturing process also has four process forces: a substrate manufacturing process (1916), a slicing process (1917), a polishing process (1918), and a heat treatment process (1919).
- a substrate manufacturing process (1916) is performed to manufacture an ingot such as single crystal sapphire, which is a base of an electronic device substrate.
- Ingots with single-crystal sapphire power are produced by crystal growth methods such as the Chiyoklarsky method (CZ method) and the Kilopros method (kyropoulusu method).
- An ingot is a cylindrical mass of crystals that serve as a substrate, approximately 2 meters in length and 8 to 12 inches in thickness. These dimensions are for the purpose of electronic devices and on a single wafer. Vary depending on the number of electronic devices created.
- a slicing step (1917) for cutting the single crystal sapphire ingot into a thin plate-like wafer is performed.
- the ingot is cut into a disk shape with a thickness of about 1 mm.
- the blade saw method is shown in Fig. 20 a).
- the ingot (2002) is cut by rotating the inner peripheral blade (2001) of high hardness stainless steel.
- the feature is that the flatness of the cut surface is good.
- ingots (2004) are cut while the diamond particles on the slurry are passed through a plurality of tensioned piano wires (2003) and reciprocating the piano wires.
- the wire saw method has the same flatness of the cut surface as the blade saw method, but is advantageous in terms of cost because the slice speed is high, and is advantageous for manufacturing large-diameter wafers.
- the ingot When cutting an ingot made of a single crystal sapphire cover, if the ingot is fixed with glass or carbon as a holding material, the ingot may be displaced with respect to the cutting direction. Therefore, by using hard calcium carbonate as the material of the holding material, it is possible to keep the deviation of the cutting angle within 0.01 degrees.
- the next step is a polishing step (1918).
- the polishing process first, the side surface of the wafer is polished by mechanical polishing.
- polishing is performed using a polishing liquid of an abrasive with a fine particle size.
- mirror polishing which is polishing of the cross section cut in the slicing process, is performed.
- the mirror polishing is performed by the apparatus shown in FIG.
- the polishing head (2104) attached with the wafer (2103) is brought into contact with the polishing pad (2102) affixed on the rotating surface plate (2101) with a constant pressure to polish the wafer.
- the polishing agent is a slurry-like polishing liquid.
- the wafer that has undergone the polishing step is subjected to a heat treatment step after washing.
- the heat treatment process is performed in order to secure a complete crystal layer near the surface of the wafer that also has a single crystal sapphire force.
- the detailed heat treatment method in the heat treatment step has been described in Embodiment 3, and will be omitted.
- a circuit is first designed (1905), and then a circuit pattern for designing the designed circuit on the wafer is designed (1906). Then, a mask for transferring the designed pattern onto the wafer is manufactured (1907).
- the mask is used in a lithography process for transferring the circuit onto the thin film.
- the mask has a circuit formed on the thin film with chromium or the like on the surface of the quartz plate.
- a wafer process which is a process for forming a circuit on the wafer.
- the wafer process consists of a substrate process (1908) and a lithography process (19 09)
- the wiring process (1910) has three major process forces. The substrate process, the lithography process, and the wiring process are repeated several times depending on the complexity of the target electronic device, as shown in FIG.
- the substrate process also has process powers such as a cleaning process (2201), a heat treatment process (2202), an impurity introduction process (2203), a film formation process (2204), and a flattening process (2205).
- process powers such as a cleaning process (2201), a heat treatment process (2202), an impurity introduction process (2203), a film formation process (2204), and a flattening process (2205).
- the cleaning process is a process for surface cleaning that is always performed between each process including the lithography process and the wiring process.
- cleaning is often performed using a combination of chemicals such as sulfuric acid, hydrochloric acid, ammonia, hydrogen fluoride, and hydrogen peroxide.
- the object of removal by washing is organic residue, oxide residue, metal contamination and so on. In some cases, removal of damage such as crystal defects may also be a cleaning step.
- the heat treatment step is not necessarily a step that must be performed, which is an essential step in the case of a silicon substrate or the like.
- a very clean furnace is used for the heat treatment process, and a carefully cleaned wafer is used.
- heat treatment several hundreds of oxide films are formed on the wafer surface. This film becomes an insulating film and is the starting point for semiconductor device manufacturing using silicon.
- the impurity introduction step is a technique for introducing a trivalent or pentavalent element such as boron arsenic or phosphorus as an impurity into a silicon substrate or the like to form a pn bond or control the impurity concentration.
- Impurity introduction methods include ion implantation, thermal diffusion, and ion doping.
- ion implantation is the mainstream. In the ion implantation method, ions such as boron and arsenic phosphorus separated in a vacuum are accelerated by applying a high voltage and implanted into a substrate.
- VPE vapor phase epitaxy
- MBE molecular beam epitaxy
- LPE liquid phase epitaxy
- SPE solid phase epitaxy
- Solid Phase Epitaxy is a process of epitaxially growing various substances to form thin films.
- Figure 23 shows a schematic diagram of an example of an epitaxial growth method of GaN crystals on a single crystal sapphire substrate by the halogen vapor phase epitaxy (HVPE), which is one of the vapor phase growth methods.
- HVPE halogen vapor phase epitaxy
- the metal-organic vapor phase growth method Metal-organic vapor phase growth method
- MOVPE Epitaxy
- metallic gallium held at a high temperature of about 900 ° C and a hydrogen chloride gas are reacted in an internal reaction tube to mainly produce gallium chloride, and a single unit maintained at about 1000 ° C.
- a GaN crystal is grown by reacting with ammonia near the crystal sapphire substrate.
- Ammonia and hydrogen chloride are supplied with the carrier gas.
- it is essential to control the temperature at two locations, the salt gallium generator and the single crystal sapphire substrate, and the flow rate control of the salt hydrogen gas and ammonia.
- MOV PE method generally, only a single crystal sapphire substrate is heated to about 1000 ° C by a substrate heating heater, and there is an organic metal compound, which is a compound of gallium and an organic material, and nitrogen.
- the raw ammonia is transported with the carrier gas, and GaN crystals grow. In this case, only the single crystal sapphire substrate needs heating and temperature control.
- the flattening process is a process in which unevenness on the wafer surface is eliminated and a uniform surface shape is obtained.
- the flattening process is an exposure process in the lithography process, which is an important process for securing a deep depth of focus (a focused area), exposing fine patterns, and improving the level difference that occurs in the film formation process. .
- the lithography process also includes photoresist application (2206), exposure (2207), development (2208), etching (2209), and resist removal (2210).
- Various other processes may be included in the lithography process.
- a photoresist which is a photosensitive resin
- a thin film such as a GaN crystal
- a mask on which a circuit pattern such as an IC is formed.
- an ultraviolet ray, excimer laser beam, electron beam, X The mask pattern is transferred onto the thin film by exposing it to light. Development is then performed to form a circuit on the thin film, and etching and resist removal are performed.
- the wiring process is repeated many times depending on the number of electronic device layers.
- the assembly process consists of dicing (1911), mounting (1 912) mounting the electronic device on the frame, and cutting the wafer on which a large number of electronic devices are formed into individual electronic devices.
- FIG. 24 shows the relationship of the output with respect to the forward voltage of the blue LED produced by the single crystal sapphire substrate of this embodiment.
- the forward voltage (Vf) is the voltage when a constant current flows through the P ⁇ N junction, and the output was measured with a photodetector using an integrating sphere.
- a blue LED was manufactured by epitaxially growing a gallium nitride thin film on the single crystal sapphire substrate of this embodiment.
- the blue LED fabricated with the single crystal sapphire substrate of the present embodiment clearly has a higher output than the blue LED manufactured by the conventional technology.
- FIG. 2 shows a surface of a single crystal sapphire substrate of Embodiment 1.
- FIG. 17 AFM measurement image of single crystal sapphire substrate of Embodiment 3.
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Abstract
Description
明 細 書 Specification
単結晶サファイア基板 Single crystal sapphire substrate
技術分野 Technical field
[0001] 本発明は LED (Light Emitting Diode)、 LD (Laser Diode)、 HEMT (High Electron M obility Transistor)、 FET (Field effect Transistor)、 SOS (Silicon- ON- Sapphire)等の 素子形成に適した結晶品質と表面状態をもつ単結晶サファイア基板の製造方法に 関する。 [0001] The present invention is suitable for forming elements such as LEDs (Light Emitting Diodes), LDs (Laser Diodes), HEMTs (High Electron Mobility Transistors), FETs (Field Effect Transistors), and SOS (Silicon-ON-Sapphire). The present invention relates to a method for manufacturing a single crystal sapphire substrate having crystal quality and surface condition.
背景技術 Background art
[0002] 現在、青色、白色発光ダイオード (LED)は交通信号機、自動車の計器パネル、携 帯電話の液晶パネル用バックライト等の光源などに使用されている。青色、白色 LE Dに用いられる窒化ガリウム (GaN)結晶は、サファイア (Al O )や炭化ケィ素(SiC) [0002] Currently, blue and white light-emitting diodes (LEDs) are used for light sources such as traffic signals, automobile instrument panels, and backlights for liquid crystal panels of mobile phones. Gallium nitride (GaN) crystals used for blue and white LEDs are sapphire (Al 2 O 3) and silicon carbide (SiC)
2 3 twenty three
などの基板上にバッファ層を介してェピタキシャル成長させることにより製造される。 特にサファイア基板は近年大量生産が可能になっており、かつ熱的およびィ匕学的に 安定なことから広く用いられるようになつている。単結晶サファイア基板は、また、 LE Dだけでなく、様々な電子デバイス製造の基板として利用されて!ヽる。 It is manufactured by epitaxial growth through a buffer layer on a substrate. In particular, sapphire substrates have recently become widely used because they have been mass-produced in recent years and are thermally and chemically stable. Single crystal sapphire substrates are also used as substrates for manufacturing various electronic devices, not just LEDs.
[0003] 単結晶サファイア基板上に GaN結晶などを成長させる場合、サファイア結晶の C面 に対して 0. 01度から 2. 0度程度傾斜させることが一般的に行われている。傾斜させ て ヽな 、サファイア単結晶表面の C面上に GaN結晶を成長させると、得られる GaN 結晶は結晶欠陥が多ぐ表面も凹凸が見られる結晶となってしまう。そこで、図 1のよ うに、サファイア単結晶の表面を C面に対して所定の角度に傾斜させた単結晶サファ ィァ基板を用いることにより、結晶欠陥が少なぐ表面も平坦な GaN結晶が得られる ことが知られている(特許文献 1)。このとき、サファイア基板表面は、図 1のようにミクロ 的なステップ状に形成される。そして、このステップ形状の規則性が高いほど、基板 上には良好な GaN結晶が成長することがわ力 ている。 [0003] When a GaN crystal or the like is grown on a single crystal sapphire substrate, it is generally performed at an angle of about 0.01 to 2.0 degrees with respect to the C plane of the sapphire crystal. When a GaN crystal is grown on the C-plane of the sapphire single crystal surface, the resulting GaN crystal becomes a crystal with many crystal defects and unevenness. Therefore, as shown in Fig. 1, by using a single crystal sapphire substrate in which the surface of the sapphire single crystal is inclined at a predetermined angle with respect to the C plane, a GaN crystal having a flat surface with few crystal defects can be obtained. (Patent Document 1). At this time, the surface of the sapphire substrate is formed in microscopic steps as shown in FIG. The higher the regularity of this step shape, the more powerful GaN crystals grow on the substrate.
特許文献 1:特開 2002— 293692号公報 Patent Document 1: JP 2002-293692 A
非特許文献 1: SASAKI Atsushi, HARA Wakana, MATSUDA Akilumi, AKIBA Shusak u, TATEDA Norihiro, YOSHIMOTO Mamoru, Nucl Instrum Methods Phys Res Sect B, VOL. 232 NO. 1—4; PAGE. 305—311; (2005/05).Non-Patent Document 1: SASAKI Atsushi, HARA Wakana, MATSUDA Akilumi, AKIBA Shusak u, TATEDA Norihiro, YOSHIMOTO Mamoru, Nucl Instrum Methods Phys Res Sect B, VOL. 232 NO. 1-4; PAGE. 305-311; (2005/05).
f^^ j¾2 : http://foundry.sanken.osaka-u.ac.jp/report/H15-010.pdf 発明の開示 f ^^ j¾2: http://foundry.sanken.osaka-u.ac.jp/report/H15-010.pdf Invention Disclosure
発明が解決しょうとする課題 Problems to be solved by the invention
[0004] しかし、特許文献 1の単結晶サファイア基板上に GaN結晶の薄膜を形成させるため に、ウェハーとして加工すると、ステップは原子レベルでみると、直線性が無ぐステツ プの高さも均一ではなく複数のステップも平行になっておらず、テラス表面には凹凸 が見られた。特に、表面の傾斜角度が大きくなると、ステップの不均一性が顕著に表 れ、テラス表面の凹凸も激しくなつた。つまり、特許文献 1に記載の単結晶サファイア 基板は、サファイア結晶を構成する酸素原子とアルミニウム原子が規則的に配列して おらず、良質の結晶が得られな 、と 、う問題があった。 [0004] However, when processing as a wafer to form a GaN crystal thin film on the single crystal sapphire substrate of Patent Document 1, the steps are not linear and the step height is not uniform at the atomic level. The steps were not parallel, and the terrace surface was uneven. In particular, when the inclination angle of the surface was increased, the unevenness of the steps became prominent and the unevenness of the terrace surface became severe. That is, the single crystal sapphire substrate described in Patent Document 1 has a problem in that oxygen atoms and aluminum atoms constituting the sapphire crystal are not regularly arranged, and a high-quality crystal cannot be obtained.
課題を解決するための手段 Means for solving the problem
[0005] 上記課題を解決するために、本件発明では、従来の単結晶サファイア基板よりもス テツプ形状が整いテラス面がより平坦な単結晶サファイア基板およびその製造方法 を提供する。 [0005] In order to solve the above problems, the present invention provides a single crystal sapphire substrate having a step shape and a flatter terrace surface than a conventional single crystal sapphire substrate, and a method for manufacturing the same.
[0006] すなわち第一の発明は、単結晶サファイア表面にテラス面を有する規則的なステツ プが形成された単結晶サファイア基板であって、基板のマクロ的表面粗さ (Ra)が 0. Inm以下であり、テラス面の表面粗さ(Ra)が 0. 03nm以下であり、ステップ高さが 0 . Inm以上 0. 3nm以下であり、テラス幅の最大値と最小値の差が 500nm以下であ る、単結晶サファイア基板を提供する。 [0006] That is, the first invention is a single crystal sapphire substrate in which a regular step having a terrace surface is formed on the single crystal sapphire surface, and the macro surface roughness (Ra) of the substrate is 0. Inm. The terrace surface roughness (Ra) is 0.03 nm or less, the step height is 0.3 Inm or more and 0.3 nm or less, and the difference between the maximum and minimum terrace width is 500 nm or less. A single crystal sapphire substrate is provided.
[0007] 第二の発明は、単結晶サファイア基板のマクロ的表面が、主面に対し 0. 1度から 0 . 6度の角度で傾斜している、単結晶サファイア基板を提供する。 [0007] The second invention provides a single crystal sapphire substrate in which the macroscopic surface of the single crystal sapphire substrate is inclined at an angle of 0.1 to 0.6 degrees with respect to the main surface.
[0008] 第三の発明は、テラス面において、酸素原子が終端をなし、酸素の単原子層を形 成するように構成されて 、る、単結晶サファイア基板を提供する。 [0008] A third invention provides a single-crystal sapphire substrate configured such that oxygen atoms terminate on a terrace surface to form a monoatomic layer of oxygen.
[0009] 第四の発明は、単結晶サファイア基板を真空雰囲気で加熱する真空加熱ステップ と、前記真空加熱ステップ後に取り出したサファイア基板を大気雰囲気で低温加熱 する第一大気加熱ステップと、第一大気加熱ステップ後に、炉温度を昇温してさらに 加熱する第二大気加熱ステップと、からなる単結晶サファイア基板の製造方法を提 供する。 [0009] A fourth invention includes a vacuum heating step of heating the single crystal sapphire substrate in a vacuum atmosphere, a first atmospheric heating step of heating the sapphire substrate taken out after the vacuum heating step in an atmospheric atmosphere, and a first atmosphere After the heating step, there is provided a method for manufacturing a single crystal sapphire substrate comprising a second atmospheric heating step in which the furnace temperature is raised and further heated. Provide.
[0010] 第五の発明は、単結晶サファイア基板を真空雰囲気で加熱する真空加熱ステップ と、前記真空加熱ステップ後に取り出したサファイア基板を大気に含まれる成分雰囲 気下で低温加熱する第一大気加熱ステップと、前記第一大気加熱ステップ後に、炉 温度を昇温して大気に含まれる成分雰囲気下でさらに加熱する第二大気加熱ステツ プと、からなる単結晶差サファイア基板の製造方法を提供する。 [0010] The fifth invention includes a vacuum heating step for heating the single crystal sapphire substrate in a vacuum atmosphere, and a first atmosphere for heating the sapphire substrate taken out after the vacuum heating step at a low temperature in a component atmosphere contained in the atmosphere. Provided is a method for producing a single crystal difference sapphire substrate comprising: a heating step; and a second atmospheric heating step in which, after the first atmospheric heating step, the furnace temperature is raised and further heated in a component atmosphere contained in the atmosphere. To do.
[0011] 第六の発明は、前記真空加熱ステップの加熱温度が 1000°C以上 1300°C以下、 保持時間が 2時間以上であり、前記第一大気加熱ステップの加熱温度が 800°C以上 1000°C以下、保持時間が 2時間以上 5時間以下であり、前記第二大気加熱ステップ の加熱温度が 1300°C以上 1600°C以下、保持時間が 1時間以上 5時間以下である 、単結晶サファイア基板の製造方法を提供する。 [0011] In a sixth invention, the heating temperature in the vacuum heating step is 1000 ° C or higher and 1300 ° C or lower, the holding time is 2 hours or longer, and the heating temperature in the first atmospheric heating step is 800 ° C or higher. Single crystal sapphire having a temperature of 1 ° C or less, a holding time of 2 hours or more and 5 hours or less, a heating temperature of the second atmospheric heating step of 1300 ° C or more and 1600 ° C or less, and a holding time of 1 hour or more and 5 hours or less A method for manufacturing a substrate is provided.
[0012] 第七の発明は、単結晶サファイア基板のテラス面を含む面側に電子デバイス素材 をェピタキシャル成長させることで電子デバイスを製造する電子デバイスの製造方法 を提供する。 [0012] A seventh invention provides an electronic device manufacturing method for manufacturing an electronic device by epitaxially growing an electronic device material on a surface side including a terrace surface of a single crystal sapphire substrate.
[0013] 第八の発明は、前記電子デバイス素材は、窒化ガリウムである電子デバイスの製造 方法を提供する。 [0013] An eighth invention provides a method of manufacturing an electronic device, wherein the electronic device material is gallium nitride.
[0014] 第九の発明は、単結晶サファイア基板を用いて、そのテラス面を含む面側に電子 デバイス素材をェピタキシャル成長させた電子デバイス中間構造体を提供する。 発明の効果 A ninth invention provides an electronic device intermediate structure in which an electronic device material is epitaxially grown on a surface side including a terrace surface using a single crystal sapphire substrate. The invention's effect
[0015] 本件発明の単結晶サファイア基板を用いることにより、テラス面がより平坦で、結晶 欠陥の少ない結晶膜を得ることができる。また、表面が平坦で結晶欠陥の少ない Ga N結晶膜を得ることが可能であり、この GaN結晶膜は、発光素子として用いた場合に は、より良好な発光特性を示す。また、本件発明の単結晶サファイア基板製造方法 によれば、サファイア単結晶表面の傾斜角度を精密に制御することができ、目的に応 じた単結晶サファイア基板を確実に得ることができる。 By using the single crystal sapphire substrate of the present invention, it is possible to obtain a crystal film having a flatter terrace surface and few crystal defects. Further, it is possible to obtain a GaN crystal film having a flat surface and few crystal defects, and this GaN crystal film exhibits better light emission characteristics when used as a light emitting device. Further, according to the method for producing a single crystal sapphire substrate of the present invention, the tilt angle of the sapphire single crystal surface can be precisely controlled, and a single crystal sapphire substrate suitable for the purpose can be obtained with certainty.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0016] 以下に、各発明を実施するための最良の形態を説明する。なお、本発明はこれら 実施の形態に何ら限定されるものではなぐその要旨を逸脱しない範囲において、種 々なる態様で実施しうる。 [0016] The best mode for carrying out each invention will be described below. It should be noted that the present invention is not limited to these embodiments, and is within the scope not departing from the gist thereof. It can be implemented in various ways.
[0017] 実施形態 1は主に請求項 1、 2及び 3について説明する。実施形態 2は主に請求項 4について説明する。実施形態 3は主に請求項 5、 6、 7、 8及び 9について説明する。 実施形態 4は主に請求項 10、 11及び 12につ 、て説明する。 [0017] The first embodiment will mainly describe claims 1, 2 and 3. The second embodiment will mainly describe claim 4. The third embodiment will mainly describe claims 5, 6, 7, 8, and 9. Embodiment 4 will mainly describe claims 10, 11 and 12.
く実施形態 1〉 Embodiment 1>
く実施形態 1 :概念〉 Embodiment 1: Concept>
[0018] 本実施形態の単結晶サファイア基板は、基板の表面粗さ、ステップの形状などを制 御し、基板上に成長する結晶の品質を向上させた。 [0018] The single crystal sapphire substrate of the present embodiment controls the surface roughness of the substrate, the shape of the steps, etc., and improves the quality of the crystal grown on the substrate.
く実施形態 1 :構成〉 <Embodiment 1: Configuration>
[0019] 図 2は単結晶サファイア基板のマクロ的表面を模式的に表した図である。単結晶サ ファイア基板は、単結晶サファイア表面に平坦なテラス面 (0201)を有する規則的な ステップが形成されている。テラス面 (0201)とは基板表面の平坦な部分のうち面積 の広い方、ステップ面 (0202)とは基板表面の平坦な部分のうち面積の狭い方、すな わち一のテラス面とそれに続くテラス面とを接続する面である。図 2に示すように、一 のテラス面とそれに続くテラス面の垂直方向の間隔をステップ高さ (h)、テラス面とそ れに続くテラス面の水平方向の間隔をテラス幅 (w)、テラス面と単結晶サファイア基 板のマクロ的表面の端線 (0203)とがなす角をオフセット角度( Θ )という。また、テラ ス面とステップ面が接する角をエッジ(0204) t 、う。 FIG. 2 is a diagram schematically showing a macroscopic surface of a single crystal sapphire substrate. In the single crystal sapphire substrate, regular steps having a flat terrace surface (0201) are formed on the single crystal sapphire surface. The terrace surface (0201) is the larger part of the flat part of the substrate surface, and the step surface (0202) is the smaller part of the flat part of the substrate surface, that is, one terrace surface and it. It is a surface that connects the following terrace surface. As shown in Fig. 2, the vertical distance between one terrace surface and the following terrace surface is the step height (h), and the horizontal distance between the terrace surface and the subsequent terrace surface is the terrace width (w), The angle between the terrace surface and the end line (0203) of the macroscopic surface of the single crystal sapphire substrate is called the offset angle (Θ). Also, the edge (0204) t is the angle at which the glass surface and the step surface meet.
[0020] 単結晶サファイアとは、サファイア( a Al O )を素材とし、理想的にはサファイアの [0020] Single crystal sapphire is made of sapphire (a Al O), ideally sapphire
2 3 twenty three
任意の結晶軸に注目したとき、試料のどの部分においてもその向きが同一であるよう な物質である。ただし通常は転位を含んでいるため、部分的に結晶軸の向きが変わ つても良い。 When focusing on an arbitrary crystal axis, it is a substance whose orientation is the same in any part of the sample. However, since it usually contains dislocations, the direction of the crystal axis may partially change.
[0021] 図 3はサファイア単結晶の単位格子を示したものである。サファイア単結晶は六方 晶構造を有する。六方晶の底面を C面 (ミラー指数表記:(0001) )、側面を Μ面 (ミラ 一指数表記: 10— 10) ) (ミラー指数のマイナス記号の表記方法は、数字の上に記載 するべきであるが、ここでは、簡略的に数字の前にマイナス記号を表記した)、斜線で 示した面を Α面 (ミラー指数表記: 11 20) )および R面 (ミラー指数表記: 10— 12) ) という。 [0022] 本実施形態の単結晶サファイア基板の特徴は以下の点である。 FIG. 3 shows a unit cell of a sapphire single crystal. A sapphire single crystal has a hexagonal crystal structure. Hexagonal crystal with C-plane (Miller index notation: (0001)) and side-faced (Mira one-index notation: 10-10)) (Miller index minus sign notation method should be written above the number However, here, the minus sign is written in front of the numbers for the sake of simplicity), and the hatched surface is the Α surface (Miller index notation: 11 20)) and R surface (Miller index notation: 10—12) ) [0022] The characteristics of the single crystal sapphire substrate of the present embodiment are as follows.
[0023] 第一に基板の表面粗さ (Ra)が 0. lnm以下である。表面粗さ (Ra)とは、基板表面 上の任意の線 (長さ L)の Xにおける平均線に対する高さを f (X)としたときに、数 1で表 される。 Raの値が小さいほど、ステップ面が平滑であることを示す。基板の表面粗さ は、基板表面全体の粗さであり、後述する特定のテラス面の表面粗さとは異なる。す なわち、基板の表面粗さを測定する際には、図 2の X方向に表面高さを測定すると良 い。 [0023] First, the surface roughness (Ra) of the substrate is 0.1 nm or less. The surface roughness (Ra) is expressed by Equation 1 where f (X) is the height of an arbitrary line (length L) on the substrate surface relative to the average line at X. The smaller the Ra value, the smoother the step surface. The surface roughness of the substrate is the roughness of the entire substrate surface and is different from the surface roughness of a specific terrace surface described later. In other words, when measuring the surface roughness of the substrate, it is better to measure the surface height in the X direction in Fig. 2.
[数 1] [Number 1]
[0024] 第二に、テラス面の表面粗さ(Ra)が 0. 03nm以下である。テラス面の表面粗さとは 、ある特定のテラス面の表面粗さである。したがって、テラス面の表面粗さを測定する 際には、図 2の y方向に表面高さを測定すると良い。 [0024] Second, the surface roughness (Ra) of the terrace surface is 0.03 nm or less. The surface roughness of the terrace surface is the surface roughness of a specific terrace surface. Therefore, when measuring the surface roughness of the terrace surface, the surface height should be measured in the y direction in Fig. 2.
[0025] 第三に、ステップ高さが 0. lnm以上 0. 3nm以下である。テラス面が C面であるとき は、ステップ高さは、酸素原子層と隣り合うアルミニウム原子層の間隔 (約 0. 22nm) であることが好ましい。この高さがステップ高さの最小単位となるものだ力もである。ス テツプ高さが酸素原子層と隣り合うアルミニウム原子層の間隔となっていることを単位 ステップという。 [0025] Third, the step height is 0.1 nm or more and 0.3 nm or less. When the terrace surface is the C surface, the step height is preferably the distance between the oxygen atomic layer and the adjacent aluminum atomic layer (about 0.22 nm). This height is also the force that becomes the minimum unit of the step height. The step height is the distance between the oxygen atomic layer and the adjacent aluminum atomic layer.
[0026] 第四に、 1つのテラス面において、テラス幅の最大値と最小値の差が 500nm以下 である。すなわち、テラス面のエッジが直線に近い形状になっていることが必要である [0026] Fourth, on one terrace surface, the difference between the maximum value and the minimum value of the terrace width is 500 nm or less. That is, it is necessary that the edge of the terrace surface has a shape close to a straight line.
[0027] 単結晶サファイア基板表面の特性を以上のように規定することで、基板表面上に成 長する GaNなどの結晶表面を平坦にし、かつ転位密度を減少させることができる。 By defining the characteristics of the single crystal sapphire substrate surface as described above, the crystal surface of GaN or the like grown on the substrate surface can be flattened and the dislocation density can be reduced.
[0028] また、テラス面が主面に対して平行であることが好ま 、。主面とは、サファイア単結 晶の C面、 A面、 M面、 R面のいずれかである。テラス面を主面と平行にするのがエネ ルギー的に最も安定であるからである。 [0029] また前記単結晶サファイア基板のマクロ的表面力 主面に対して 0. 1度力 0. 6度 の角度で傾斜して 、ることが好ま 、。また主面に対し任意の方向に対して傾斜して いるよりも、特定の方向に対して傾斜していることがより好ましい。例えば、主面が C面 である場合には、 C面から A面方向または M面方向に向力つて 0. 1度力も 0. 6度の 角度で傾斜して ヽるのが好ま 、。 [0028] In addition, it is preferable that the terrace surface is parallel to the main surface. The main surface is one of the C-plane, A-plane, M-plane, and R-plane of the sapphire single crystal. This is because the terrace surface is parallel to the main surface because it is the most stable in terms of energy. [0029] Further, the macroscopic surface force of the single crystal sapphire substrate is preferably inclined at an angle of 0.1 degree force 0.6 degree with respect to the main surface. Further, it is more preferable that the main surface is inclined with respect to a specific direction rather than with respect to an arbitrary direction. For example, when the main surface is the C surface, it is preferable that the 0.1 degree force is inclined at an angle of 0.6 degrees when directed from the C surface toward the A surface direction or the M surface direction.
[0030] 図 4は、マクロ的表面を説明した図である。マクロ的表面とは、図 4の点線に示すよう に、単結晶サファイア基板をマクロ的に見たときの平均的な面を表す。傾斜角度が 0 . 1度以下の場合は、ステップ面とテラス面が明確に形成できず、傾斜角度が 0. 6度 以上の場合は、ステップ高さが 0. 3nm以上必要となり、ステップがうまく形成されな い。 FIG. 4 is a diagram illustrating a macroscopic surface. As shown by the dotted line in Fig. 4, the macroscopic surface represents the average surface when the single crystal sapphire substrate is viewed macroscopically. If the tilt angle is 0.1 degrees or less, the step surface and the terrace surface cannot be clearly formed. If the tilt angle is 0.6 degrees or more, the step height is required to be 0.3 nm or more, and the step is good. Not formed.
く実施形態 1 :実施例〉 Embodiment 1: Example>
[0031] 図 5に本実施形態の C面を主面とした単結晶サファイア基板の AFM測定結果の一 例を示す。図 5に示したように、本実施形態の単結晶サファイア基板は、形状の整つ たステップが形成されていることがわかる。また、この単結晶サファイア基板の表面形 状を測定した結果、テラス面の表面粗さは 0. 013nm、テラス幅は 400〜600nm、ス テツプ高さは約 0. 2nmであることがわかった。 [0031] FIG. 5 shows an example of an AFM measurement result of a single crystal sapphire substrate with the C-plane as the main surface of the present embodiment. As shown in FIG. 5, it can be seen that the single crystal sapphire substrate of this embodiment has steps with a uniform shape. As a result of measuring the surface shape of this single crystal sapphire substrate, it was found that the surface roughness of the terrace surface was 0.013 nm, the terrace width was 400 to 600 nm, and the step height was about 0.2 nm.
く実施形態 1 :効果〉 <Embodiment 1: Effect>
[0032] 本実施形態のサファイア基板を用いることにより、表面が平坦でかつ転位密度が少 ないェピタキシャル膜を得ることができる。結晶性の良好なェピタキシャル膜は、発光 素子などとして用いたときも良好な発光特性を示す。 By using the sapphire substrate of this embodiment, an epitaxial film having a flat surface and a low dislocation density can be obtained. An epitaxial film with good crystallinity shows good light emission characteristics even when used as a light emitting element.
く実施形態 2〉 Embodiment 2>
く実施形態 2 :概要〉 Embodiment 2: Overview>
[0033] 本実施形態のサファイア単結晶は、基板表面が酸素原子で構成され、酸素原子が 規則正しく配列していることを特徴としている。これにより、サファイア基板上に結晶性 の良好なェピタキシャル膜を形成する事が可能となる。 [0033] The sapphire single crystal of this embodiment is characterized in that the substrate surface is composed of oxygen atoms, and the oxygen atoms are regularly arranged. As a result, it is possible to form an epitaxial film with good crystallinity on the sapphire substrate.
く実施形態 2 :構成〉 <Embodiment 2: Configuration>
[0034] 本実施形態の単結晶サファイア基板は、テラス面において、酸素原子が終端をなし 、酸素の単原子層を形成するように構成されている。なお、ここでの酸素原子が終端 をなし、酸素単原子層を形成するような構成は、結晶欠陥や製造プロセス上の製造 誤差により表面にアルミニウム原子が露出する程度のものは酸素単原子層を形成し て 、るとみなされる。なぜなら完全な結晶は理論上はとも力べ工業的には製造するこ とが困難だ力もである。また、これらの結晶欠陥や製造プロセス上の誤差の程度は製 品歩留まりを悪化させる原因になるが、不良品を廃棄するという考え方に立てば欠陥 や不良は商業的合理性の範囲内である程度は許容される。 [0034] The single crystal sapphire substrate of the present embodiment is configured such that oxygen atoms terminate on the terrace surface to form a monoatomic layer of oxygen. Here, the oxygen atom ends here The structure in which an oxygen monoatomic layer is formed is considered to form an oxygen monoatomic layer if aluminum atoms are exposed on the surface due to crystal defects or manufacturing errors in the manufacturing process. This is because perfect crystals are theoretically difficult to manufacture industrially. In addition, these crystal defects and the degree of error in the manufacturing process cause the product yield to deteriorate, but if the concept of discarding defective products is used, the defects and defects are within a certain extent within the range of commercial rationality. Permissible.
[0035] 本実施形態の単結晶サファイア基板は、テラス面がサファイア結晶の C面 (ミラー指 数表記:(0001) )から構成される。図 6にサファイア結晶の概念図を示した。尚、図 中では、アルミニウム原子は、黒い丸で示している力 酸素原子については、図が煩 雑になるため省略している。サファイアの結晶は図 6の(a)または(b)に示したような 酸素原子を頂点に有する正八面体構造が連なった形状となっている。(a)は、酸素 原子のみで構成された正八面体構造で、(b)はアルミニウム原子を正八面体構造中 に有する正八面体構造である。これらの正八面体構造力 (c)に示すように多数構成 されることでサファイア結晶を構成している。(c)の斜線で示した面は、サファイア結 晶の C面の一部を構成する面である。 [0035] The single crystal sapphire substrate of this embodiment is composed of a C-plane (mirror index notation: (0001)) whose terrace surface is a sapphire crystal. Figure 6 shows a conceptual diagram of the sapphire crystal. In the figure, aluminum atoms are omitted for the force oxygen atoms indicated by black circles because the figure becomes complicated. The sapphire crystal has a regular octahedral structure with oxygen atoms at the apexes as shown in Fig. 6 (a) or (b). (A) is a regular octahedral structure composed only of oxygen atoms, and (b) is a regular octahedral structure having aluminum atoms in the regular octahedral structure. As shown in these regular octahedron structural forces (c), a large number of sapphire crystals constitute a sapphire crystal. The surface indicated by the oblique lines in (c) is a surface constituting a part of the C surface of the sapphire crystal.
[0036] 本実施形態はこの C面によってテラス面が構成されている。サファイア基板上に成 長する結晶は、サファイア結晶の最表面に位置する原子によって大きく左右される。 よってまず、単結晶サファイア基板の最表面の検討を行った。単結晶サファイア基板 の最表面となる C面方向上部より、最表面のみの原子を表すと図 7のようになる。図 7 の斜線で示した三角形は、図 6に示したサファイア結晶の正八面体構造の斜線で示 した一面に該当する。図 7に示した六角形 (0701)は、図 3で示した六角柱の C面部 分に該当する。 In this embodiment, a terrace surface is constituted by the C surface. The crystal grown on the sapphire substrate is greatly influenced by the atoms located on the outermost surface of the sapphire crystal. Therefore, first, the outermost surface of the single crystal sapphire substrate was examined. Figure 7 shows the atoms on the outermost surface from the top in the C-plane direction, which is the outermost surface of the single crystal sapphire substrate. The triangle indicated by the diagonal line in Fig. 7 corresponds to the one side indicated by the diagonal line in the octahedral structure of the sapphire crystal shown in Fig. 6. The hexagon (0701) shown in Fig. 7 corresponds to the C-plane part of the hexagonal column shown in Fig. 3.
[0037] 図 7に示した直線 A— B (0702) (つまり A面 (ミラー指数表記:(11 20) ) )で切断 し、矢印の方向からみた断面図を図 8に示した。サファイア結晶の C面を主面として構 成することにより、図 7から最表面の原子層が酸素原子のみ力もなる単原子層力もな ることがゎカゝる。図 8と同じ方向カゝらテラス面およびステップを形成した場合の断面図 を図 9に示した。ステップのエッジは切断を行う角度や研磨、熱処理時の条件に応じ て、(a)、 (b) (c)のように鈍角や鋭角または直角の角を持つ。また (d)のように鋭角と 鈍角、直角のいずれの角を持つこともある。(a)から (d)のように、酸素原子のみを結 ぶ直線で構成された面は、何れの場合も酸素原子が終端、または最表面として構成 されているとした。よって本実施形態の単結晶サファイア基板は、テラス面は C面によ つて形成されており、表面は酸素原子のみで構成されている。またステップ面も酸素 原子で構成されており、原則的には、アルミニウム原子が表面に配列されることは無 い。 [0037] FIG. 8 shows a cross-sectional view taken along the line A—B (0702) shown in FIG. 7 (that is, the A plane (Miller index notation: (11 20))) and viewed from the direction of the arrow. By constructing the sapphire crystal with the C-plane as the main surface, it is clear from Fig. 7 that the atomic layer on the outermost surface also has a monoatomic layer force consisting of only oxygen atoms. Figure 9 shows a cross-sectional view of the terrace surface and steps formed in the same direction as in Fig. 8. The edge of the step has an obtuse angle, an acute angle, or a right angle, as shown in (a), (b), or (c), depending on the cutting angle and the conditions during polishing and heat treatment. Also, as shown in (d) May have either an obtuse angle or a right angle. As shown in (a) to (d), the surface composed of straight lines connecting only oxygen atoms is assumed to have oxygen atoms terminated or outermost in any case. Therefore, in the single crystal sapphire substrate of the present embodiment, the terrace surface is formed by the C surface, and the surface is composed only of oxygen atoms. The step surface is also composed of oxygen atoms, and in principle, aluminum atoms are not arranged on the surface.
く実施形態 2 :実施例〉 Embodiment 2: Example>
[0038] 本実施形態で示した単結晶サファイア基板の表面の原子配列を測定するために、 低速イオン散舌 L分光法 (low— energy ion scattering spectroscopy: LEISb)による測定 を行った。 LEISSは、非特許文献 1に記載されているように、結晶の表面原子の組成 および配列状態を測定することが可能であり、結晶の評価に用いられる分析手法で ある。 LEISSは、低エネルギーのイオンビームを試料表面に照射し、散乱イオンを検 出しエネルギースペクトルの変化を測定する。イオンビームの入射角度や入射方向 を変化させることにより、イオンビームの照射方向から見た原子配列が異なることによ り、検出される散乱イオンのエネルギースペクトルが変化することを利用して、対象試 料の原子配列を測定する。散乱イオンの検出は、イオン源と同軸上に設置された飛 行時間型測定装置によって行われる。また飛行時間型測定装置では、照射対象とな る原子の定性が行われる。本実施形態の単結晶サファイア基板では、入射するィォ ンビームとしてヘリウムイオンをパルス照射して測定を行った。 LEISSによって測定さ れたスペクトルは、結晶の理想形での原子配列を元に計算により得られたシミュレ一 シヨン結果との比較や、ピークが出現する位置および強度により原子の配置位置を 推定し評価される。 [0038] In order to measure the atomic arrangement on the surface of the single crystal sapphire substrate shown in the present embodiment, the measurement was performed by low-energy ion scattering spectroscopy (LEISb). As described in Non-Patent Document 1, LEISS can measure the composition and arrangement of surface atoms of a crystal and is an analytical technique used for crystal evaluation. LEISS irradiates the sample surface with a low-energy ion beam, detects scattered ions, and measures changes in the energy spectrum. By changing the energy spectrum of the scattered ions detected by changing the incident angle and the incident direction of the ion beam and changing the atomic arrangement as seen from the irradiation direction of the ion beam, Measure the atomic arrangement of the material. Scattered ions are detected by a time-of-flight measuring device installed coaxially with the ion source. In addition, the time-of-flight measurement device qualifies atoms to be irradiated. In the single crystal sapphire substrate of this embodiment, measurement was performed by irradiating a helium ion pulse as an incident ion beam. The spectrum measured by LEISS is compared with the simulation result obtained by calculation based on the atomic arrangement in the ideal form of the crystal, and the arrangement position of the atom is estimated and evaluated by the position and intensity where the peak appears. Is done.
[0039] 図 10に本実施形態の主面を C面とした単結晶サファイア基板を LEISSによって測定 を行ったスペクトル結果を示した。下段に示したスペクトルは、サファイア結晶の C面 の理想形での原子配列を元に得られたシミュレーション結果である。本実施形態の 単結晶サファイア基板力も得られたスペクトルとシミュレーションにより得られたスぺク トルを比較すると、入射方位角度が 30度から 360度まで、スペクトルとピーク検出位 置力 本実施形態の単結晶サファイア基板とシミュレーションにより得られたスぺタト ルでほぼ同角度で検出されている。また、図 10中の(a)から (f)のピークでは、シミュ レーシヨンの結果で見られるピークの「肩」が、本実施形態の単結晶サファイア基板で は、小さなピークもしくは「肩」として検出されており、極めて理想形に近い原子配列を 持つ単結晶サファイア基板が得られていることが分かる。 [0039] Fig. 10 shows the spectrum results of measuring the single crystal sapphire substrate with the main surface of the present embodiment as the C-plane by LEISS. The spectrum shown at the bottom is the simulation result obtained based on the ideal atomic arrangement of the C-plane of the sapphire crystal. Comparing the spectrum obtained from the single crystal sapphire substrate force of this embodiment with the spectrum obtained by simulation, the spectrum and peak detection position force of the incident azimuth angle ranged from 30 degrees to 360 degrees. Crystal sapphire substrate and spatter obtained by simulation Are detected at almost the same angle. In addition, in the peaks (a) to (f) in FIG. 10, the “shoulder” of the peak seen in the simulation results is detected as a small peak or “shoulder” in the single crystal sapphire substrate of this embodiment. It can be seen that a single crystal sapphire substrate having an atomic arrangement very close to the ideal shape is obtained.
[0040] また、図 25には、主面を A面としたときの単結晶サファイア基板を LEISSによって測 定を行ったスペクトル結果を示した。 LEISS測定は、基板に対して角度 15度で Heィォ ンを照射し、測定対象となるサファイア基板を 360度回転させ測定を行う。この場合、 理想的な A面である場合には、測定結果が 180度ごとに周期的なピークとなる。図 2 5では、ピーク(a)および (b)に対して、 180度移動した角度で (c)および (d)のピーク が出現しており、 180度ごとの周期的なピークとなっている。さらに、これらの結果は、 基板のオリエンテーションフラットに対して LEISS測定を行った場合と、同様のスぺタト ルを表しており、図 25に示したサファイア基板力 A面を主面とした基板であることを 示している。 [0040] Fig. 25 shows the spectrum results of the single crystal sapphire substrate measured by LEISS when the principal surface is the A-plane. In the LEISS measurement, Heon is irradiated at an angle of 15 degrees to the substrate, and the sapphire substrate to be measured is rotated 360 degrees. In this case, if it is an ideal A-plane, the measurement results have a periodic peak every 180 degrees. In Figure 25, peaks (c) and (d) appear at an angle shifted by 180 degrees with respect to peaks (a) and (b), which are periodic peaks every 180 degrees. . Furthermore, these results show the same spectrum as when the LEISS measurement was performed on the orientation flat of the substrate, and the results for the substrate with the sapphire substrate force A surface shown in Fig. 25 as the main surface. It shows that there is.
く実施形態 2 :効果〉 <Embodiment 2: Effect>
[0041] 本実施形態のサファイア基板を用いることにより、表面が平坦でかつ転位密度が少 ないェピタキシャル膜を得ることができる。結晶性の良好なェピタキシャル膜は、発光 素子などとして用いたときも良好な発光特性を示す。 By using the sapphire substrate of this embodiment, an epitaxial film having a flat surface and a low dislocation density can be obtained. An epitaxial film with good crystallinity shows good light emission characteristics even when used as a light emitting element.
く実施形態 3〉 Embodiment 3>
く実施形態 3 :概念〉 <Embodiment 3: Concept>
[0042] 本実施形態は、実施形態 1又は 2の単結晶サファイア基板の熱処理方法に関する 。熱処理方法は、真空加熱ステップと第一大気加熱ステップと第二大気加熱ステップ の 3段階力もなる熱処理方法と、真空加熱ステップと大気加熱ステップの 2段階力 な る熱処理方法の 2種類の熱処理方法がある。 The present embodiment relates to a heat treatment method for a single crystal sapphire substrate of Embodiment 1 or 2. There are two types of heat treatment methods: a heat treatment method that has a three-step force of a vacuum heating step, a first atmospheric heating step, and a second air heating step, and a heat treatment method that has a two-step force of a vacuum heating step and an atmospheric heating step. is there.
く実施形態 3 :構成〉 <Embodiment 3: Configuration>
[0043] 本実施形態の単結晶サファイア基板の製造方法は、熱処理方法は、真空加熱ステ ップと第一大気加熱ステップと第二大気加熱ステップの 3段階力 なる熱処理方法と 、真空加熱ステップと大気加熱ステップの 2段階からなる熱処理方法の 2種類の熱処 理方法がある。 [0044] 図 11および図 12に本実施形態の熱処理を行う加熱炉の一例を示した。図 11は、 3 段階と 2段階力もなる熱処理方法の真空加熱ステップを行う真空加熱炉である。加熱 炉(1101)は、発熱体(1102)によって加熱される。試料は試料搬入搬出口(1104) の下方より試料台(1103)が上下することによって、加熱炉内に搬入、搬出される。 加熱試料は、試料台が下がった状態で、試料台にセットし、試料台を矢印の方向へ 移動させ加熱炉内に搬入される。搬出時はこれとは逆に、試料台を矢印と逆へ移動 し搬出を行う。加熱炉には、クライオポンプ(1105)と真空ポンプ(1106)が取り付け られており、真空ポンプにて加熱炉内を減圧する。また真空度を上げるために、冷却 を行うクライオポンプが備え付けられている。また、これらの制御は制御装置(1107) にて行われる。 [0043] In the method for manufacturing a single crystal sapphire substrate of the present embodiment, the heat treatment method includes a heat treatment method having three steps of a vacuum heating step, a first atmospheric heating step, and a second atmospheric heating step, and a vacuum heating step. There are two types of heat treatment methods, a heat treatment method consisting of two steps, an atmospheric heating step. FIG. 11 and FIG. 12 show an example of a heating furnace that performs the heat treatment of the present embodiment. Fig. 11 shows a vacuum heating furnace that performs the vacuum heating step of the heat treatment method with three-stage and two-stage power. The heating furnace (1101) is heated by the heating element (1102). The sample is carried into and out of the heating furnace as the sample stage (1103) moves up and down from below the sample carry-in / out port (1104). The heated sample is set on the sample table while the sample table is lowered, and the sample table is moved in the direction of the arrow and is carried into the heating furnace. Conversely, when unloading, move the sample table in the direction opposite to the arrow and unload it. A cryopump (1105) and a vacuum pump (1106) are attached to the heating furnace, and the inside of the heating furnace is depressurized by the vacuum pump. In order to raise the degree of vacuum, a cryopump for cooling is provided. These controls are performed by the control device (1107).
[0045] 図 12には、 3段階力 なる熱処理方法の第一大気加熱ステップと第二大気加熱ス テツプ、 2段階力もなる熱処理方法の大気加熱ステップを行う大気加熱炉である。カロ 熱炉(1201)は、発熱体(1202)によって加熱される。試料は試料搬入搬出口(120 3)より搬入および搬出が行われる。試料搬入搬出口の右には、温度コントロールなど を行うための制御装置(1204)が備え付けられている。また、 3段階力もなる熱処理方 法の第一大気加熱ステップと第二大気加熱ステップ、 2段階力もなる熱処理方法の 大気加熱ステップは大気雰囲気下または大気に含まれる成分雰囲気下で行われる ため、内部流入させる大気の流量を確認する流量計(1205)が備え付けられている FIG. 12 shows an atmospheric heating furnace that performs a first atmospheric heating step and a second atmospheric heating step of a heat treatment method having a three-stage force, and an atmospheric heating step of a heat treatment method having a two-stage force. The Karo heating furnace (1201) is heated by the heating element (1202). The sample is loaded and unloaded from the sample loading / unloading port (1203). A control device (1204) for temperature control and the like is provided to the right of the sample loading / unloading port. In addition, the first and second air heating steps of the heat treatment method with a three-stage force, and the air heat step of the heat treatment method with a two-step force are performed in an air atmosphere or a component atmosphere contained in the air. A flow meter (1205) is provided to check the flow rate of the incoming air.
[0046] 3段階からなる熱処理方法、 2段階力 なる熱処理方法共に、まず図 11の真空加熱 炉にて熱処理を行い、熱処理終了後、図 12の大気加熱炉にて大気雰囲気中にて熱 処理を行う。 [0046] In both the three-step heat treatment method and the two-step heat treatment method, heat treatment is first performed in the vacuum heating furnace of FIG. 11, and after the heat treatment is completed, heat treatment is performed in the air atmosphere of the air heating furnace of FIG. I do.
[0047] 図 13は本実施形態の 3段階力もなる熱処理の流れを説明した図である。本実施形 態の単結晶サファイア基板の熱処理方法は、真空加熱ステップ (S1301)と、第一大 気加熱ステップ(S 1302)と、第二大気加熱ステップ(S 1303)と、力もなる。これらの 熱処理は、単結晶サファイアのインゴットを製造後、スライシングおよび研磨が行われ た後に行われる工程で、単結晶サファイア基板表面の完全結晶層を確保するために 行われる。 [0048] 真空加熱ステップ(S1301)は、単結晶サファイア基板を真空雰囲気で加熱する。 真空加熱ステップの目的は、アルミナ昇華温度の手前で過剰酸素除去を行うとともに 、研磨作業中に混入した硫化物、塩化物、水酸化物などの不純物を融点以上で蒸 発させる目的である。真空加熱ステップの加熱温度は 1600°C以上 2000°C以下、保 持時間は 2時間以上とするのが好ましい。加熱温度が 1600°C以下または保持時間 力 時間以下では、不純物の除去が十分でなぐ加熱温度が 2000°C以上では、単 結晶サファイア基板の変形が大きくなるためである。真空雰囲気の気圧は、 10"5Tor r以下であることが好ま U、。これ以上の気圧となると不純物の除去効果が低くなるた めである。 FIG. 13 is a diagram illustrating the flow of heat treatment that also has a three-stage force according to this embodiment. The heat treatment method for the single crystal sapphire substrate according to the present embodiment also includes a vacuum heating step (S1301), a first atmospheric heating step (S1302), and a second atmospheric heating step (S1303). These heat treatments are performed after manufacturing the single crystal sapphire ingot, followed by slicing and polishing, in order to secure a complete crystal layer on the surface of the single crystal sapphire substrate. [0048] In the vacuum heating step (S1301), the single crystal sapphire substrate is heated in a vacuum atmosphere. The purpose of the vacuum heating step is to remove excess oxygen before the alumina sublimation temperature and to vaporize impurities such as sulfides, chlorides and hydroxides mixed during the polishing operation above the melting point. The heating temperature in the vacuum heating step is preferably 1600 ° C or more and 2000 ° C or less, and the holding time is preferably 2 hours or more. This is because when the heating temperature is 1600 ° C or lower or the holding time is less than force time, the single crystal sapphire substrate is greatly deformed when the heating temperature is 2000 ° C or higher, at which impurities are not sufficiently removed. The atmospheric pressure in the vacuum atmosphere is preferably 10 " 5 Torr or less U. If the atmospheric pressure is higher than this, the effect of removing impurities is reduced.
[0049] 第一大気加熱ステップ(S 1302)は、真空加熱ステップ (S1301)後に取り出したサ ファイア基板を大気雰囲気または大気に含まれる成分中で低温加熱する。第一大気 加熱ステップの目的は、炭素を酸ィ匕し二酸ィ匕炭素として取り除くためである。大気雰 囲気および大気に含まれる成分中での低温加熱は、炭素を酸化し二酸化炭素にさ せるために十分な酸素を含んだ雰囲気であれば良 、。第一大気加熱ステップの加 熱温度は 800°C以上 1000°C以下、保持時間が 2時間以上 5時間以下であることが 好ましい。加熱温度が 800°C以下または保持時間が 2時間以下では、炭素を十分に 二酸ィ匕炭素に酸ィ匕させることができず、加熱温度が 1000°C以上または保持時間が 5時間以上では単結晶サファイア基板が変形するためである。真空加熱ステップ (S1 301)と第一大気加熱ステップ (S 1302)に用いる炉は、別の炉であることが好ましい 力 同一の炉であっても構わない。 In the first atmospheric heating step (S 1302), the sapphire substrate taken out after the vacuum heating step (S 1301) is heated at a low temperature in an atmospheric atmosphere or a component contained in the atmospheric air. The purpose of the first atmospheric heating step is to acidify and remove carbon as diacid carbon. Low-temperature heating in the atmosphere and components contained in the atmosphere is sufficient if the atmosphere contains sufficient oxygen to oxidize carbon to carbon dioxide. The heating temperature of the first atmospheric heating step is preferably 800 ° C. or higher and 1000 ° C. or lower, and the holding time is 2 hours or longer and 5 hours or shorter. If the heating temperature is 800 ° C or less or the holding time is 2 hours or less, the carbon cannot be sufficiently oxidized to carbon dioxide, and if the heating temperature is 1000 ° C or more or the holding time is 5 hours or more. This is because the single crystal sapphire substrate is deformed. The furnaces used for the vacuum heating step (S1 301) and the first atmospheric heating step (S1302) are preferably different furnaces.
[0050] 第二大気加熱ステップ(S 1303)は、第一大気加熱ステップ (S 1302)後に、炉温 度を昇温してさらに加熱する。第二大気加熱ステップは、大気雰囲気下または大気 に含まれる成分中で行われる。このステップにおいて、単結晶サファイア基板表面の ステップを規則的に整えることができる。第二大気加熱ステップの加熱温度は、 1000 °C以上 1300°C以下とし、保持時間は 1時間以上 5時間以下とするのが好ましい。カロ 熱温度が 1000°C以下または保持時間が 1時間以下では、ステップが整列せず、カロ 熱温度が 1300°C以上または保持時間が 5時間以上では単結晶サファイア基板が変 形するためである。 [0051] 第一大気加熱ステップ(SI 302)及び第二大気加熱ステップ (SI 303)においては 、基板が気流の影響を受けると装填位置による温度分布が生ずるため、基板はホル ダー内に固定した上、サファイアのブロックで密閉すると良い。温度と保持時間は上 記範囲内で、基板の傾斜角度に応じて変化させる。温度と保持時間が上記範囲外 だと、ステップ高さの均一性や真直性、テラス面の平坦性が損なわれたり、アルミ-ゥ ム原子の会合が生じて、アルミニウム原子と酸素原子の規則的な配列が損なわれる ことがある。 [0050] In the second atmospheric heating step (S1303), after the first atmospheric heating step (S1302), the furnace temperature is raised and further heated. The second air heating step is performed in an air atmosphere or in a component contained in the air. In this step, the steps on the surface of the single crystal sapphire substrate can be regularly arranged. The heating temperature in the second atmospheric heating step is preferably 1000 ° C. or higher and 1300 ° C. or lower, and the holding time is preferably 1 hour or longer and 5 hours or shorter. This is because the steps do not align when the calo heat temperature is 1000 ° C or less or the holding time is 1 hour or less, and the single crystal sapphire substrate is deformed when the calo heat temperature is 1300 ° C or more or the holding time is 5 hours or more. . [0051] In the first atmospheric heating step (SI 302) and the second atmospheric heating step (SI 303), since the temperature distribution depending on the loading position occurs when the substrate is affected by the air flow, the substrate is fixed in the holder. Above, it is better to seal with a sapphire block. The temperature and holding time are varied within the above range according to the tilt angle of the substrate. If the temperature and holding time are out of the above ranges, the step height uniformity and straightness, the flatness of the terrace surface will be impaired, and aluminum atoms will be associated with each other. The correct arrangement may be lost.
[0052] 図 14は本実施形態の 2段階力もなる熱処理の流れを説明した図である。本実施形 態の単結晶サファイア基板の熱処理方法は、真空加熱ステップ (S1401)と、大気カロ 熱ステップ(S1402)と力らなる。これらの熱処理は、単結晶サファイアのインゴットを 製造後、スライシングおよび研磨が行われた後に行われる。 FIG. 14 is a diagram illustrating the flow of heat treatment that also has a two-stage force in the present embodiment. The heat treatment method for the single crystal sapphire substrate of the present embodiment consists of a vacuum heating step (S1401) and an atmospheric calorie heating step (S1402). These heat treatments are performed after slicing and polishing after the production of the single crystal sapphire ingot.
[0053] 真空加熱ステップ(S1401)は、単結晶サファイア基板を真空雰囲気で加熱する。 In the vacuum heating step (S1401), the single crystal sapphire substrate is heated in a vacuum atmosphere.
真空加熱ステップの加熱温度は 1600°C以上 2000°C以下、保持時間は 2時間以上 とするのが好ましい。真空雰囲気の気圧は、 3段階力もなる熱処理方法と同様に、 10 _5Torr以下であることが好まし 、。 The heating temperature in the vacuum heating step is preferably 1600 ° C or more and 2000 ° C or less, and the holding time is preferably 2 hours or more. The pressure of the vacuum atmosphere is preferably 10 _ 5 Torr or less, as in the heat treatment method with three-stage force.
[0054] 大気加熱ステップ(S 1402)は、真空加熱ステップ (S1401)後に取り出したサファ ィァ基板を大気雰囲気または大気に含まれる成分中で加熱する。大気加熱ステップ の加熱温度は 1200°C以上 1400°C以下、保持時間が 1時間以上 5時間以下である ことが好ましい。大気雰囲気および大気に含まれる成分中での熱処理は、炭素を酸 化し二酸ィ匕炭素にさせるために十分な酸素を含んだ雰囲気であれば良い。また、大 気加熱ステップは、大気雰囲気下または大気に含まれる成分中で行われ、単結晶サ ファイア基板表面のステップを規則的に整える。 In the air heating step (S 1402), the sapphire substrate taken out after the vacuum heating step (S 1401) is heated in an air atmosphere or a component contained in the air. The heating temperature in the atmospheric heating step is preferably 1200 ° C to 1400 ° C, and the holding time is 1 hour to 5 hours. The heat treatment in the air atmosphere and the components contained in the air may be performed in an atmosphere containing sufficient oxygen to oxidize carbon to diacid-carbon. In addition, the atmospheric heating step is performed in an air atmosphere or in a component contained in the air, and regularly arranges steps on the surface of the single crystal sapphire substrate.
[0055] 尚、 2段階からなる熱処理方法の目的や、熱処理による単結晶サファイア基板への 影響などについては、 3段階力 なる熱処理方法とほぼ同様であるため詳細な説明 は省略する。 [0055] The purpose of the two-stage heat treatment method and the effect of the heat treatment on the single crystal sapphire substrate are substantially the same as those of the three-stage heat treatment method, and a detailed description thereof will be omitted.
く実施形態 3 :具体例〉 <Embodiment 3: Specific example>
[0056] 図 15に本実施形態の 3段階力もなる熱処理方法の具体例の一例を示した。(a)を 用いて、 3段階からなる熱処理方法を説明する。まず、真空加熱ステップにおいて、 室温 (RT)から、 1700°Cまで 7時間かけて昇温する。昇温後 1700°Cにて 2時間保持 し、保持後 12時間かけて室温まで降温させる。真空加熱ステップ終了後、過熱炉を 真空加熱炉から大気加熱炉へ変える。第一大気加熱ステップは、室温から 900°Cま で 4時間かけて昇温し、 900°Cにて 3時間保持する。保持後 6時間かけて室温まで降 温させる。第一大気加熱ステップ終了後、加熱炉は別の大気加熱炉に変えてもよい し、そのまま同じ加熱炉を使用してもよい。第二加熱ステップは、まず、室温から 120 0°Cまで 5時間かけて昇温し、 2時間 1200°Cにて保持する。保持後、 10時間かけて室 温まで降温し、熱処理が完了する。尚、 3段階力もなる熱処理方法は、第一大気加熱 ステップ終了後(a)のように一度常温 (RT)まで温度を下げた後に、第二大気加熱ス テツプの昇温を開始してもよいし、(b)のように、第一大気加熱ステップ終了後、温度 を下げずに、第二大気加熱ステップの昇温を開始してもよ 、。 FIG. 15 shows an example of a specific example of the heat treatment method having a three-stage force according to this embodiment. Using (a), a three-stage heat treatment method will be described. First, in the vacuum heating step, Raise the temperature from room temperature (RT) to 1700 ° C over 7 hours. Hold the temperature at 1700 ° C for 2 hours after raising the temperature, and then lower the temperature to room temperature over 12 hours after holding. After the vacuum heating step is completed, the superheating furnace is changed from the vacuum heating furnace to the atmospheric heating furnace. In the first atmospheric heating step, the temperature is raised from room temperature to 900 ° C over 4 hours and held at 900 ° C for 3 hours. Allow to cool to room temperature over 6 hours after holding. After the first atmospheric heating step, the heating furnace may be changed to another atmospheric heating furnace, or the same heating furnace may be used as it is. In the second heating step, first, the temperature is raised from room temperature to 1200 ° C over 5 hours and held at 1200 ° C for 2 hours. After holding, the temperature is lowered to room temperature over 10 hours to complete the heat treatment. In the heat treatment method with three-stage power, after the first atmospheric heating step is completed, the temperature of the second atmospheric heating step may be started after the temperature is once lowered to room temperature (RT) as shown in (a). Then, as shown in (b), after the first atmospheric heating step, the temperature increase in the second atmospheric heating step may be started without lowering the temperature.
[0057] 図 16に本実施形態の 2段階力もなる熱処理方法の具体例の一例を示した。まず、 真空加熱ステップにおいて、室温 (RT)から、 1700°Cまで 7時間かけて昇温する。昇 温後 1700°Cにて 2時間保持し、保持後 12時間かけて室温まで降温させる。真空カロ 熱ステップ終了後、過熱炉を真空加熱炉から大気加熱炉へ変える。大気加熱ステツ プは、室温から 1300°Cまで 5時間かけて昇温し、 1300°Cにて 4時間保持する。保持 後、 10時間かけて室温まで降温し、熱処理が完了する。 FIG. 16 shows an example of a specific example of the heat treatment method having a two-step force according to this embodiment. First, in the vacuum heating step, the temperature is raised from room temperature (RT) to 1700 ° C over 7 hours. After raising the temperature, hold it at 1700 ° C for 2 hours and let it cool down to room temperature over 12 hours. After the vacuum calorie heat step, the superheater is changed from a vacuum furnace to an atmospheric furnace. In the atmospheric heating step, the temperature is raised from room temperature to 1300 ° C over 5 hours and held at 1300 ° C for 4 hours. After holding, the temperature is lowered to room temperature over 10 hours to complete the heat treatment.
[0058] 尚、 3段階からなる熱処理方法、 2段階からなる熱処理方法共に、昇温速度並びに 降温速度は、使用する加熱炉の性能に応じて変化されるものである。 [0058] In both the three-stage heat treatment method and the two-stage heat treatment method, the temperature increase rate and the temperature decrease rate are changed according to the performance of the heating furnace to be used.
く実施形態 3 :効果〉 <Embodiment 3: Effect>
[0059] 図 17に本実施形態の 3段階からなる熱処理方法によって得られた単結晶サフアイ ァ基板表面の AFM測定画像を示した。 a)は熱処理前の単結晶サファイア基板であ る。 a)の画像では、テラス面の間隔が一定ではなぐテラス面のエッジが曲線となって いることが分かる。これを実施形態 3に示した 3段階からなる熱処理方法により熱処理 を行うと、 b)となる。 b)では、テラス面がほぼ一定の間隔からなり、テラス面のエッジも 直線力 構成されていることがわかる。また、参考に c)には、非特許文献 2に記載さ れた従来技術によって得られた単結晶サファイア基板表面の画像を示した。 c)の表 面は、テラス面のエッジが曲線であり、テラス面の間隔も一定となっておらず、本件発 明の熱処理方法前の単結晶サファイア基板と同様な表面となっている。よって、本実 施形態の熱処理方法を行うことにより、ステップが直線でステップ面が一定の間隔か らなる単結晶サファイア基板を量産に適する方法で得ることができた。 FIG. 17 shows an AFM measurement image of the surface of the single crystal sapphire substrate obtained by the three-stage heat treatment method of the present embodiment. a) is a single crystal sapphire substrate before heat treatment. In the image of a), it can be seen that the edge of the terrace surface is a curve where the interval between the terrace surfaces is not constant. When this is heat-treated by the three-stage heat treatment method shown in Embodiment 3, b) is obtained. In (b), it can be seen that the terrace surface has almost constant intervals, and the edge of the terrace surface is also composed of a linear force. For reference, c) shows an image of the surface of the single-crystal sapphire substrate obtained by the conventional technique described in Non-Patent Document 2. In the surface of c), the edge of the terrace surface is curved and the interval between the terrace surfaces is not constant. The surface is the same as that of the single crystal sapphire substrate before the bright heat treatment method. Therefore, by carrying out the heat treatment method of the present embodiment, a single crystal sapphire substrate having a straight line and step surfaces with a constant interval could be obtained by a method suitable for mass production.
く実施形態 4〉 Embodiment 4>
く実施形態 4 :概要〉 Embodiment 4: Overview>
[0060] 本実施形態は、前記単結晶サファイア基板に電子デバイス素材をェピタキシャル 成長させることで、電子デバイス又は電子デバイスの中間構造体を製造する。 In this embodiment, an electronic device or an intermediate structure of an electronic device is manufactured by epitaxially growing an electronic device material on the single crystal sapphire substrate.
く実施形態 4 :構成〉 <Embodiment 4: Configuration>
[0061] 本実施形態の電子デバイスの製造方法は、単結晶サファイア基板のテラス面を含 む面側に電子デバイス素材をェピタキシャル成長させることで電子デバイスを製造す る。 The electronic device manufacturing method of this embodiment manufactures an electronic device by epitaxially growing an electronic device material on the surface side including the terrace surface of the single crystal sapphire substrate.
[0062] ェピタキシャル成長は、薄膜の成長技術の中で、あら力じめ作られて 、る単結晶 基板の表面に、その結晶と結晶方向をそろえて新たな結晶層を形成する方法である 。エピタキシーによる結晶成長は、結晶の融点よりも低い温度で行うことができるため 、不純物の混入も少なく純度の高い結晶を作製する手段として利用されている。本実 施形態では、元となる基板の結晶を単結晶サファイア基板として、目的の結晶膜をェ ピタキシャル成長させる。ェピタキシャル成長方法には、気相エピタキシー(VPE:Vap or Phase Epitaxy)、分子線エピタキシー(MBE: Molecular Beam Epitaxy)、液相ェピ タキシー(LPE: Liquid Phase Epitaxy)、固相エピタキシー(SPE: Solid Phase Epitaxy) などの方法がある。 [0062] Epitaxial growth is a method of forming a new crystal layer by aligning the crystal direction with the crystal on the surface of a single crystal substrate, which has been intensively produced in the thin film growth technology. . Since crystal growth by epitaxy can be performed at a temperature lower than the melting point of the crystal, it is used as a means for producing a high-purity crystal with few impurities. In this embodiment, a target crystal film is epitaxially grown using a crystal of a base substrate as a single crystal sapphire substrate. Epitaxial growth methods include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and solid phase epitaxy (SPE). There are methods such as Phase Epitaxy).
[0063] 単結晶サファイア基板にェピタキシャル成長させる電子デバイス素材としては、図 1 8に示したような材料がある。単位元素としては、シリコン(Si)やゲルマニウム(Ge)、 セレン(Se)などの材料や、化合物としては、亜鉛化合物(ZnO、 ZnS、 ZnSb)、酸ィ匕 バリウム(BaO)、カドミウム化合物(CdS、 CdSe)、ガリウム化合物(GaNゝ GaAs)、ィ ンジゥム化合物(InP、 InAs、 InSb)、ゲルマニウム化合物(GeTe)、鉛化合物(PbS 、 PbSe、 PbTe)、バナジウム化合物(VO )、アンチモン化合物(Sb Te )、ビスマス As an electronic device material to be epitaxially grown on a single crystal sapphire substrate, there are materials as shown in FIG. Unit elements include silicon (Si), germanium (Ge), and selenium (Se), and compounds include zinc compounds (ZnO, ZnS, ZnSb), barium oxide (BaO), and cadmium compounds (CdS). , CdSe), gallium compounds (GaN ゝ GaAs), indium compounds (InP, InAs, InSb), germanium compounds (GeTe), lead compounds (PbS, PbSe, PbTe), vanadium compounds (VO), antimony compounds (Sb Te ), Bismuth
2 2 3 2 2 3
化合物(BiSe、 Bi Te )、セシウム化合物(Cs Sb)、酸化銅(Cu O)、ケィ素化合物 Compound (BiSe, BiTe), Cesium compound (Cs Sb), Copper oxide (Cu 2 O), Silicon compound
3 2 3 3 2 3 2 3 3 2
(SiC)、銀ィ匕合物 (AgSbTe、 AgBiS )などがある。 [0064] これらの電子デバイス素材を単結晶サファイア基板にェピタキシャル成長させ、図 1 8に示したようなダイオード(LEDや LD)やトランジスタ(HEMDTや FETなど)、 IC、 LSI,光電素子、整流素子、熱陰極、圧電素子、レーザ、ホール素子、熱電素子、バリ スタ、サーミスタなどに加工される。また SOS (silicon- ON- Sapphire)などの製造を行 うことも可能である。 (SiC), silver compounds (AgSbTe, AgBiS). [0064] These electronic device materials are epitaxially grown on a single crystal sapphire substrate, and diodes (LEDs and LDs), transistors (such as HEMDTs and FETs), ICs, LSIs, photoelectric devices, and rectifiers as shown in Figure 18 Processed into elements, hot cathodes, piezoelectric elements, lasers, Hall elements, thermoelectric elements, varistors, thermistors, etc. It is also possible to manufacture SOS (silicon-ON-Sapphire).
[0065] 特に、窒化ガリウム (GaN)は、青紫色ダイオードや白色ダイオードなどに利用され 注目されている。窒化ガリウム半導体は、青紫色ダイオードを実用化させ、発光ダイ オードによるフルカラーのディスプレイを誕生させた。また紫外光を発光させ白色蛍 光体と組み合わせ蛍光灯に代わる消費電力の低い光源としても利用が期待されてい る。この窒化ガリウムは、超高周波トランジスタとして実用化されているガリウムヒ素(G aAs)と元素周期律表上同じ、 3族と 5族の元素力もなる半導体である。そのため、ガリ ゥムヒ素の高キャリア移動と 、う特長を生力した超高周波トランジスタに加えて、窒化 ガリウムは、高出力動作可能な素子への利用の検討がなされている。 [0065] In particular, gallium nitride (GaN) is attracting attention as it is used for blue-violet diodes and white diodes. For gallium nitride semiconductors, blue-violet diodes have been put into practical use, and full-color displays using light-emitting diodes have been born. In addition, it is expected to be used as a light source with low power consumption to replace ultraviolet lamps by emitting ultraviolet light and combining with white phosphors. This gallium nitride is the same semiconductor as the gallium arsenide (GaAs), which has been put to practical use as an ultra-high frequency transistor, and has the same group 3 and 5 elemental power. For this reason, in addition to ultrahigh frequency transistors that have made the most of the high carrier mobility of gallium arsenide and gallium nitride, gallium nitride is being considered for use in devices capable of high power operation.
[0066] 電子デバイスは、一般的に図 19に示したようなプロセスで製造される。電子デバィ スの製造は、基板製造プロセス(1901)と、マスク製造プロセス(1902)、ウェハープ ロセス( 1903)、糸且立プロセス( 1904)の 4つのプロセスから成り立つ。 [0066] An electronic device is generally manufactured by a process as shown in FIG. Electronic device manufacturing consists of four processes: a substrate manufacturing process (1901), a mask manufacturing process (1902), a wafer process (1903), and a thread-and-stand process (1904).
[0067] 基板製造プロセスは、基板製造工程(1916)、スライシング工程(1917)、研磨ェ 程(1918)、熱処理工程(1919)の 4つの工程力もなる。基板製造プロセスでは、ま ず電子デバイスの基板の元となる単結晶サファイアなどのインゴットを製造する基板 製造工程(1916)を行う。単結晶サファイア力もなるインゴットは、チヨクラルスキー法 ( CZ法)やキロプロス法 (kyropoulusu法)などの結晶成長方法により製造される。インゴ ットは基板となる結晶の円柱状の塊であり、長さが約 2メートル、太さは 8インチから 12 インチであり、これらの大きさは、電子デバイスの目的や 1枚のウェハー上に作成され る電子デバイスの数に応じて変化させる。 [0067] The substrate manufacturing process also has four process forces: a substrate manufacturing process (1916), a slicing process (1917), a polishing process (1918), and a heat treatment process (1919). In the substrate manufacturing process, first, a substrate manufacturing process (1916) is performed to manufacture an ingot such as single crystal sapphire, which is a base of an electronic device substrate. Ingots with single-crystal sapphire power are produced by crystal growth methods such as the Chiyoklarsky method (CZ method) and the Kilopros method (kyropoulusu method). An ingot is a cylindrical mass of crystals that serve as a substrate, approximately 2 meters in length and 8 to 12 inches in thickness. These dimensions are for the purpose of electronic devices and on a single wafer. Vary depending on the number of electronic devices created.
[0068] 次に、この単結晶サファイアのインゴットを薄い板状のウェハーにカットするスライシ ング工程(1917)となる。スライシング工程は、インゴットを厚さ約 1ミリメートル程度の 円盤状にカットする。スライシング工程で行われるカッティング方法には主にブレード ソー方式とワイヤーソー方式の二つがある。ブレードソー方式は、図 20の a)に示すよ うにステンレス製高硬度鋼の内周刃(2001)を回転させてインゴット(2002)をカット する。切断面の平坦度が良好な点が特徴である。またワイヤーソー方式は、 b)に示し たように引張した複数のピアノ線(2003)にスラリー上のダイヤモンド砲粒を流し、ピ ァノ線を往復運動させながら、インゴット(2004)をカットする。ブレードソー方式に比 ベワイヤーソー方式は、切断面の平坦度は、ブレードソー方式におよばないが、スラ イス速度が速ぐコスト的に有利であり、大口径のウェハーの製造に有利である。尚、 単結晶サファイアカゝらなるインゴットをカットする場合には、インゴットをガラスや炭素を ホールド材として固定すると、切断方向に対してインゴットがずれるおそれがある。そ こでホールド材の材質に硬質炭酸カルシウムを用いることによって、切断角度のずれ を 0. 01度以内に納めることが可能である。 Next, a slicing step (1917) for cutting the single crystal sapphire ingot into a thin plate-like wafer is performed. In the slicing process, the ingot is cut into a disk shape with a thickness of about 1 mm. There are two main cutting methods used in the slicing process: blade saw method and wire saw method. The blade saw method is shown in Fig. 20 a). The ingot (2002) is cut by rotating the inner peripheral blade (2001) of high hardness stainless steel. The feature is that the flatness of the cut surface is good. In the wire saw method, as shown in b), ingots (2004) are cut while the diamond particles on the slurry are passed through a plurality of tensioned piano wires (2003) and reciprocating the piano wires. Compared to the blade saw method, the wire saw method has the same flatness of the cut surface as the blade saw method, but is advantageous in terms of cost because the slice speed is high, and is advantageous for manufacturing large-diameter wafers. When cutting an ingot made of a single crystal sapphire cover, if the ingot is fixed with glass or carbon as a holding material, the ingot may be displaced with respect to the cutting direction. Therefore, by using hard calcium carbonate as the material of the holding material, it is possible to keep the deviation of the cutting angle within 0.01 degrees.
[0069] スライシング工程が終了すると次は、研磨工程(1918)となる。研磨工程ではまず、 ウェハーの側面を機械研磨により研磨する。機械研磨には、細カゝぃ粒径の研磨剤の 研磨液を使って研磨を行う。側面を研磨した後、次にスライシング工程でカットした断 面の研磨である鏡面研磨を行う。鏡面研磨は、図 21に示した装置によって行われる 。回転する定盤(2101)の上に貼り付けられた研磨パッド(2102)に、ウェハー(210 3)を取り付けた研磨ヘッド(2104)を一定圧力で接触させてウェハーを研磨する。研 磨剤はスラリ一状の研磨液である。 [0069] When the slicing step is completed, the next step is a polishing step (1918). In the polishing process, first, the side surface of the wafer is polished by mechanical polishing. For mechanical polishing, polishing is performed using a polishing liquid of an abrasive with a fine particle size. After the side surfaces are polished, mirror polishing, which is polishing of the cross section cut in the slicing process, is performed. The mirror polishing is performed by the apparatus shown in FIG. The polishing head (2104) attached with the wafer (2103) is brought into contact with the polishing pad (2102) affixed on the rotating surface plate (2101) with a constant pressure to polish the wafer. The polishing agent is a slurry-like polishing liquid.
[0070] 研磨工程を経たウェハーは、洗浄後、熱処理工程となる。熱処理工程は、単結晶 サファイア力もなるウェハーの表面近傍での完全結晶層を確保するために行われる 。熱処理工程での詳細な熱処理方法については、実施形態 3にて述べたので、省略 する。 [0070] The wafer that has undergone the polishing step is subjected to a heat treatment step after washing. The heat treatment process is performed in order to secure a complete crystal layer near the surface of the wafer that also has a single crystal sapphire force. The detailed heat treatment method in the heat treatment step has been described in Embodiment 3, and will be omitted.
[0071] 一方、マスク製造プロセスでは、まず回路の設計を行い(1905)、次に設計された 回路をウェハー上に作り込む回路のパターンを設計する(1906)。そして、設計され たパターンをウェハー上に転写するためのマスクが製造される(1907)。マスクは、回 路を薄膜上に転写するためのリソグラフィー工程で用いられる。マスクは、石英製の 板表面にクロムなどにより、薄膜上に作り込む回路が形成されている。 On the other hand, in the mask manufacturing process, a circuit is first designed (1905), and then a circuit pattern for designing the designed circuit on the wafer is designed (1906). Then, a mask for transferring the designed pattern onto the wafer is manufactured (1907). The mask is used in a lithography process for transferring the circuit onto the thin film. The mask has a circuit formed on the thin film with chromium or the like on the surface of the quartz plate.
[0072] ウェハーとマスクが完成すると、次にウェハー上に回路を作り込む工程であるゥェ ハープロセスとなる。ウェハープロセスは、基板工程(1908)、リソグラフィー工程(19 09)、配線工程(1910)の大きく 3つのプロセス力もなる。基板工程とリソグラフィーェ 程、配線工程は、図 20に示したように、目的の電子デバイスの複雑さに応じて複数 回繰り返し行われる。 [0072] When the wafer and the mask are completed, a wafer process, which is a process for forming a circuit on the wafer, is performed. The wafer process consists of a substrate process (1908) and a lithography process (19 09) The wiring process (1910) has three major process forces. The substrate process, the lithography process, and the wiring process are repeated several times depending on the complexity of the target electronic device, as shown in FIG.
[0073] 基板工程は、洗浄工程 (2201)、熱処理工程 (2202)、不純物導入工程 (2203)、 膜形成工程(2204)、平坦ィ匕工程(2205)などの工程力もなる。 [0073] The substrate process also has process powers such as a cleaning process (2201), a heat treatment process (2202), an impurity introduction process (2203), a film formation process (2204), and a flattening process (2205).
[0074] 洗浄工程は、リソグラフィー工程や配線工程をはじめとする各工程間で必ず行われ る、表面清浄ィ匕のための工程である。この工程では、硫酸や塩酸、アンモニア、フッ 化水素、過酸ィ匕水素などの薬液を組み合わせて洗浄することが多い。洗浄による除 去の対象は、有機物残渣、酸化物残渣、金属汚染などである。また、場合によっては 、結晶の欠陥などのダメージの除去も洗浄工程とする場合もある。 The cleaning process is a process for surface cleaning that is always performed between each process including the lithography process and the wiring process. In this process, cleaning is often performed using a combination of chemicals such as sulfuric acid, hydrochloric acid, ammonia, hydrogen fluoride, and hydrogen peroxide. The object of removal by washing is organic residue, oxide residue, metal contamination and so on. In some cases, removal of damage such as crystal defects may also be a cleaning step.
[0075] 熱処理工程は、シリコン基板などの場合は必須で行われる工程である力 必ずしも 行わなければならない工程ではない。熱処理工程には、極めて清浄な雰囲気の炉が 用いられ、注意深く洗浄が行われたウェハーが用いられる。熱処理によりウェハー表 面に数百應の酸ィ匕膜が形成される。この膜は絶縁膜となりシリコンを用いた半導体 デバイス製造の出発点となる。 [0075] The heat treatment step is not necessarily a step that must be performed, which is an essential step in the case of a silicon substrate or the like. A very clean furnace is used for the heat treatment process, and a carefully cleaned wafer is used. By heat treatment, several hundreds of oxide films are formed on the wafer surface. This film becomes an insulating film and is the starting point for semiconductor device manufacturing using silicon.
[0076] 不純物導入工程は、シリコン基板などにホウ素ゃヒ素、リンなどの 3価および 5価族 元素を不純物として導入し pn結合の形成や不純物濃度制御を行う技術である。不純 物導入の方法としては、イオン打ち込み法や、熱拡散法、イオンドーピング法などが あるが、現在はイオン打ち込み法が主流である。イオン打ち込み法では、真空中で 分離されたホウ素、ヒ素リンなどのイオンに、高電圧をかけて加速し、基板中に打ち込 む。 [0076] The impurity introduction step is a technique for introducing a trivalent or pentavalent element such as boron arsenic or phosphorus as an impurity into a silicon substrate or the like to form a pn bond or control the impurity concentration. Impurity introduction methods include ion implantation, thermal diffusion, and ion doping. Currently, ion implantation is the mainstream. In the ion implantation method, ions such as boron and arsenic phosphorus separated in a vacuum are accelerated by applying a high voltage and implanted into a substrate.
[0077] 膜形成工程は、ウェハー上に気相エピタキシー(VPE : Vapor Phase Epitaxy)、分子 線エピタキシー(MBE: Molecular Beam Epitaxy)、液相エピタキシー(LPE: Liquid Ph ase Epitaxy)、固相エピタキシー(SPE: Solid Phase Epitaxy)などの方法によって様々 な物質をェピタキシャル成長させ、薄膜を形成させる工程である。 [0077] The film formation process is performed on a wafer by vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), solid phase epitaxy (SPE). : Solid Phase Epitaxy) is a process of epitaxially growing various substances to form thin films.
[0078] 気相成長法の一つであるハロゲン気相成長法(Hydride Vapor Phase Epitaxy : H VP E)による単結晶サファイア基板上への GaN結晶のェピタキシャル成長方法の一例の 概略図を図 23の(a)に、有機金属化合物気相成長法 (Meta卜 Organic Vapor Phase Epitaxy :MOVPE)による単結晶サファイア基板上への GaN結晶のェピタキシャル成 長方法の一例の概略図を図 23の(b)に示した。 HVPE法では、一般に 900°C程度の 高温に保持された金属ガリウムと塩ィ匕水素ガスを内部反応管にて反応させて主に塩 化ガリウムを生成し、 1000°C程度に保たれた単結晶サファイア基板付近でアンモ- ァと反応させて GaN結晶を成長させる。アンモニアおよび塩化水素はキャリアガスと 共に供給される。この方法では、塩ィ匕ガリウム生成部および単結晶サファイア基板の 2力所の温度制御と塩ィ匕水素ガスおよびアンモニアの流量制御が必須である。 MOV PE法では、一般的には単結晶サファイア基板のみが 1000°C程度に基板加熱用ヒ ータにより加熱され、そこにガリウムの原料となるガリウムと有機物の化合物である有 機金属化合物と窒素原料となるアンモニアがキャリアガスと共に輸送され、 GaN結晶 が成長する。この場合、加熱および温度制御が必要なのは、単結晶サファイア基板 のみである。 [0078] Figure 23 shows a schematic diagram of an example of an epitaxial growth method of GaN crystals on a single crystal sapphire substrate by the halogen vapor phase epitaxy (HVPE), which is one of the vapor phase growth methods. In (a), the metal-organic vapor phase growth method (Meta 卜 Organic Vapor Phase Fig. 23 (b) shows a schematic diagram of an example of an epitaxy growth method of GaN crystals on a single crystal sapphire substrate by Epitaxy (MOVPE). In the HVPE method, metallic gallium held at a high temperature of about 900 ° C and a hydrogen chloride gas are reacted in an internal reaction tube to mainly produce gallium chloride, and a single unit maintained at about 1000 ° C. A GaN crystal is grown by reacting with ammonia near the crystal sapphire substrate. Ammonia and hydrogen chloride are supplied with the carrier gas. In this method, it is essential to control the temperature at two locations, the salt gallium generator and the single crystal sapphire substrate, and the flow rate control of the salt hydrogen gas and ammonia. In the MOV PE method, generally, only a single crystal sapphire substrate is heated to about 1000 ° C by a substrate heating heater, and there is an organic metal compound, which is a compound of gallium and an organic material, and nitrogen. The raw ammonia is transported with the carrier gas, and GaN crystals grow. In this case, only the single crystal sapphire substrate needs heating and temperature control.
[0079] 平坦ィ匕工程は、ウェハー表面の凹凸を無くし、均一な表面形状とする工程である。 [0079] The flattening process is a process in which unevenness on the wafer surface is eliminated and a uniform surface shape is obtained.
平坦ィ匕工程で用いられる方法としては、エッチバック法などがあるが、代表的な方法 としては、化学的機械的研磨である。平坦ィ匕工程は、リソグラフィー工程における露 光で、深い焦点深度 (ピントが合う領域)を確保し、微細なパターンを露光したり、膜 形成工程において生じる段差を改善するための重要な工程である。 As a method used in the flattening step, there is an etch back method, but a typical method is chemical mechanical polishing. The flattening process is an exposure process in the lithography process, which is an important process for securing a deep depth of focus (a focused area), exposing fine patterns, and improving the level difference that occurs in the film formation process. .
[0080] リソグラフィー工程は、フォトレジスト塗布 (2206)、露光(2207)、現像(2208)、ェ ツチング(2209)、レジスト除去(2210)力もなる。リソグラフィー工程には、そのほか 様々な工程が入ることもある。リソグラフィー工程は、まず、 GaN結晶などの薄膜上に 、感光性榭脂であるフォトレジストを塗布し、 ICなどの回路パターンが形成されたマス クを通し、紫外線やエキシマレーザ光線、電子ビーム、 X線などを照射して露光しマ スクパターンを薄膜上に転写する。その後現像を行い薄膜上に回路を形成させエツ チング、レジスト除去を行う。 The lithography process also includes photoresist application (2206), exposure (2207), development (2208), etching (2209), and resist removal (2210). Various other processes may be included in the lithography process. In the lithography process, first, a photoresist, which is a photosensitive resin, is coated on a thin film such as a GaN crystal, and then passed through a mask on which a circuit pattern such as an IC is formed. Then, an ultraviolet ray, excimer laser beam, electron beam, X The mask pattern is transferred onto the thin film by exposing it to light. Development is then performed to form a circuit on the thin film, and etching and resist removal are performed.
[0081] 回路が薄膜上に形成されると、次に配線が行われる。配線工程は、膜形成工程 (2 211)、平坦ィ匕工程(2212)、洗浄工程(2213)など力もなる力 詳細については上 記の基板工程とほぼ共通であるため、説明は省略する。配線工程は、電子デバイス の層数に応じて何度も繰り返し行われる。 [0082] 配線が終了し、ウェハープロセスが終了すると、組立プロセスとなる。組立プロセス は、多数の電子デバイスが形成されたウェハーを切断し、一つ一つの電子デバイス とする、ダイシング工程(1911)、電子デバイスをフレーム上に乗せるマウント工程(1 912)、電子デバイスの電極とフレームを金の細線で接続するボンディング工程(191 3)、榭脂により電子デバイスを封入する封入工程(1914)、電子デバイスの良否を検 查する検査工程 (1915)からなる。検査が終了すると電子デバイスとして出荷される。 く実施形態 4 :効果〉 When the circuit is formed on the thin film, wiring is performed next. Since the wiring process is almost the same as the above-described substrate process in detail, the description thereof will be omitted because the film forming process (2 211), the flattening process (2212), the cleaning process (2213), etc. have the same force. The wiring process is repeated many times depending on the number of electronic device layers. When the wiring is completed and the wafer process is completed, the assembly process is started. The assembly process consists of dicing (1911), mounting (1 912) mounting the electronic device on the frame, and cutting the wafer on which a large number of electronic devices are formed into individual electronic devices. And a frame (1913) in which the frame is connected with a thin gold wire, an encapsulation process (1914) in which the electronic device is encapsulated with grease, and an inspection process (1915) in which the quality of the electronic device is checked. When the inspection is completed, it is shipped as an electronic device. <Embodiment 4: Effect>
[0083] 図 24に本実施形態の単結晶サフアイァ基板で作成した青色 LEDの順方向電圧に 対する出力の関係を示した。順方向電圧 (Vf)は P→N接合へ一定電流を流したとき の電圧、であり、出力は、積分球を用いてフォトディテクターで計測した。本実施形態 の単結晶サファイア基板に窒化ガリウム薄膜をェピタキシャル成長させ、青色 LEDを 製造した。本実施形態の単結晶サファイア基板で作成した青色 LEDは、従来技術に よって製造された青色 LEDに比べ、出力が高いことが明ら力となった。これは、結晶 方位が厳密に制御され、一定方向と均一高さを持つ真直ステップ、平坦なテラス、酸 素原子を終端とする単原子層サファイア基板の上に電子デバイス素材がェピタキシ ャル成長により形成され、より理想に近い結晶方位と平坦層を有し、欠陥の無い単結 晶サファイア基板が製造されて 、るためである。 FIG. 24 shows the relationship of the output with respect to the forward voltage of the blue LED produced by the single crystal sapphire substrate of this embodiment. The forward voltage (Vf) is the voltage when a constant current flows through the P → N junction, and the output was measured with a photodetector using an integrating sphere. A blue LED was manufactured by epitaxially growing a gallium nitride thin film on the single crystal sapphire substrate of this embodiment. The blue LED fabricated with the single crystal sapphire substrate of the present embodiment clearly has a higher output than the blue LED manufactured by the conventional technology. This is because the crystal orientation is strictly controlled, and the electronic device material is grown on the monolayer sapphire substrate terminated with a straight step, flat terrace, and oxygen atoms terminated in a constant direction and uniform height. This is because a single-crystal sapphire substrate that is formed and has a crystal orientation and a flat layer that are closer to the ideal and has no defects is manufactured.
図面の簡単な説明 Brief Description of Drawings
[0084] [図 1]単結晶サファイア基板表面の概念図 [0084] [Fig.1] Conceptual diagram of the surface of single crystal sapphire substrate
[図 2]実施形態 1の単結晶サファイア基板表面を示した図 FIG. 2 shows a surface of a single crystal sapphire substrate of Embodiment 1.
[図 3]単結晶サファイアの結晶形態を示した図 [Figure 3] Diagram showing the crystal morphology of single crystal sapphire
圆 4]マクロ的表面を説明する図 圆 4] Diagram explaining macroscopic surface
[図 5]単結晶サファイア基板の AFM測定データ [Figure 5] AFM measurement data of single crystal sapphire substrate
[図 6]サファイアの結晶構造を説明する概念図 [Fig.6] Conceptual diagram explaining the crystal structure of sapphire
[図 7]サファイア単結晶を C面最表面を表した概念図 [Fig.7] Conceptual diagram of the C-plane outermost surface of a sapphire single crystal
[図 8]サファイア単結晶を切断した時の断面図透視 [Fig.8] Cross section perspective when sapphire single crystal is cut
[図 9]ステップの形成されたサファイア単結晶を切断した時の断面図透視図 [Fig.9] Cross-sectional perspective view of a sapphire single crystal with a step cut
[図 10]C面を主面とする単結晶サファイア基板の LEISS測定データ [図 11]実施形態 3の真空加熱炉の一例 [Fig.10] LEISS measurement data of single crystal sapphire substrate with C-plane as main surface [Fig. 11] Example of vacuum heating furnace of Embodiment 3
[図 12]実施形態 3の大気加熱炉の一例 [Fig. 12] Example of atmospheric heating furnace of Embodiment 3
圆 13]実施形態 3の単結晶サファイア基板の製造方法を示すフローチヤ 圆 14]実施形態 3の単結晶サファイア基板の製造方法を示すフローチヤ 圆 15]実施形態 3の単結晶サファイア基板の熱処理温度変化 圆 16]実施形態 3の単結晶サファイア基板の熱処理温度変化 圆 13] Flow chart showing the method of manufacturing the single crystal sapphire substrate of Embodiment 3 圆 14] Flow chart showing the method of manufacturing the single crystal sapphire substrate of Embodiment 3 圆 15] Change in heat treatment temperature of the single crystal sapphire substrate of Embodiment 3 圆16] Change in heat treatment temperature of single crystal sapphire substrate of embodiment 3
[図 17]実施形態 3の単結晶サファイア基板の AFM測定画像 FIG. 17: AFM measurement image of single crystal sapphire substrate of Embodiment 3.
圆 18]実施形態 4の電子デバイスの製造方法を説明するための図 圆 19]実施形態 4の電子デバイス製造方法の流れを説明するための図 圆 20]実施形態 4のウェハーの切断方法を説明するための図 圆 21]実施形態 4のウェハーの研磨方法を説明するための図 圆 22]実施形態 4の電子デバイス製造方法を説明するための図 圆 23]実施形態 4の電子デバイス製造方法を説明するための図 圆 24]実施形態 4の電子デバイスの最大順方向電圧測定結果 圆 18] Diagram for explaining the electronic device manufacturing method of Embodiment 4 実 施 19] Diagram for explaining the flow of the electronic device manufacturing method of Embodiment 4 の 20] The wafer cutting method of Embodiment 4 FIG. 21] A diagram for explaining the wafer polishing method of the fourth embodiment. FIG. 22] A diagram for explaining the electronic device manufacturing method of the fourth embodiment. FIG. 23] The electronic device manufacturing method of the fourth embodiment. Illustration 圆 24] Maximum forward voltage measurement result of electronic device of Embodiment 4
[図 25]A面を主面とする単結晶サファイア基板の LEISS測定データ 符号の説明 [Fig.25] LEISS measurement data of single crystal sapphire substrate with A-plane as main surface Explanation of symbols
0201 テラス面 0201 Terrace
0202 ステップ面 0202 Step side
0203 マクロ的表面の端線 0203 Macroscopic edge
0204 エッジ 0204 Edge
0205 マクロ的表面 0205 Macroscopic surface
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CN102634850A (en) * | 2012-03-31 | 2012-08-15 | 江苏鑫和泰光电科技有限公司 | Annealing method of sapphire wafer |
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CN104755660A (en) * | 2012-10-31 | 2015-07-01 | 蓝宝石科技株式会社 | Heat treatment method and heat treatment device for single crystal sapphire |
WO2016153070A1 (en) * | 2015-03-26 | 2016-09-29 | 京セラ株式会社 | Sapphire member and method for manufacturing sapphire member |
US20190024258A1 (en) * | 2016-03-30 | 2019-01-24 | Nikon Corporation | Aluminum oxide, method for manufacturing aluminum oxide and optical component |
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