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WO2007106627A3 - Silicon deposition over dual surface orientation substrates to promote uniform polishing - Google Patents

Silicon deposition over dual surface orientation substrates to promote uniform polishing Download PDF

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Publication number
WO2007106627A3
WO2007106627A3 PCT/US2007/062096 US2007062096W WO2007106627A3 WO 2007106627 A3 WO2007106627 A3 WO 2007106627A3 US 2007062096 W US2007062096 W US 2007062096W WO 2007106627 A3 WO2007106627 A3 WO 2007106627A3
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WO
WIPO (PCT)
Prior art keywords
over
silicon
gate electrodes
layer
surface orientation
Prior art date
Application number
PCT/US2007/062096
Other languages
French (fr)
Other versions
WO2007106627A2 (en
Inventor
Gregory S Spencer
Peter J Beckage
Mariam G Sadaka
Original Assignee
Freescale Semiconductor Inc
Gregory S Spencer
Peter J Beckage
Mariam G Sadaka
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Gregory S Spencer, Peter J Beckage, Mariam G Sadaka filed Critical Freescale Semiconductor Inc
Priority to CN2007800085722A priority Critical patent/CN101401297B/en
Publication of WO2007106627A2 publication Critical patent/WO2007106627A2/en
Publication of WO2007106627A3 publication Critical patent/WO2007106627A3/en

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    • H—ELECTRICITY
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02367—Substrates
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    • H01L21/02494—Structure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
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    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline silicon (101, 103) over the nitride mask layer (95). The polysilicon material (101, 103) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface (100) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes (151) over a first SOI layer (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon layer (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
PCT/US2007/062096 2006-03-14 2007-02-14 Silicon deposition over dual surface orientation substrates to promote uniform polishing WO2007106627A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2007800085722A CN101401297B (en) 2006-03-14 2007-02-14 Silicon deposition over dual surface orientation substrates to promote uniform polishing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/375,796 2006-03-14
US11/375,796 US7754587B2 (en) 2006-03-14 2006-03-14 Silicon deposition over dual surface orientation substrates to promote uniform polishing

Publications (2)

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WO2007106627A2 WO2007106627A2 (en) 2007-09-20
WO2007106627A3 true WO2007106627A3 (en) 2007-12-13

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US (1) US7754587B2 (en)
KR (1) KR20080109757A (en)
CN (1) CN101401297B (en)
TW (1) TW200739820A (en)
WO (1) WO2007106627A2 (en)

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US7524707B2 (en) * 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
US7986029B2 (en) * 2005-11-08 2011-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Dual SOI structure
US7776679B2 (en) * 2007-07-20 2010-08-17 Stmicroelectronics Crolles 2 Sas Method for forming silicon wells of different crystallographic orientations
EP2203934A1 (en) * 2007-10-18 2010-07-07 Nxp B.V. Method of manufacturing localized semiconductor-on-insulator (soi) structures in a bulk semiconductor wafer
US9595479B2 (en) * 2008-07-08 2017-03-14 MCube Inc. Method and structure of three dimensional CMOS transistors with hybrid crystal orientations
US8093084B2 (en) 2009-04-30 2012-01-10 Freescale Semiconductor, Inc. Semiconductor device with photonics
CN101986435B (en) * 2010-06-25 2012-12-19 中国科学院上海微系统与信息技术研究所 Manufacturing method of metal oxide semiconductor (MOS) device structure for preventing floating body and self-heating effect
US8614478B2 (en) * 2010-07-26 2013-12-24 Infineon Technologies Austria Ag Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor
US8786012B2 (en) 2010-07-26 2014-07-22 Infineon Technologies Austria Ag Power semiconductor device and a method for forming a semiconductor device
US9105660B2 (en) * 2011-08-17 2015-08-11 United Microelectronics Corp. Fin-FET and method of forming the same
US8963208B2 (en) * 2012-11-15 2015-02-24 GlobalFoundries, Inc. Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
US20170018427A1 (en) * 2015-07-15 2017-01-19 Applied Materials, Inc. Method of selective epitaxy
US10727374B2 (en) * 2015-09-04 2020-07-28 Seoul Semiconductor Co., Ltd. Transparent conductive structure and formation thereof
US10438838B2 (en) * 2016-09-01 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and related method
US11004958B2 (en) 2018-10-31 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
CN112242342B (en) * 2019-07-17 2024-12-10 上海新微技术研发中心有限公司 Single crystal silicon local SOI substrate, optoelectronic device and preparation method
US12191142B2 (en) * 2021-07-22 2025-01-07 Changxin Memory Technologies, Inc. Semiconductor structure and method for manufacturing semiconductor structure

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Publication number Publication date
WO2007106627A2 (en) 2007-09-20
TW200739820A (en) 2007-10-16
US20070218654A1 (en) 2007-09-20
KR20080109757A (en) 2008-12-17
CN101401297B (en) 2011-09-14
CN101401297A (en) 2009-04-01
US7754587B2 (en) 2010-07-13

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