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WO2007099621A1 - Appareil de communication - Google Patents

Appareil de communication Download PDF

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Publication number
WO2007099621A1
WO2007099621A1 PCT/JP2006/303866 JP2006303866W WO2007099621A1 WO 2007099621 A1 WO2007099621 A1 WO 2007099621A1 JP 2006303866 W JP2006303866 W JP 2006303866W WO 2007099621 A1 WO2007099621 A1 WO 2007099621A1
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WO
WIPO (PCT)
Prior art keywords
circuit
amplifier circuit
signal
frequency amplifier
frequency
Prior art date
Application number
PCT/JP2006/303866
Other languages
English (en)
Japanese (ja)
Inventor
Masaru Sawada
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/303866 priority Critical patent/WO2007099621A1/fr
Publication of WO2007099621A1 publication Critical patent/WO2007099621A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
    • H04B1/406—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with more than one transmission mode, e.g. analog and digital modes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/7163—Spread spectrum techniques using impulse radio
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices

Definitions

  • the present invention relates to a communication device.
  • UWB Ultra wideband wireless communication
  • unlicensed wireless communication networks used in the fields of personal computers, personal digital assistants, and home appliances.
  • technical issues there are the following technical issues.
  • Patent Document 1 describes a multiband radio device having an HF synthesizer that generates a first reference frequency signal in a high band and an LF synthesizer that generates a second reference frequency signal. .
  • Patent Document 2 describes a receiving apparatus that is used in combination as a calibration circuit when a phase variable circuit is calibrated in a non-reception mode.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-64397
  • Patent Document 2 Japanese Patent Laid-Open No. 2002-135186
  • An object of the present invention is to provide a communication device that can amplify a received signal in a wide frequency band.
  • an antenna for receiving a radio signal, a low-frequency amplifier circuit for amplifying a low-frequency signal received via the antenna, and a reception via the antenna
  • a communication device including a high frequency amplifier circuit for amplifying the high frequency signal.
  • FIG. 1 is a block diagram showing a configuration example of a UWB communication apparatus according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing a band group of a multiband orthogonal wave frequency division multiplexing system.
  • FIG. 3 is a flowchart showing processing of the UWB communication apparatus.
  • FIG. 4 is a diagram showing a configuration example of a communication frame of the UWB communication apparatus.
  • FIG. 5 is a block diagram showing a configuration example of a UWB communication apparatus according to a second embodiment of the present invention.
  • FIG. 6 is a block diagram showing a configuration example of a UWB communication apparatus according to a third embodiment of the present invention.
  • FIG. 2 shows a multi-band orthogonal frequency division multiplexing (MB-OFDM) according to the first embodiment of the present invention.
  • MB-OFDM multi-band orthogonal frequency division multiplexing
  • the UWB is 3.1-: LO. 6 MHz, and has a first band group 201 to a fifth band group 205.
  • the first band group 201 includes a first band 211 having a center frequency of 3432 MHz, a second node 212 having a center frequency of 3960 MHz, and a third band 213 having a center frequency force of 488 ⁇ .
  • the second band group 202 includes a fourth band 214 having a center frequency of 5016 MHz, a fifth band 215 having a center frequency of 5544 MHz, and a sixth band 216 having a center frequency power of 072 MHz.
  • the third band group 203 includes a seventh node 217 having a center frequency of 6600 MHz, an eighth band 218 having a center frequency of 7128 MHz, and a ninth band 219 having a center frequency of 7656 MHz.
  • the fourth band group 204 includes a tenth node 220 having a center frequency of 8184 MHz, an eleventh band 221 having a center frequency of 8712 MHz, and a twelfth band 222 having a center frequency of 9240 MHz.
  • the fifth band group 205 includes a thirteenth band 223 having a center frequency of 9768 MHz and a fourteenth band 224 having a center frequency of 10296 MHz.
  • a UWB band is divided into a plurality of band groups 201 to 205, and each band group is frequency-hopped to perform wideband transmission.
  • each band group is frequency-hopped to perform wideband transmission.
  • three bands 211 to 213 are switched according to time.
  • FIG. 1 is a block diagram illustrating a configuration example of the UWB communication apparatus according to the present embodiment.
  • the antenna 101 has an antenna gain of OdB and transmits / receives a radio signal.
  • the bandpass filter 102 filters the input signal, passes only a signal in a predetermined frequency band, and removes noise.
  • the antenna 101 is connected to the physical layer circuit 100 via the bandpass filter 102.
  • the physical layer circuit 100 includes a transmission circuit and a reception circuit.
  • the digital signal processor (DSP) 121 digitally processes the transmission signal, outputs the I signal to the digital Z analog converter 1221, and outputs the Q signal to the digital Z analog converter 122Q.
  • the I signal and the Q signal are signals orthogonal to each other.
  • the digital Z analog converter 1221 converts the I signal into a digital signal and outputs it to the baseband circuit 123.
  • the digital Z analog converter 122Q converts the Q signal into a digital signal and outputs the analog signal to the baseband circuit 123.
  • the baseband circuit 123 shapes the I signal and Q signal and outputs them to the modulation circuit 124.
  • the modulation circuit 124 modulates the I signal and the Q signal based on the signal input from the synthesizer 112 and outputs the transmission signal to the bandpass filter 125.
  • the bandpass filter 125 filters the input signal, passes only a signal in a predetermined frequency band, and removes noise.
  • the power amplifier 126 amplifies the output signal of the bandpass filter 125 and outputs the amplified signal to the antenna 101 via the selector (selection circuit) 103 and the bandpass filter 102.
  • the selector 103 is connected to the power amplifier 126 in the transmission mode.
  • the antenna 101 transmits the transmission signal by radio.
  • the selector 103 is connected to the low-frequency low-noise amplifier circuit 105L and the selector 104 in the reception mode.
  • the low-frequency low-noise amplifier circuit 105 L is an amplifier circuit for amplifying the low-frequency signal from the selector 103, and outputs the amplified signal to the demodulator circuit 106L.
  • the amplifier circuit 105L receives power when the power-down signal PDL is canceled and stops power supply when the power-down signal PDL is activated. It is.
  • the low frequency demodulation circuit 106L demodulates the output signal of the amplification circuit 105L based on the low frequency signal input from the low frequency synthesizer 112, and generates an I signal and a Q signal.
  • a low-frequency amplifier circuit 105L suitable for amplifying a low-frequency signal and a high-frequency amplifier circuit 105H suitable for amplifying a high-frequency signal are provided. As a result, a received signal in a wide frequency band can be appropriately amplified.
  • the selector 104 selects the output signal of the selector 103 or the output signal of the high frequency synthesizer 116 and outputs it to the high frequency low noise amplification circuit 105H.
  • the selector 104 selects and outputs the output signal of the high frequency synthesizer 116 in the calibration (characteristic adjustment) mode, and selects and outputs the output signal of the selector 103 in the reception mode.
  • the high frequency low noise amplification circuit 105H is an amplification circuit for amplifying the high frequency signal from the selector 104, and outputs the amplified signal to the demodulation circuit 106H.
  • the amplifier circuit 105H receives power supply when the power down signal PDH is canceled and stops power supply when the power down signal PDL is activated.
  • the high frequency demodulation circuit 106H demodulates the output signal of the amplification circuit 105H based on the high frequency signal input from the high frequency synthesizer 116, and generates an I signal and a Q signal.
  • Synthesizers 112 and 116 are phase-locked loop (PLL) circuits.
  • the selector 107 selects an output signal of the low band demodulation circuit 106L or the high band demodulation circuit 106H according to the control signal, and outputs it to the baseband circuit 108.
  • the selector 107 selects and outputs the I signal and the Q signal output from the low-frequency demodulation circuit 106L when the low-frequency band group (channel) 201 is assigned as a use frequency, and outputs a high-frequency band loop ( Channel)
  • the I and Q signals output from the high frequency demodulation circuit 106H are selected and output.
  • the baseband circuit 108 shapes the I signal and the Q signal, outputs the I signal to the auto gain controller (AGC) 1091, and outputs the Q signal to the auto gain controller (AGC) 109Q.
  • the auto gain controller 1091 controls the gain of the I signal according to the full range of the analog Z / digital converter 1101.
  • Auto gain controller 109Q Z Digital converter Controls the gain of the Q signal according to the full range of the 110Q.
  • the analog / digital converter 1101 converts the output signal of the auto gain controller 1091 into digital as well.
  • the analog / digital converter 110Q converts the output signal of the auto gain controller 109Q into a digital signal.
  • the DSP 111 digitally processes the output signals of the analog Z / digital converters 1101 and 110Q.
  • the UWB communication apparatus handles a weak received signal with a wide frequency band to be used. For this reason, the higher the frequency of the received signal, the greater the effect of variations in elements within the receiving circuit. For example, device variations increase with changes in temperature, Z, or power supply voltage. Therefore, it is necessary to provide a calibration circuit and carry out calibration (characteristic adjustment) of the high frequency amplifier circuit 105H.
  • the high frequency synthesizer 116 outputs a calibration signal to the high frequency amplifier circuit 105H via the selector 104.
  • the selector 104 selects and outputs a calibration signal in the calibration mode.
  • the high frequency amplifier circuit 105H amplifies the calibration signal.
  • the output level detection circuit 113 detects the level (for example, voltage level) of the output signal of the high frequency amplification circuit 105H.
  • the sequencer (control circuit) 114 controls the bias control circuit 115 and the high frequency synthesizer 116 based on the level detected by the output level detection circuit 113.
  • the bias control circuit 115 adjusts the bias (for example, bias voltage) of the high frequency amplifier circuit 105H according to the detected level.
  • the gain of the high-frequency amplifier circuit 105H changes according to the bias.
  • the high frequency synthesizer 116 sweeps (changes) the frequency under the control of the sequencer 114, and sequentially outputs calibration signals to the high frequency amplifier circuit 105H.
  • the calibration circuit adjusts the bias of the high-frequency amplifier circuit 105H based on the output level of the high-frequency amplifier circuit 105H for the calibration signals of a plurality of frequencies.
  • the calibration circuit adjusts and optimizes the bias of the high-frequency amplifier circuit 105H, thereby preventing variations in the amplification factor of the high-frequency amplifier circuit 105H due to temperature, Z, or power supply voltage. be able to.
  • FIG. 4 is a diagram showing a configuration example of a communication frame of the UWB communication apparatus according to the present embodiment.
  • the communication frame (superframe) FR includes a beacon 401, a CAP 402, and a GTS 403.
  • a network is established using only the band group 201 in the low band, and the medium band power of the entire band group power used by the physical layer circuit 100 of each communication device is allocated.
  • CAP 402 is a collision allowable access time, and is a period for determining a data rate and an assigned channel (band group).
  • GTS 403 is an occupied slot time and is a communication occupied time assigned to a communication device in the network.
  • the low frequency receiving circuit includes a low frequency amplifying circuit 105L and a low frequency demodulating circuit 106L.
  • the high frequency receiving circuit includes a high frequency amplifying circuit 105H and a high frequency demodulating circuit 106H.
  • Periods TL1 and TH1 are periods (including beacons 401 and CAP402) from communication device power-on to CAP402.
  • Periods TL2 and TH2 are periods (including GTS403) from the end of CAP 402 to the start of beacon 401 of the next communication frame FR.
  • Periods TL1 and TL2 indicate the processing period of the low-frequency receiving circuit.
  • Periods TH1 and TH2 indicate the processing period of the high-frequency receiving circuit.
  • the low-frequency receiving circuit performs processing of the beacon 401 and the CAP 402 in the period TL1, and determines an allocation channel.
  • a case will be described in which any one of the high frequency band groups 202 to 205 is assigned and the high frequency channel mode MH is set.
  • the high frequency receiving circuit is not used, and only the low frequency receiving circuit is used. Therefore, while the low-frequency receiving circuit performs processing in the period TL1, the high-frequency receiving circuit performs the above-described calibration processing in the period TH1 to adjust the bias of the high-frequency amplifier circuit 105H.
  • the high-frequency receiving circuit communicates with the GTS 403 using the high-frequency band group allocated in the period TH2.
  • the power down signal PDL is activated and the power supply to the low frequency amplifying circuit 105L is stopped in the period TL2.
  • the power supply to the low frequency demodulation circuit 106L may be stopped.
  • Periods TL11 and TH11 are the period (including beacon 401 and CAP402) from the power-on of the communication device to CAP402.
  • the Periods TL12 and TH12 are periods (including GTS403) from the end of CAP 402 to the start of beacon 401 of the next communication frame FR.
  • Periods TL11 and TL12 indicate the processing period of the low-frequency receiving circuit.
  • Periods TH11 and TH12 indicate the processing period of the high-frequency receiving circuit.
  • the low-frequency receiving circuit performs processing of the beacon 401 and the CAP 402 in the period TL11 to determine the allocation channel.
  • the high frequency receiving circuit is not used, and only the low frequency receiving circuit is used. Therefore, while the low-frequency receiving circuit performs processing in the period TL11, the high-frequency receiving circuit performs the above-described calibration processing in the period T HI 1 to adjust the bias of the high-frequency amplifier circuit 105H. .
  • the low-frequency receiving circuit communicates with the GTS 403 using the low-frequency band group 201 assigned in the period TL12.
  • the power down signal PDH is activated and the power supply to the high frequency amplifying circuit 105H is stopped.
  • the power supply to the high frequency demodulation circuit 106H may be stopped.
  • the selector 107 selects and outputs a signal based on the output of the low-frequency amplifier circuit 105L, performs communication using the low-frequency signal, and assigns a use frequency band. In the meantime, the calibration circuit adjusts the bias of the high frequency amplifier circuit 105H.
  • FIG. 3 is a flowchart showing processing of the UWB communication apparatus according to the present embodiment.
  • the UWB communication device When the power of the B communication device is turned on, the UWB communication device performs the following processing.
  • step S301 the power-down signals PDL and PDH are canceled, and power is supplied to the low-frequency receiving circuit (low-frequency RF circuit) and the high-frequency receiving circuit (high-frequency RF circuit).
  • step S302 transmission / reception is awaited.
  • the low-frequency receiving circuit is in the receiving state.
  • the high frequency receiving circuit waits for the waiting time of the calibration process.
  • the waiting time is, for example, several ms. This standby can stabilize the temperature state of the communication device.
  • the following calibration process is performed. Immediately after the power is turned on, the radiation of the radio wave is low! / By releasing the power down signals PDL and PDH of the receiver circuit, the temperature rise of the LSI board of the communication device can be accelerated. As a result, the low-voltage power supply can be stabilized.
  • step S303 the high-frequency receiving circuit starts a calibration process.
  • the high frequency synthesizer (PLL circuit) 116 oscillates a calibration signal of the first frequency under the control of the sequencer 114 and outputs it to the high frequency amplifier circuit 105H.
  • the bias control circuit 115 initializes the bias under the control of the sequencer 114 and outputs the result to the high frequency amplifier circuit 105H.
  • step S304 the output level detection circuit 113 measures the output level of the high frequency amplification circuit 105H for the calibration signal of the first frequency.
  • step S305 the high-frequency receiving circuit starts the i-th calibration process.
  • i 2.
  • the high frequency synthesizer (PLL circuit) 116 oscillates a calibration signal of the i-th frequency under the control of the sequencer 114 and outputs it to the high frequency amplifier circuit 105H.
  • step S306 the output level detection circuit 113 measures the output level of the high frequency amplification circuit 105H for the calibration signal of the i-th frequency.
  • step S307 it is checked whether i is a predetermined number n or less. If i is less than or equal to n, i is incremented, and the process returns to step S305 to perform the i-th calibration treatment in the same manner as described above. If i is greater than n, go to step S308. From this, it is possible to measure the output level of the high frequency amplifier circuit 105H for n frequencies by sweeping (changing) the frequency.
  • n is an integer of 2 or more. Multiple frequencies Calibration accuracy can be improved by performing calibration based on the current output level. It is not limited to multiple frequencies, but you may perform calibration using a single frequency.
  • step S308 the sequencer 114 refers to the table and controls the bias via the bias control circuit 115 based on the above-mentioned n output levels.
  • the bias control circuit 115 adjusts (updates) the bias supplied to the high frequency amplifier circuit 105H according to the control.
  • step S309 it is checked whether calibration is completed. If the communication device is not yet stable and the above n output levels are unstable, the process proceeds to step S310. When proper bias adjustment is completed by calibration, go to step S311 until the adjustment is completed.
  • step S310 the same processing as step S303 is performed. That is, a high frequency synthesizer
  • (PLL circuit) 116 oscillates a calibration signal of the first frequency under the control of the sequencer 114, and outputs it to the high frequency amplifier circuit 105H. Thereafter, the process returns to step S304, and the above processing is repeated.
  • step S311 the selector 104 connects the input of the high frequency amplification circuit 105H to the selector 103, and puts the high frequency reception circuit into a reception state.
  • step S312 it is checked which of the high frequency receiving circuit and the low frequency receiving circuit is received.
  • the beacon 401 and the CAP 402 described above determine the high band channel mode ⁇ or the low band channel mode ML. If it is the high frequency channel mode MH, the process proceeds to step S313, and if it is the low frequency channel mode ML, the process proceeds to step S314.
  • step S313 the high-frequency receiving circuit performs reception, and the low-frequency receiving circuit powers down.
  • the selector 107 selects the output signal of the high frequency demodulation circuit 106H and outputs it to the baseband circuit 108.
  • step S314 the low-frequency receiving circuit performs reception, and the high-frequency receiving circuit powers down.
  • the selector 107 selects the output signal of the low frequency demodulation circuit 106L and outputs it to the baseband circuit 108.
  • the selector 107 performs the low frequency amplification circuit. Select and output a signal based on the output of the circuit 105L or the high-frequency amplifier circuit 105H, to the amplifier circuit corresponding to the selected signal of the low-frequency amplifier circuit 105L and the high-frequency amplifier circuit 105H Stop the power supply.
  • the MB-OFDM receiver circuit hops three bands (frequencies) in a band group, so it does not use the entire band at once, but reduces the frequency band for each band group band (1.5 GHz).
  • the amplifier circuit 105L or the high-frequency amplifier circuit 105H is switched.
  • the unused amplifier circuit 105 L or 105H suppresses an increase in power consumption by powering down.
  • the bias value by calibration is stored in the sequencer 114, so that it can return to the operating state immediately after canceling the power-down.
  • the high frequency amplifier circuit 105H has a wide frequency band of the input signal, calibration for a wide frequency band is required.
  • the high frequency synthesizer 116 generates a calibration signal for the center frequency of each band group and performs calibration.
  • the low-frequency amplifier circuit 105L for amplifying the low-frequency signal received via the antenna 101, and the high-frequency signal received via the antenna 101 A high-frequency amplifier circuit 105H for amplification.
  • the low-frequency signal is the band group 201 and the high-frequency signal is the band group 202 to 205 is described.
  • the boundary between the low-frequency signal and the high-frequency signal is not limited to this.
  • This high frequency signal is a signal having a higher frequency than the low frequency signal.
  • the calibration circuit inputs a calibration signal having a plurality of frequencies to the high-frequency amplifier circuit 105H, and the high-frequency amplifier circuit 105H according to the multi-frequency output signal of the high-frequency amplifier circuit 105H. Adjust the bias.
  • the selector 107 selects and outputs a signal based on the output of the low-frequency amplifier circuit 105L or the high-frequency amplifier circuit 105H.
  • the calibration circuit adjusts the bias of the high-frequency amplifier circuit 105H while the selector 107 selects and outputs a signal based on the output of the low-frequency amplifier circuit 105L.
  • the UWB communication device it is necessary to match in a wide band at the input stage of the amplifier circuit of the receiving circuit. Matching is caused by fluctuations in the transconductance (gm) of MOS field-effect transistors. It may not be obtained and the reception state may deteriorate.
  • the amplifier circuit is divided into a low-frequency amplifier circuit 105L and a high-frequency amplifier circuit 105H, and the reception band is divided and received, thereby limiting the adjustment range of the circuit constants of the amplifier circuits 105L and 105H. Convergence can be improved.
  • a plurality of amplifier circuits 105L and 105H may be calibrated. Further, the present invention is not limited to the case where the amplifier circuit is divided into two amplifier circuits 105L and 105H, and may be divided into three or more.
  • the convergence of the calibration can be improved by adjusting the low-frequency side power sequentially the high-frequency amplifier circuit.
  • the high frequency side is more sensitive to the bias being adjusted. By adjusting from the low range, convergence can be improved while maintaining accuracy.
  • FIG. 5 is a block diagram showing a configuration example of the UWB communication apparatus according to the second embodiment of the present invention. In the following, the difference of this embodiment from the first embodiment will be described. This embodiment differs from the first embodiment in the calibration circuit.
  • the high frequency synthesizer 116 generates a calibration signal under the control of the microprocessor 503 and outputs it to the selector 504.
  • the selector 504 selects the output signal of the high-frequency synthesizer 116 or the band-pass filter 125 and outputs it to the power amplifier 126.
  • the selector 504 selects and outputs the output signal of the high frequency synthesizer 116 during calibration, and selects and outputs the output signal of the bandpass filter 125 during transmission.
  • the selector 104 selects either the output signal of the power amplifier 126 or the selector 103 and outputs the selected signal to the high frequency amplifier circuit 105H.
  • the selector 104 selects and outputs the output signal of the power amplifier 126 during calibration, and selects and outputs the output signal of the selector 103 during reception.
  • the power amplifier 126 amplifies the calibration signal generated by the high frequency synthesizer 116.
  • the high frequency amplifying circuit 105H amplifies and outputs the calibration signal output from the power amplifier 126.
  • Bandpass filter for high frequencies 501 filters the output signal of the high frequency amplification circuit 105H, passes only a signal in a predetermined frequency band, and removes noise.
  • the comparison circuit 502 compares the output signal of the bandpass filter 501 and the reference level REF, and outputs a comparison result.
  • the microprocessor 503 adjusts the bias of the high frequency amplifier circuit 105H according to the comparison result. In other words, the bias of the high frequency amplifier circuit 105H is adjusted so that the output voltage of the high frequency amplifier circuit 105H is equal to the reference voltage REF.
  • the calibration circuit inputs the calibration signal to the high frequency amplifier circuit 105H via the transmission amplifier circuit 126 for amplifying the transmission signal. Then, the bias of the high frequency amplifier circuit 105H is adjusted according to the output signal of the high frequency amplifier circuit 105H.
  • the high-frequency amplifier circuit 105H is calibrated using the transmission amplifier circuit 126.
  • analog circuits are calibrated by keeping the transistor transconductance (gm) constant.
  • This embodiment uses the low transmission power of the weak wireless system, and the output signal of the transmission amplifier circuit 126 is input to the high-frequency amplifier circuit 105H inside the communication device (LSI), and the high-frequency amplifier circuit Calibrating 105H has the effect of optimizing wideband matching.
  • the amplification circuit is limited to two stages in the MOS field effect transistor cascode configuration. Since high-frequency signals are easily affected by parasitic elements, adjustment elements such as switching transistor switches should be removed as much as possible. By performing calibration using feedback, the number of adjustment elements in the main body of the high-frequency amplifier circuit 105H can be reduced.
  • FIG. 6 is a block diagram showing a configuration example of the UWB communication apparatus according to the third embodiment of the present invention.
  • This embodiment differs from the second embodiment in the calibration circuit.
  • the selector 504 of the second embodiment is deleted.
  • the selector 104 selects the output signal or reference potential of the selector 103 and outputs it to the high frequency amplifier circuit 105H.
  • the selector 104 selects and outputs a reference potential during calibration. When receiving, the output signal of the selector 103 is selected and output.
  • the selector 601 selects the output signal or reference potential of the selector 103 and outputs the selected signal to the low-frequency amplifier circuit 105L.
  • the selector 601 selects and outputs the reference potential during calibration, and selects and outputs the output signal of the selector 103 during reception.
  • the high-frequency amplifier circuit 105H and the low-frequency amplifier circuit 105L amplify and output the reference potential.
  • the high-frequency bandpass filter 501 filters the output signal of the high-frequency amplifier circuit 105H, passes only a signal in a predetermined frequency band, and removes noise.
  • the low-frequency bandpass filter 602 filters the output signal of the low-frequency amplifier circuit 105L, passes only a signal in a predetermined frequency band, and removes noise.
  • the comparison circuit 502 compares the output signals of the bandpass filters 501 and 602 and outputs a comparison result.
  • the microprocessor 503 adjusts the bias of the high frequency amplifier circuit 105H according to the comparison result. That is, the bias of the high frequency amplifier circuit 105H is adjusted so that the output voltage of the high frequency amplifier circuit 105H is the same as the output voltage of the low frequency amplifier circuit 105L.
  • the calibration circuit inputs a calibration signal (reference potential) to the low-frequency amplifier circuit 105L and the high-frequency amplifier circuit 105H, and the low-frequency amplifier circuit 105L and the high-frequency amplifier circuit 105H.
  • the bias of the high frequency amplifier circuit 105H is adjusted according to the output signal of the high frequency amplifier circuit 105H.
  • the high-frequency signal is affected by the parasitic element due to the layout of the receiving circuit as compared to the low-frequency signal, and the gm value changes immediately. Easy to deteriorate. For this reason, by providing the low-frequency amplifier circuit 105L and the high-frequency amplifier circuit 105H, the adjustment is easy to converge with little fluctuation in characteristics.
  • the plurality of amplifier circuits 105L and 105H have a large circuit area and are disadvantageous in terms of cost, an increase in power consumption can be suppressed by powering down the amplifier circuit 105L or 105H in the non-use band. .
  • the temperature of the substrate can be increased quickly in the LSI with the low power supply voltage, and the circuit state can be stabilized during characteristic adjustment. Can do.
  • Calibration is performed by using a calibration signal having a plurality of frequencies. It is possible to detect the gain of multiple points in the region, and the effect of improving the adjustment accuracy is obtained.
  • a broadband wireless communication device UWB communication device
  • a wideband RF analog circuit receiveriver circuit
  • UWB communication device 0.5 to several GHz
  • a wideband RF analog circuit receiveriver circuit

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Transceivers (AREA)
  • Amplifiers (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

L'invention porte sur un appareil de communication caractérisé en ce qu'il comprend une antenne (101) pour la réception d'un signal radio, un circuit amplificateur basse fréquence (105L) pour l'amplification d'un signal basse fréquence reçu par l'antenne et un circuit amplificateur haute fréquence (105H) pour l'amplification d'un signal haut fréquence reçu par l'antenne.
PCT/JP2006/303866 2006-03-01 2006-03-01 Appareil de communication WO2007099621A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/303866 WO2007099621A1 (fr) 2006-03-01 2006-03-01 Appareil de communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/303866 WO2007099621A1 (fr) 2006-03-01 2006-03-01 Appareil de communication

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Publication Number Publication Date
WO2007099621A1 true WO2007099621A1 (fr) 2007-09-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014147921A1 (fr) * 2013-03-18 2014-09-25 ソニー株式会社 Dispositif de réception et procédé de réception

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10170633A (ja) * 1996-12-13 1998-06-26 Nec Corp アクティブ・フェイズト・アレイ・レーダの位相校正装置
JPH11234055A (ja) * 1998-02-16 1999-08-27 Nippon Telegr & Teleph Corp <Ntt> 非線形増幅器
JP2001053527A (ja) * 1999-05-28 2001-02-23 Matsushita Electric Ind Co Ltd 通信装置及び通信方法
JP2001119251A (ja) * 1999-08-31 2001-04-27 Stmicroelectronics Sa 二重通過帯域増幅回路及び無線周波受信ヘッド

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10170633A (ja) * 1996-12-13 1998-06-26 Nec Corp アクティブ・フェイズト・アレイ・レーダの位相校正装置
JPH11234055A (ja) * 1998-02-16 1999-08-27 Nippon Telegr & Teleph Corp <Ntt> 非線形増幅器
JP2001053527A (ja) * 1999-05-28 2001-02-23 Matsushita Electric Ind Co Ltd 通信装置及び通信方法
JP2001119251A (ja) * 1999-08-31 2001-04-27 Stmicroelectronics Sa 二重通過帯域増幅回路及び無線周波受信ヘッド

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014147921A1 (fr) * 2013-03-18 2014-09-25 ソニー株式会社 Dispositif de réception et procédé de réception
JPWO2014147921A1 (ja) * 2013-03-18 2017-02-16 ソニーセミコンダクタソリューションズ株式会社 受信装置および受信方法
US9991916B2 (en) 2013-03-18 2018-06-05 Sony Semiconductor Solutions Corporation Receiving device and receiving method

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