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WO2007048387A3 - Halbleiterbauelement mit pn-übergang und verfahren zur herstellung desselben - Google Patents

Halbleiterbauelement mit pn-übergang und verfahren zur herstellung desselben Download PDF

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Publication number
WO2007048387A3
WO2007048387A3 PCT/DE2006/001848 DE2006001848W WO2007048387A3 WO 2007048387 A3 WO2007048387 A3 WO 2007048387A3 DE 2006001848 W DE2006001848 W DE 2006001848W WO 2007048387 A3 WO2007048387 A3 WO 2007048387A3
Authority
WO
WIPO (PCT)
Prior art keywords
junction
semiconductor component
production
conducting region
semiconductor
Prior art date
Application number
PCT/DE2006/001848
Other languages
English (en)
French (fr)
Other versions
WO2007048387A2 (de
Inventor
Anton Mauder
Frank Pfirsch
Hans-Joachim Schulze
Stefan Sedlmaier
Armin Willmeroth
Original Assignee
Infineon Technologies Austria
Anton Mauder
Frank Pfirsch
Hans-Joachim Schulze
Stefan Sedlmaier
Armin Willmeroth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Stefan Sedlmaier, Armin Willmeroth filed Critical Infineon Technologies Austria
Publication of WO2007048387A2 publication Critical patent/WO2007048387A2/de
Publication of WO2007048387A3 publication Critical patent/WO2007048387A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

Die Erfindung betrifft ein Halbleiterbauelement (1) und ein Verfahren zur Herstellung desselben. Das Halbleiterbauelement (3) weist einen Halbleiterkörper (4) auf. In dem Halbleiterkörper (4) ist ein PN-Übergang angeordnet, der ein p-leitendes Gebiet (11) und ein n-leitendes Gebiet (9) aufweist. Das p-leitende Gebiet (11) oder das n-leitende Gebiet (9) des PN-Übergangs weisen Bereiche (23) auf, welche den PN-Übergang innerhalb des Halbleiterkörpers (4) räumlich begrenzen.
PCT/DE2006/001848 2005-10-24 2006-10-19 Halbleiterbauelement mit pn-übergang und verfahren zur herstellung desselben WO2007048387A2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102005051180.5 2005-10-24
DE102005051180 2005-10-24
DE102006004627A DE102006004627B3 (de) 2005-10-24 2006-01-31 Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben
DE102006004627.7 2006-01-31

Publications (2)

Publication Number Publication Date
WO2007048387A2 WO2007048387A2 (de) 2007-05-03
WO2007048387A3 true WO2007048387A3 (de) 2007-09-27

Family

ID=37775138

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2006/001848 WO2007048387A2 (de) 2005-10-24 2006-10-19 Halbleiterbauelement mit pn-übergang und verfahren zur herstellung desselben

Country Status (2)

Country Link
DE (1) DE102006004627B3 (de)
WO (1) WO2007048387A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044414A1 (de) * 2007-09-17 2009-03-19 Infineon Technologies Austria Ag Halbleiterbauelement und Verfahren zur Herstellung desselben
US20090236680A1 (en) 2008-03-20 2009-09-24 Infineon Technologies Austria Ag Semiconductor device with a semiconductor body and method for its production
US7943449B2 (en) 2008-09-30 2011-05-17 Infineon Technologies Austria Ag Semiconductor component structure with vertical dielectric layers
US8183666B2 (en) * 2009-10-29 2012-05-22 Infineon Technologies Ag Semiconductor device including semiconductor zones and manufacturing method
US8866221B2 (en) 2012-07-02 2014-10-21 Infineon Technologies Austria Ag Super junction semiconductor device comprising a cell area and an edge area
CN114784132B (zh) * 2022-04-18 2023-06-27 杭州电子科技大学 一种碳化硅微沟槽中子探测器结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122222A1 (en) * 2001-12-27 2003-07-03 Hideki Okumura Semiconductor device having vertical metal insulator semiconductor transistor and method of manufacturing the same
US20050029222A1 (en) * 2001-09-27 2005-02-10 Xingbi Chen Method of manufacturing semiconductor device having composite buffer layer
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10340131B4 (de) * 2003-08-28 2005-12-01 Infineon Technologies Ag Halbleiterleistungsbauteil mit Ladungskompensationsstruktur und monolithisch integrierter Schaltung, sowie Verfahren zu dessen Herstellung

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050167742A1 (en) * 2001-01-30 2005-08-04 Fairchild Semiconductor Corp. Power semiconductor devices and methods of manufacture
US20050029222A1 (en) * 2001-09-27 2005-02-10 Xingbi Chen Method of manufacturing semiconductor device having composite buffer layer
US20030122222A1 (en) * 2001-12-27 2003-07-03 Hideki Okumura Semiconductor device having vertical metal insulator semiconductor transistor and method of manufacturing the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
OSTEN H J ET AL: "Carbon-containing group IV heterostructures on Si: properties and device applications", PREPARATION AND CHARACTERIZATION, ELSEVIER SEQUOIA, NL, vol. 321, no. 1-2, 26 May 1998 (1998-05-26), pages 11 - 14, XP004147886, ISSN: 0040-6090 *
SHAO L ET AL: "Boron diffusion in silicon: the anomalies and control by point defect engineering", MATERIALS SCIENCE AND ENGINEERING R: REPORTS, ELSEVIER SEQUOIA S.A., LAUSANNE, CH, vol. 42, no. 3-4, 1 November 2003 (2003-11-01), pages 65 - 114, XP004470026, ISSN: 0927-796X *

Also Published As

Publication number Publication date
WO2007048387A2 (de) 2007-05-03
DE102006004627B3 (de) 2007-04-12

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