WO2007010801A1 - Step-up/down switching regulator, its control circuit, and electronic apparatus using same - Google Patents
Step-up/down switching regulator, its control circuit, and electronic apparatus using same Download PDFInfo
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- WO2007010801A1 WO2007010801A1 PCT/JP2006/313881 JP2006313881W WO2007010801A1 WO 2007010801 A1 WO2007010801 A1 WO 2007010801A1 JP 2006313881 W JP2006313881 W JP 2006313881W WO 2007010801 A1 WO2007010801 A1 WO 2007010801A1
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- transistor
- terminal
- switching
- control circuit
- synchronous rectification
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- 230000001360 synchronised effect Effects 0.000 claims abstract description 65
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 230000007704 transition Effects 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims 2
- 230000005669 field effect Effects 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 abstract 1
- 230000003449 preventive effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000002265 prevention Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 229910001416 lithium ion Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- Step-up and step-down switching regulators their control circuits, and electronic equipment using them
- the present invention relates to a switching regulator, and more particularly to a synchronous rectification step-up or step-down switching regulator.
- batteries such as lithium ion batteries are mounted as power sources in such electronic devices.
- a DCZDC converter such as a switching regulator that boosts or lowers the battery voltage is used to supply the voltage output from the lithium-ion battery to devices operating at different power supply voltages.
- a step-up or step-down switching regulator includes a method using a rectifying diode (hereinafter referred to as a diode rectification method) and a method using a synchronous rectification transistor instead of a diode (hereinafter referred to as synchronous rectification).
- a diode is required in addition to the inductor and output capacitor outside the force control circuit, which has the advantage that high efficiency can be obtained when the load current flowing through the load is small, so that the circuit area increases.
- the efficiency when the current supplied to the load is small is inferior to the former.
- the synchronous rectification step-up switching regulator is supplied with a battery voltage or the like.
- a synchronous rectification transistor and an inductor are connected in series between the input terminal connected to the output terminal that outputs the boosted voltage (hereinafter referred to as output voltage).
- output voltage the boosted voltage
- Patent Document 1 Japanese Patent Application Laid-Open No. 2004-32875
- Patent Document 2 JP 2002-252971 A
- the present invention has been made in view of an energetic problem, and its comprehensive purpose is to perform synchronous rectification switching that can cut off the current that flows when the step-up / step-down operation is stopped without providing a DC prevention transistor. It is in the provision of the Regulator.
- One embodiment of the present invention relates to a control circuit for a synchronous rectification step-up switching regulator.
- This control circuit includes a first terminal to which an input voltage is supplied via an externally connected inductor, a second terminal to which an output capacitor is connected, a switching transistor provided between the first terminal and the ground, A synchronous rectification transistor provided between the first terminal and the second terminal; a back gate of the synchronous rectification transistor; a first transistor provided between the first terminal; a back gate of the synchronous rectification transistor; A second transistor provided between the two terminals; and a switch control unit that controls on / off of the first and second transistors.
- the first and second transistors are provided, and the on / off of the two transistors is controlled, whereby the synchronous rectification transistor The current flowing through the back gate can be controlled.
- a DC prevention transistor is not provided in series with the inductor, it is possible to prevent unnecessary current from flowing and preventing voltage from appearing at the output terminal when boosting is stopped.
- the switch control unit turns off the first transistor and the second transistor during the boost stop period of the boost switching regulator driven by the present control circuit, and turns off the first transistor during the boost operation period. Two transistors may be turned on.
- the current path through the back gate of the synchronous rectification transistor can be cut off. Further, during the boosting operation period, a current path can be generated via the back gate of the synchronous rectification transistor by turning on the second transistor.
- the switch control unit may gradually turn on the second transistor while the first transistor is turned on during the start-up period during which the step-up switching regulator enters the operation stop state force step-up operation state. .
- the synchronous rectification transistor can be prevented from being latched up.
- This control circuit includes a first terminal that outputs a switching voltage to an externally connected inductor, a second terminal that is supplied with an input voltage from the outside, and a switching transistor provided between the first terminal and the second terminal.
- a synchronous rectifying transistor provided between the first terminal and the ground, a first transistor provided between the back gate and the first terminal of the switching transistor, and provided between the back gate of the switching transistor and the second terminal.
- a switch controller for controlling on / off of the first and second transistors.
- the first and second transistors are provided, and the on / off of the two transistors is controlled, so that the switching transistor is connected via the back gate of the switching transistor.
- the current flowing through be able to.
- the switch control unit turns off the first transistor and the second transistor during the step-down stop period of the step-down switching regulator driven by the present control circuit, turns off the first transistor during the step-down operation period, Two transistors may be turned on.
- the current path through the knock gate of the switching transistor can be cut off. Also, during the step-down operation period, a current path through the back gate of the switching transistor can be generated by turning on the second transistor.
- the switch control unit may gradually turn on the second transistor while the first transistor is turned off during the start-up period in which the step-down switching regulator transitions from the operation stop state to the step-down operation state. .
- Yet another embodiment of the present invention relates to a switching regulator control circuit capable of switching between a step-up mode and a step-down mode.
- This control circuit functions as a switching transistor in the boost mode, functions as a synchronous rectification transistor in the step-down mode, and functions as a synchronous rectification transistor in the step-up mode.
- a second switching transistor that functions as a switching transistor, a first transistor provided between the back gate and drain of the second switching transistor, and a second transistor provided between the knock gate and source of the second switching transistor.
- a transistor and a switch control unit for controlling on / off of the first and second transistors.
- the switch control unit can appropriately switch the on / off states of the first and second transistors in the step-up mode and the step-down mode.
- the switching transistor, the synchronous rectification transistor, the first transistor, the second transistor, and the switch control unit may be integrated on a single semiconductor substrate.
- the integration here includes the case where all the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated as a single unit. Some resistors and capacitors are provided outside the semiconductor substrate.
- Another aspect of the present invention is a step-up switching regulator.
- This switching level The regulator includes the control circuit described above, one end connected to the first terminal of the control circuit, the other end to which the input voltage is applied, one end connected to the second terminal of the control circuit, and the other end grounded. And output a voltage at one end of the output capacitor.
- the switch control unit by appropriately controlling on / off of the first and second transistors by the switch control unit, the current flowing through the back gate of the synchronous rectification transistor can be controlled, and the boost is stopped. Sometimes, an input voltage appears at one end of the output capacitor or current can be prevented from flowing through the load.
- the switching regulator includes an output capacitor having one end grounded, an inductor having one end connected to the other end of the output capacitor, and the above-described control circuit that supplies a switching voltage to the other end of the inductor. The voltage at the other end of the output capacitor is output.
- the current flowing through the back gate of the switching transistor can be controlled by controlling on / off of the first and second transistors.
- Yet another embodiment of the present invention is an electronic device.
- This electronic device includes a battery and the above-described switching regulator that increases or decreases the voltage of the battery.
- inrush current at power-on can be suppressed by controlling the current flowing through the synchronous rectification transistor or the back gate of the switching transistor.
- loss due to resistance can be reduced, and the circuit area can be reduced.
- FIG. 1 is a circuit diagram showing a configuration of a step-up switching regulator according to a first embodiment.
- FIG. 2 is a time chart showing an operating state of the step-up switching regulator of FIG.
- FIG. 3 is a circuit diagram showing a configuration of a step-up switching regulator according to a second embodiment.
- FIG. 4 is a time chart showing an operating state of the step-down switching regulator of FIG. 3.
- FIG. 5 is a circuit diagram showing a configuration of a control circuit according to a third embodiment.
- FIG. 6 is a block diagram showing a configuration of an electronic device in which the control circuit of FIGS. 1, 3, and 5 is preferably used.
- control circuit 102 1st terminal, 104 2nd terminal, 106 voltage feedback terminal, 11 0 control circuit, 112 1st terminal, 114 2nd terminal, 116 voltage feedback terminal, 120 control circuit, 122 1st control circuit Terminal, 124 second terminal, 126 voltage feedback terminal, 128 voltage feedback terminal, 200 step-up switching regulator, 202 input terminal, 204 output terminal, 210 step-down switching regulator, 212 input terminal, 214 output terminal ,
- FIG. 1 is a circuit diagram showing a configuration of a step-up switching regulator 200 according to the first embodiment.
- the step-up switching regulator 200 is a synchronous rectification switching regulator including a control circuit 100, an inductor Ll, and an output capacitor Co.
- An input voltage Vin is applied to the input terminal 202.
- the step-up switching regulator 200 according to the present embodiment steps up the input voltage Vin at a predetermined step-up ratio and outputs the output voltage Vout from the output terminal 204.
- An inductor L1 is connected between the first terminal 102 of the control circuit 100 and the input terminal 202 of the step-up switching regulator 200.
- the input voltage Vin is supplied to the first terminal 102 via the inductor L1.
- An output capacitor Co is connected between the second terminal 104 and the ground.
- the control circuit 100 includes a switching transistor SW1, a synchronous rectification transistor SW2, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a pulse width modulator 14, on one semiconductor substrate. Are collected.
- the switching transistor SW1 is an N-channel MOSFET, the drain is connected to the first terminal 102, and the source is grounded.
- the synchronous rectification transistor SW2 is a P-channel MOSFET, and has a drain connected to the first terminal 102 and a source connected to the second terminal 104.
- the first gate control signal Vgl and the second gate control signal Vg2 output from the driver circuit 10 are input to the gates of the switching transistor SW1 and the synchronous rectification transistor SW2.
- the output voltage Vout of the step-up switching regulator 200 is fed back to the voltage feedback terminal 106 of the control circuit 100.
- the output voltage Vout fed back is input to the pulse width modulator 14.
- the pulse width modulator 14 generates a pulse width modulation signal (hereinafter referred to as a PWM signal Vpwm) in which the ratio between the high level and the low level time, that is, the duty ratio changes.
- the duty ratio of the PWM signal Vpwm is controlled so that the output voltage Vout approaches a predetermined reference voltage.
- the driver circuit 10 generates the first gate control signal Vgl and the second gate control signal Vg2 based on the PWM signal Vpwm output from the pulse width modulator 14, and the switching transistor SW1 and the Output to the gate of the rectifying transistor SW2.
- the switching transistor SW1 and the synchronous rectification transistor SW2 are alternately turned on and off based on the duty ratio of the PWM signal Vpwm.
- body diodes (parasitic diodes) Dl and D2 exist between the back gate and the drain of the synchronous rectification transistor SW2 or between the back gate and the source.
- the back gate of this P-channel MOSFET is used connected to the source, so that both ends of the second body diode D2 are used in a short-circuited state.
- the current flows from the input terminal 202 to the output terminal 204 via the first body diode D1 when the boosting is stopped.
- a first transistor Ml and a second transistor M2 are provided instead of connecting the back gate of the synchronous rectification transistor SW2 to the source.
- the first transistor Ml is a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW 1 and the first terminal 102. That is, the source of the first transistor Ml is connected to the first terminal 102, and the drain is connected to the back gate of the synchronous rectification transistor SW2.
- the second transistor M2 is also a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW1 and the second terminal 104. That is, the source of the second transistor M2 is connected to the back gate of the synchronous rectification transistor SW2, and the drain is connected to the second terminal 104.
- the switch control unit 12 generates the first control signal Vcntl and the second control signal Vcnt2 according to the operating state of the step-up switching regulator 200, and the gates of the first transistor Ml and the second transistor M2 Each voltage is controlled by controlling the voltage.
- the step-up switching regulator 200 is in a step-up stop state in which the step-up operation is stopped and power supply to the load is stopped, and a step-up operation state in which a predetermined output voltage Vout is supplied to the load by the step-up operation. And the start-up state corresponding to the transition period from the boost stop state to the boost operation state.
- FIG. 2 is a time chart showing the operating state of the step-up switching regulator 200.
- the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
- the step-up switching regulator 200 Prior to time TO, the step-up switching regulator 200 is in a step-up stop state. At this time, the switch control unit 12 sets the first control signal Vcntl and the second control signal Vcnt2 to high level. Then, both the first transistor Ml and the second transistor M2 are turned off. When both the first transistor M1 and the second transistor M2 are turned off, no current flows through the first body diode Dl and the second body diode D2 of the synchronous rectification transistor SW2. As a result, the current path via the back gate of the synchronous rectification transistor SW2 can be interrupted between the input terminal 202 and the output terminal 204, current flows through the load, or the output terminal 204 is close to the input voltage Vin. The voltage can be prevented from appearing. Before time TO, the potential Vbg of the back gate of the synchronous rectification transistor SW2 becomes high! /.
- a standby signal STB (not shown in FIG. 1) changes from a low level to a high level, and activation of the step-up switching regulator 200 is instructed.
- the switch control unit 12 sets the first control signal Vcntl to low level and turns on the first transistor Ml. Further, the switch control unit 12 gradually decreases the second control signal Vcnt2 from the high level to the low level. Thereafter, when the second control signal Vcnt2 decreases and the gate-source voltage of the second transistor M2 becomes higher than the threshold voltage V, the second transistor M2 is turned on. As the second transistor M2 is gradually turned on, the output voltage Vout appearing at the second terminal 104 rises to near the input voltage Vin applied to the input terminal 202.
- the step-up switching regulator 200 can suppress the occurrence of the inrush current by gradually turning on the second transistor M2 at the time of startup. Monkey.
- the switch control unit 12 sets the first control signal Vcntl to high level and turns off the first transistor Ml. Thereafter, at time T3, the switching operation of the switching transistor SW1 and the synchronous rectification transistor SW2 is started by the pulse width modulator 14 and the driver circuit 10. When the boost operation is started at time T3, the output voltage Vout rises to a predetermined reference voltage.
- the first transistor Ml is turned off and the second transistor M2 is turned on during the step-up operation. Since this is a circuit state similar to the state in which the back gate of the P-channel MOSFET is connected to the source, the boosting operation can be suitably performed. In addition, starting at time TO and the force By starting the boosting operation at time T3 after the lapse of the period, the back gate voltage Vbg of the switching transistor SW1 decreases! /, While the switching transistor SW1 is turned on and latch-up occurs. Can be prevented.
- the second embodiment relates to a synchronous rectification step-down switching regulator 210.
- FIG. 3 is a circuit diagram showing a configuration of the step-down switching regulator 210 according to the second embodiment.
- the step-down switching regulator 210 is a synchronous rectification switching regulator including a control circuit 110, an inductor Ll, and an output capacitor Co.
- An input voltage Vin is applied to the input terminal 212.
- the step-down switching regulator 210 steps down the input voltage Vin and outputs the output voltage Vout from the output terminal 214.
- An inductor L1 is connected between the first terminal 112 of the control circuit 110 and the output terminal 214 of the step-down switching regulator 210.
- An output capacitor Co is connected between the output terminal 214 and the ground.
- the first terminal 112 outputs the switching voltage Vsw to the inductor L 1 connected to the outside.
- An input voltage Vin is supplied to the second terminal 114 from the outside.
- the control circuit 110 includes a switching transistor SW3, a synchronous rectification transistor SW4, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a pulse width modulator 14.
- the synchronous rectification transistor SW4 is an N-channel MOSFET, and has a drain connected to the first terminal 112 and a source grounded.
- the switching transistor SW3 is a P-channel MOSFET, and has a drain connected to the first terminal 112 and a source connected to the second terminal 114.
- the first gate control signal Vg3 and the second gate control signal Vg4 output from the driver circuit 10 are input to the gates of the switching transistor SW3 and the synchronous rectification transistor SW4.
- the output voltage Vout of the step-down switching regulator 210 is fed back to the voltage feedback terminal 116 of the control circuit 110.
- the feedback output voltage Vout is the pulse width modulator 14 Is input.
- the pulse width modulator 14 and the driver circuit 10 drive the switching transistor SW3 and the synchronous rectification transistor SW4 based on the feedback output voltage Vout.
- a first transistor Ml and a second transistor M2 are provided.
- the first transistor Ml is a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW 3 and the first terminal 112. That is, the source of the first transistor Ml is connected to the first terminal 112, and the drain is connected to the back gate of the switching transistor SW3.
- the second transistor M2 is also a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW3 and the second terminal 114. That is, the source of the second transistor M2 is connected to the back gate of the switching transistor SW3, and the drain is connected to the second terminal 114.
- the switch control unit 12 generates the first control signal Vcntl and the second control signal Vcnt2 according to the operating state of the step-down switching regulator 210, and the gates of the first transistor Ml and the second transistor M2 Each voltage is controlled by controlling the voltage.
- the step-down switching regulator 210 is a step-down stop state in which the step-down operation is stopped to stop power supply to the load, and a step-down operation state in which a predetermined output voltage Vout is supplied to the load by the step-down operation. , And the start-up state corresponding to the transition period from the step-down stop state to the step-down operation state.
- FIG. 4 is a time chart showing the operating state of the step-down switching regulator 210.
- the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
- the step-down switching regulator 210 Prior to time TO, the step-down switching regulator 210 is in a step-down stop state. At this time, the switch control unit 12 sets the first control signal Vcntl and the second control signal Vcnt2 to high level to turn off both the first transistor Ml and the second transistor M2. 1st transistor M When both the first and second transistors M2 are turned off, no current flows through the first body diode Dl and the second body diode D2 of the switching transistor SW3. Before the time TO, the potential Vbg of the back gate of the synchronous rectification transistor SW2 is high.
- a standby signal STB (not shown in FIG. 3) changes from a low level to a high level, and the start of the step-down operation of step-down switching regulator 210 is instructed.
- the switch control unit 12 gradually decreases the second control signal Vcnt2 from high level to low level while maintaining the first control signal Vcntl at the neutral level.
- the back gate voltage Vbg of the switching transistor SW3 is maintained at a high level.
- the step-down switching regulator 210 causes the input voltage Vin to appear in the switching voltage Vsw by turning off the first transistor Ml at the time of startup. Can be prevented.
- the first transistor Ml is off and the second transistor M2 is on during the step-down operation. Since this is a circuit state similar to the state in which the back gate of the P-channel MOSFET is connected to the source, the step-down operation can be suitably performed.
- control circuit 100 shown in FIG. 1 and the control circuit 110 shown in FIG. 3 have the same circuit configuration, and the arrangement of the external inductor Ll, output capacitor Co, input voltage Vin, and output voltage Vout appear. The position is different. Therefore, in the third embodiment, the control circuit 100 in FIG. 1 and the control circuit 110 in FIG. 3 are used as a control circuit for a switching regulator capable of switching between a step-up type and a step-down type.
- FIG. 5 is a circuit diagram showing a configuration of the control circuit 120 according to the third embodiment.
- control The circuit 120 includes a first switching transistor SW5, a second switching transistor SW6, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a noise width modulator 14.
- the first switching transistor SW5 functions as a switching transistor in the step-up mode, and functions as a synchronous rectification transistor in the step-down mode.
- the second switching transistor SW6 functions as a synchronous rectification transistor in the step-up mode, and functions as a switching transistor in the step-down mode.
- the first transistor Ml and the second transistor M2 are both P-channel MOS FETs.
- the output voltage is fed back to the voltage feedback terminal 126.
- the first terminal 122 corresponds to the first terminal 102 in FIG. 1 or the first terminal 112 in FIG. 3
- the second terminal 124 corresponds to the second terminal 104 in FIG. 1 or the second terminal 114 in FIG.
- the first transistor Ml is provided between the back gate and the drain of the second switching transistor SW6.
- the second transistor M2 is provided between the back gate and the source of the second switching transistor.
- a mode instruction signal MODE for designating the step-up mode or the step-down mode is input to the mode terminal 128.
- the mode instruction signal MODE is input to the switch control unit 12.
- the switch control unit 12 determines whether to operate in the step-up mode or the step-down mode based on the mode instruction signal MODE, and controls on / off of the first transistor Ml and the second transistor M2 based on the determination result. .
- the switch control unit 12 controls the first transistor Ml and the second transistor M2 by the method described in the first embodiment in the step-up mode, and the second embodiment in the step-down mode.
- the first transistor Ml and the second transistor M2 are controlled by the method described in the embodiment.
- the control circuit 120 configured as described above, even when the user uses the control circuit as either a step-up switching regulator or a step-down switching regulator, the first transistor Ml, The second transistor M2 can be controlled.
- FIG. 6 is a block diagram showing a configuration of an electronic device 300 in which the control circuits 100, 110, 120 of FIGS. 1, 3, and 5 are preferably used.
- the electronic device 300 is, for example, a digital still camera or a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360.
- the battery 310 is, for example, a lithium ion battery, and outputs about 3 to 4 V as the battery voltage Vbat.
- the microcomputer 350 is a block that comprehensively controls the entire electronic device 300, and operates at a power supply voltage of 1.5V.
- 1 ⁇ : 0360 includes 1 ⁇ 83 (1 ⁇ : 0) (31 ⁇ Emitting Diode) of 13 ⁇ 4 ⁇ , and is used as a liquid crystal knock light or lighting. A drive voltage of 4V or more is required for driving. .
- the power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel.
- the analog circuit 330, the digital circuit Supply appropriate power supply voltage to 340, microcomputer 350, and LED360.
- the control circuit 120 of FIG. 5 can be suitably used for such a power supply device 320 by arranging a plurality of control circuits 120 in parallel to constitute a multi-channel control circuit. That is, when a 4-channel control circuit is configured, the third channel CH3 that supplies the power supply voltage to the microcomputer 350 is operated in the step-down mode, and the fourth channel CH4 that supplies the power supply voltage to the LED 360 is in the step-up mode. Just make it work!
- control circuit 100 or the like is integrated in one LSI.
- the present invention is not limited to this, and some components are discretely provided outside the LSI. It may be provided as a chip element or chip component, or may be composed of multiple LSIs.
- the setting of the logic values of the high level and the low level is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.
- the control circuit of the switching regulator according to the present invention can be used for a power supply device.
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Abstract
A switching regulator of synchronous rectifying type capable of blocking the current flowing when voltage step-up/down operation is stopped without providing any DC current preventive transistor. An input voltage Vin is supplied to a first terminal (102) of a control circuit (100) through an inductor (L1) connected to the outside. An output capacitor (Co) is connected to a second terminal (104). A switching transistor (SW1) is disposed between the first terminal (102) and the ground, and a synchronous rectifying transistor (SW2) is disposed between the first and second terminals (102, 104). A first transistor (M1) is disposed between the back gate of a synchronous rectifying transistor (M2) and the first terminal (102), and the second transistor (M2) is disposed between the back gate and the second terminal (104). A switching control section (12) keeps the first and second transistors (M1, M2) off during a step-up stop period and keeps the first transistor (M1) off and the second transistor (M2) on during a step-up period.
Description
明 細 書 Specification
昇圧型、降圧型スイッチングレギユレータおよびその制御回路ならびにそ れを用いた電子機器 Step-up and step-down switching regulators, their control circuits, and electronic equipment using them
技術分野 Technical field
[0001] 本発明は、スイッチングレギユレータに関し、特に同期整流方式の昇圧型または降 圧型スイッチングレギユレータに関する。 TECHNICAL FIELD [0001] The present invention relates to a switching regulator, and more particularly to a synchronous rectification step-up or step-down switching regulator.
背景技術 Background art
[0002] 近年の携帯電話、 PDA (Personal Digital Assistant)、ノート型パーソナルコ ンピュータなどのさまざまな電子機器は、液晶のノ ックライトとして設けられた発光ダ ィオード(以下、 LEDという)やマイクロプロセッサ、あるいはその他のアナログ、デジ タル回路などの異なる電源電圧で動作する多くのデバイスが搭載されている。 [0002] In recent years, various electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook personal computers have a light emitting diode (hereinafter referred to as an LED), a microprocessor, or a microprocessor, Many other devices that operate with different power supply voltages such as analog and digital circuits are installed.
[0003] 一方で、こうした電子機器にはリチウムイオン電池などの電池が電源として搭載され る。リチウムイオン電池から出力される電圧を、異なる電源電圧で動作するデバイス に供給するために、電池電圧を昇圧または降圧するスイッチングレギユレータなどの DCZDCコンバータが用いられる。 On the other hand, batteries such as lithium ion batteries are mounted as power sources in such electronic devices. A DCZDC converter such as a switching regulator that boosts or lowers the battery voltage is used to supply the voltage output from the lithium-ion battery to devices operating at different power supply voltages.
[0004] 昇圧型あるいは降圧型のスイッチングレギユレータは、整流用のダイオードを用いる 方式 (以下、ダイオード整流方式という)と、ダイオードの代わりに、同期整流用トラン ジスタを用いる方式 (以下、同期整流方式という)が存在する。前者の場合、負荷に 流れる負荷電流が小さいときに高効率が得られるという利点を有する力 制御回路の 外部に、インダクタ、出力キャパシタに加えてダイオードが必要となるため、回路面積 が大きくなる。後者の場合、負荷に供給する電流が小さいときの効率は、前者に比べ て劣るが、ダイオードの代わりにトランジスタを用いるため、 LSIの内部に集積化する ことができ、周辺部品を含めた回路面積としては小型化が可能となる。携帯電話など 小型化が要求される電子機器においては、整流用トランジスタを用いたスイッチング レギユレータ(以下、同期整流方式スイッチングレギユレータと 、う)が用いられること が多い。 [0004] A step-up or step-down switching regulator includes a method using a rectifying diode (hereinafter referred to as a diode rectification method) and a method using a synchronous rectification transistor instead of a diode (hereinafter referred to as synchronous rectification). Method). In the former case, a diode is required in addition to the inductor and output capacitor outside the force control circuit, which has the advantage that high efficiency can be obtained when the load current flowing through the load is small, so that the circuit area increases. In the latter case, the efficiency when the current supplied to the load is small is inferior to the former. However, since a transistor is used instead of a diode, it can be integrated inside the LSI, and the circuit area including peripheral components As a result, downsizing is possible. In electronic devices that require miniaturization such as cellular phones, switching regulators using rectifying transistors (hereinafter referred to as synchronous rectification switching regulators) are often used.
[0005] ここで同期整流方式の昇圧型スイッチングレギユレータは、電池電圧などが入力さ
れる入力端子から、昇圧後の電圧 (以下、出力電圧という)を出力する出力端子との 間に、同期整流用トランジスタおよびインダクタが直列に接続される経路を有する。同 期整流用トランジスタに Pチャンネル MOSFETを用い、かつそのバックゲートをソー ス (またはドレイン)と接続した場合には、同期整流用トランジスタをオフして昇圧動作 を停止した状態においても、ノ ックゲートとドレイン (またはソース)間のボディダイォ ード(寄生ダイオード)およびインダクタを介して負荷に電流が流れてしまうという問題 かあつた。 [0005] Here, the synchronous rectification step-up switching regulator is supplied with a battery voltage or the like. A synchronous rectification transistor and an inductor are connected in series between the input terminal connected to the output terminal that outputs the boosted voltage (hereinafter referred to as output voltage). When a P-channel MOSFET is used for the synchronous rectification transistor and its back gate is connected to the source (or drain), even when the boost operation is stopped by turning off the synchronous rectification transistor, The problem was that current would flow to the load via the body diode (parasitic diode) between the drain (or source) and the inductor.
[0006] 特許文献 1 :特開 2004— 32875号公報 [0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-32875
特許文献 2 :特開 2002— 252971号公報 Patent Document 2: JP 2002-252971 A
発明の開示 Disclosure of the invention
発明が解決しょうとする課題 Problems to be solved by the invention
[0007] 昇圧動作停止時に同期整流用トランジスタおよびインダクタを介して負荷に流れる 電流を遮断するために、この電流経路上にスィッチ素子として直流防止用トランジス タを設ける方法が考えられる。しかしながら、この直流防止用トランジスタは、昇圧動 作時には抵抗素子として働くため電力損失をもたらしてしまう。この直流防止用トラン ジスタによる電力損失を低減するためには、トランジスタサイズを大きくしてオン抵抗 を低減する必要があるが、これは回路面積の増大を招くという問題がある。 In order to cut off the current flowing to the load via the synchronous rectification transistor and the inductor when the boosting operation is stopped, a method of providing a DC prevention transistor as a switch element on the current path is conceivable. However, this DC prevention transistor acts as a resistance element during the boosting operation, resulting in power loss. In order to reduce the power loss due to the DC prevention transistor, it is necessary to increase the transistor size and reduce the on-resistance. However, this causes a problem that the circuit area increases.
[0008] 本発明は力かる課題に鑑みてなされたものであり、その包括的な目的は、直流防止 用トランジスタを設けずに昇降圧動作の停止時に流れる電流を遮断可能な同期整流 方式のスイッチングレギユレータの提供にある。 [0008] The present invention has been made in view of an energetic problem, and its comprehensive purpose is to perform synchronous rectification switching that can cut off the current that flows when the step-up / step-down operation is stopped without providing a DC prevention transistor. It is in the provision of the Regulator.
課題を解決するための手段 Means for solving the problem
[0009] 本発明のある態様は、同期整流方式の昇圧型スイッチングレギユレータの制御回 路に関する。この制御回路は、外部に接続されるインダクタを介して入力電圧が供給 される第 1端子と、出力キャパシタが接続される第 2端子と、第 1端子と接地間に設け られたスイッチングトランジスタと、第 1端子と第 2端子間に設けられた同期整流用トラ ンジスタと、同期整流用トランジスタのバックゲートと第 1端子間に設けられた第 1トラ ンジスタと、同期整流用トランジスタのバックゲートと第 2端子間に設けられた第 2トラ ンジスタと、第 1、第 2トランジスタのオンオフを制御するスィッチ制御部と、を備える。
[0010] この態様によると、同期整流用トランジスタのバックゲートをソースあるいはドレインと 接続する代わりに、第 1、第 2トランジスタを設け、 2つのトランジスタのオンオフを制御 することにより、同期整流用トランジスタのバックゲートを介して流れる電流を制御する ことができる。その結果、インダクタと直列に直流防止用トランジスタを設けなくても、 昇圧停止時において不要な電流が流れ、出力端子に電圧が現れるのを防止するこ とがでさる。 [0009] One embodiment of the present invention relates to a control circuit for a synchronous rectification step-up switching regulator. This control circuit includes a first terminal to which an input voltage is supplied via an externally connected inductor, a second terminal to which an output capacitor is connected, a switching transistor provided between the first terminal and the ground, A synchronous rectification transistor provided between the first terminal and the second terminal; a back gate of the synchronous rectification transistor; a first transistor provided between the first terminal; a back gate of the synchronous rectification transistor; A second transistor provided between the two terminals; and a switch control unit that controls on / off of the first and second transistors. [0010] According to this aspect, instead of connecting the back gate of the synchronous rectification transistor to the source or the drain, the first and second transistors are provided, and the on / off of the two transistors is controlled, whereby the synchronous rectification transistor The current flowing through the back gate can be controlled. As a result, even if a DC prevention transistor is not provided in series with the inductor, it is possible to prevent unnecessary current from flowing and preventing voltage from appearing at the output terminal when boosting is stopped.
[0011] スィッチ制御部は、本制御回路により駆動される昇圧型スイッチングレギユレータの 昇圧停止期間において、第 1トランジスタおよび第 2トランジスタをオフし、昇圧動作 期間において第 1トランジスタをオフし、第 2トランジスタをオンしてもよい。 The switch control unit turns off the first transistor and the second transistor during the boost stop period of the boost switching regulator driven by the present control circuit, and turns off the first transistor during the boost operation period. Two transistors may be turned on.
昇圧停止期間において、第 1トランジスタ、第 2トランジスタをともにオフすることによ り、同期整流用トランジスタのバックゲートを介しての電流経路を遮断することができ る。また、昇圧動作期間には、第 2トランジスタをオンすることにより、同期整流用トラン ジスタのバックゲートを介した電流経路を生成することができる。 By turning off both the first transistor and the second transistor during the boost stop period, the current path through the back gate of the synchronous rectification transistor can be cut off. Further, during the boosting operation period, a current path can be generated via the back gate of the synchronous rectification transistor by turning on the second transistor.
[0012] スィッチ制御部は、昇圧型スイッチングレギユレータの動作停止状態力 昇圧動作 状態に遷移する起動期間に、第 1トランジスタをオンした状態で、第 2トランジスタを徐 々にオンしてもよい。 [0012] The switch control unit may gradually turn on the second transistor while the first transistor is turned on during the start-up period during which the step-up switching regulator enters the operation stop state force step-up operation state. .
この場合、同期整流用トランジスタがラッチアップするのを防止することができる。 In this case, the synchronous rectification transistor can be prevented from being latched up.
[0013] 本発明の別の態様は、同期整流方式の降圧型スイッチングレギユレータの制御回 路に関する。この制御回路は、外部に接続されるインダクタにスイッチング電圧を出 力する第 1端子と、外部から入力電圧が供給される第 2端子と、第 1端子と第 2端子間 に設けられたスイッチングトランジスタと、第 1端子と接地間に設けられた同期整流用 トランジスタと、スイッチングトランジスタのバックゲートと第 1端子間に設けられた第 1ト ランジスタと、スイッチングトランジスタのバックゲートと第 2端子間に設けられた第 2ト ランジスタと、第 1、第 2トランジスタのオンオフを制御するスィッチ制御部と、を備える Another aspect of the present invention relates to a control circuit for a synchronous rectification step-down switching regulator. This control circuit includes a first terminal that outputs a switching voltage to an externally connected inductor, a second terminal that is supplied with an input voltage from the outside, and a switching transistor provided between the first terminal and the second terminal. A synchronous rectifying transistor provided between the first terminal and the ground, a first transistor provided between the back gate and the first terminal of the switching transistor, and provided between the back gate of the switching transistor and the second terminal. And a switch controller for controlling on / off of the first and second transistors.
[0014] この態様によると、スイッチングトランジスタのバックゲートをドレインあるいはソースと 接続する代わりに、第 1、第 2トランジスタを設け、 2つのトランジスタのオンオフを制御 することにより、スイッチングトランジスタのバックゲートを介して流れる電流を制御する
ことができる。 [0014] According to this aspect, instead of connecting the back gate of the switching transistor to the drain or the source, the first and second transistors are provided, and the on / off of the two transistors is controlled, so that the switching transistor is connected via the back gate of the switching transistor. The current flowing through be able to.
[0015] スィッチ制御部は、本制御回路により駆動される降圧型スイッチングレギユレータの 降圧停止期間において、第 1トランジスタおよび第 2トランジスタをオフし、降圧動作 期間において第 1トランジスタをオフし、第 2トランジスタをオンしてもよい。 The switch control unit turns off the first transistor and the second transistor during the step-down stop period of the step-down switching regulator driven by the present control circuit, turns off the first transistor during the step-down operation period, Two transistors may be turned on.
降圧停止期間において、第 1トランジスタ、第 2トランジスタをともにオフすることによ り、スイッチングトランジスタのノックゲートを介しての電流経路を遮断することができ る。また、降圧動作期間には、第 2トランジスタをオンすることにより、スイッチングトラ ンジスタのバックゲートを介した電流経路を生成することができる。 By turning off both the first transistor and the second transistor during the step-down stop period, the current path through the knock gate of the switching transistor can be cut off. Also, during the step-down operation period, a current path through the back gate of the switching transistor can be generated by turning on the second transistor.
[0016] スィッチ制御部は、降圧型スイッチングレギユレータの動作停止状態から降圧動作 状態に遷移する起動期間に、第 1トランジスタをオフした状態で、第 2トランジスタを徐 々にオンしてもよい。 [0016] The switch control unit may gradually turn on the second transistor while the first transistor is turned off during the start-up period in which the step-down switching regulator transitions from the operation stop state to the step-down operation state. .
[0017] 本発明のさらに別の態様は、昇圧モードまたは降圧モードを切り替え可能なスイツ チングレギユレータの制御回路に関する。この制御回路は、昇圧モード時においてス イッチングトランジスタとして機能し、降圧モード時において同期整流用トランジスタと して機能する第 1スイッチングトランジスタと、昇圧モード時において同期整流用トラン ジスタとして機能し、降圧モード時にぉ 、てスイッチングトランジスタとして機能する第 2スイッチングトランジスタと、第 2スイッチングトランジスタのバックゲートとドレイン間に 設けられた第 1トランジスタと、第 2スイッチングトランジスタのノ ックゲートとソース間に 設けられた第 2トランジスタと、第 1、第 2トランジスタのオンオフを制御するスィッチ制 御部と、を備える。 [0017] Yet another embodiment of the present invention relates to a switching regulator control circuit capable of switching between a step-up mode and a step-down mode. This control circuit functions as a switching transistor in the boost mode, functions as a synchronous rectification transistor in the step-down mode, and functions as a synchronous rectification transistor in the step-up mode. Sometimes a second switching transistor that functions as a switching transistor, a first transistor provided between the back gate and drain of the second switching transistor, and a second transistor provided between the knock gate and source of the second switching transistor. A transistor and a switch control unit for controlling on / off of the first and second transistors.
[0018] この態様によれば、スィッチ制御部により、昇圧モード、降圧モードで第 1、第 2トラ ンジスタのオン、オフの状態を適切に切り替えることができる。 [0018] According to this aspect, the switch control unit can appropriately switch the on / off states of the first and second transistors in the step-up mode and the step-down mode.
[0019] スイッチングトランジスタ、同期整流用トランジスタ、第 1トランジスタ、第 2トランジスタ ならびにスィッチ制御部は、 1つの半導体基板上に一体集積ィ匕されてもよい。なお、 ここでの集積化とは、回路の構成要素のすべてが半導体基板上に形成される場合や 、回路の主要構成要素が一体集積化される場合が含まれ、回路定数の調節用に一 部の抵抗やキャパシタなどが半導体基板の外部に設けられて 、てもよ 、。 [0019] The switching transistor, the synchronous rectification transistor, the first transistor, the second transistor, and the switch control unit may be integrated on a single semiconductor substrate. The integration here includes the case where all the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated as a single unit. Some resistors and capacitors are provided outside the semiconductor substrate.
[0020] 本発明の別の態様は、昇圧型スイッチングレギユレータである。このスイッチングレ
ギュレータは、上述の制御回路と、一端が制御回路の第 1端子に接続され、他端に 入力電圧が印加されるインダクタと、一端が制御回路の第 2端子に接続され、他端が 接地された出力キャパシタと、を備え、出力キャパシタの一端の電圧を出力する。 [0020] Another aspect of the present invention is a step-up switching regulator. This switching level The regulator includes the control circuit described above, one end connected to the first terminal of the control circuit, the other end to which the input voltage is applied, one end connected to the second terminal of the control circuit, and the other end grounded. And output a voltage at one end of the output capacitor.
[0021] この態様によると、スィッチ制御部により第 1、第 2トランジスタのオンオフを適切に制 御することにより、同期整流用トランジスタのバックゲートを介して流れる電流を制御 することができ、昇圧停止時において、出力キャパシタの一端に入力電圧が現れ、あ るいは負荷に電流が流れるのを防止することができる。 [0021] According to this aspect, by appropriately controlling on / off of the first and second transistors by the switch control unit, the current flowing through the back gate of the synchronous rectification transistor can be controlled, and the boost is stopped. Sometimes, an input voltage appears at one end of the output capacitor or current can be prevented from flowing through the load.
[0022] 本発明の別の態様は、降圧型スイッチングレギユレータである。このスイッチングレ ギュレータは、一端が接地された出力キャパシタと、出力キャパシタの他端にその一 端が接続されたインダクタと、インダクタの他端にスイッチング電圧を供給する上述の 制御回路と、を備え、出力キャパシタの他端の電圧を出力する。 [0022] Another aspect of the present invention is a step-down switching regulator. The switching regulator includes an output capacitor having one end grounded, an inductor having one end connected to the other end of the output capacitor, and the above-described control circuit that supplies a switching voltage to the other end of the inductor. The voltage at the other end of the output capacitor is output.
[0023] この態様によると、第 1、第 2トランジスタのオンオフを制御することにより、スィッチン グトランジスタのバックゲートを介して流れる電流を制御することができる。 According to this aspect, the current flowing through the back gate of the switching transistor can be controlled by controlling on / off of the first and second transistors.
[0024] 本発明のさらに別の態様は、電子機器である。この電子機器は、電池と、電池の電 圧を昇圧もしくは降圧する上述のスイッチングレギユレータと、を備える。 [0024] Yet another embodiment of the present invention is an electronic device. This electronic device includes a battery and the above-described switching regulator that increases or decreases the voltage of the battery.
この態様〖こよれば、同期整流用トランジスタあるいはスイッチングトランジスタのバッ クゲートを介して流れる電流を制御することにより、電源投入時の突入電流を抑制す ることができる。また、直流防止用トランジスタを設ける必要がないため、抵抗による損 失を低減することができ、回路面積を削減することができる。 According to this embodiment, inrush current at power-on can be suppressed by controlling the current flowing through the synchronous rectification transistor or the back gate of the switching transistor. In addition, since there is no need to provide a DC prevention transistor, loss due to resistance can be reduced, and the circuit area can be reduced.
[0025] なお、以上の構成要素の任意の組合せや本発明の構成要素や表現を、方法、装 置、システムなどの間で相互に置換したものもまた、本発明の態様として有効である。 図面の簡単な説明 [0025] It should be noted that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention that are mutually replaced between methods, devices, systems, etc. are also effective as an aspect of the present invention. Brief Description of Drawings
[0026] [図 1]第 1の実施の形態に係る昇圧型スイッチングレギユレータの構成を示す回路図 である。 FIG. 1 is a circuit diagram showing a configuration of a step-up switching regulator according to a first embodiment.
[図 2]図 1の昇圧型スイッチングレギユレータの動作状態を示すタイムチャートである。 2 is a time chart showing an operating state of the step-up switching regulator of FIG.
[図 3]第 2の実施の形態に係る昇圧型スイッチングレギユレータの構成を示す回路図 である。 FIG. 3 is a circuit diagram showing a configuration of a step-up switching regulator according to a second embodiment.
[図 4]図 3の降圧型スイッチングレギユレータの動作状態を示すタイムチャートである。
[図 5]第 3の実施の形態に係る制御回路の構成を示す回路図である。 4 is a time chart showing an operating state of the step-down switching regulator of FIG. 3. FIG. 5 is a circuit diagram showing a configuration of a control circuit according to a third embodiment.
[図 6]図 1、図 3、図 5の制御回路が好適に使用される電子機器の構成を示すブロック 図である。 FIG. 6 is a block diagram showing a configuration of an electronic device in which the control circuit of FIGS. 1, 3, and 5 is preferably used.
符号の説明 Explanation of symbols
[0027] 100 制御回路、 102 第 1端子、 104 第 2端子、 106 電圧帰還端子、 11 0 制御回路、 112 第 1端子、 114 第 2端子、 116 電圧帰還端子、 120 制 御回路、 122 第 1端子、 124 第 2端子、 126 電圧帰還端子、 128 電圧帰 還端子、 200 昇圧型スイッチングレギユレータ、 202 入力端子、 204 出力端 子、 210 降圧型スイッチングレギユレータ、 212 入力端子、 214 出力端子、 [0027] 100 control circuit, 102 1st terminal, 104 2nd terminal, 106 voltage feedback terminal, 11 0 control circuit, 112 1st terminal, 114 2nd terminal, 116 voltage feedback terminal, 120 control circuit, 122 1st control circuit Terminal, 124 second terminal, 126 voltage feedback terminal, 128 voltage feedback terminal, 200 step-up switching regulator, 202 input terminal, 204 output terminal, 210 step-down switching regulator, 212 input terminal, 214 output terminal ,
SW1 スイッチングトランジスタ、 SW2 同期整流用トランジスタ、 SW3 スィッチ ングトランジスタ、 SW4 同期整流用トランジスタ、 SW5 第 1スイッチングトランジ スタ、 SW6 第 2スイッチングトランジスタ、 Ml 第 1トランジスタ、 M2 第 2トラン ジスタ、 10 ドライバ回路、 12 スィッチ制御部、 14 パルス幅変調器、 L1 ィ ンダクタ、 Co 出力キャパシタ、 Vgl 第 1ゲート制御信号、 Vg2 第 2ゲート制 御信号、 D1 第 1ボディダイオード、 D2 第 2ボディダイオード、 Vcntl 第 1制 御信号、 Vcnt2 第 2制御信号。 SW1 switching transistor, SW2 synchronous rectification transistor, SW3 switching transistor, SW4 synchronous rectification transistor, SW5 first switching transistor, SW6 second switching transistor, Ml first transistor, M2 second transistor, 10 driver circuit, 12 Switch control unit, 14 pulse width modulator, L1 inductor, Co output capacitor, Vgl first gate control signal, Vg2 second gate control signal, D1 first body diode, D2 second body diode, Vcntl first control Signal, Vcnt2 Second control signal.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0028] 以下、本発明を好適な実施の形態をもとに図面を参照しながら説明する。各図面に 示される同一または同等の構成要素、部材、処理には、同一の符号を付するものとし 、適宜重複した説明は省略する。また、実施の形態は、発明を限定するものではなく 例示であって、実施の形態に記述されるすべての特徴やその組み合わせは、必ずし も発明の本質的なものであるとは限らない。 Hereinafter, the present invention will be described based on a preferred embodiment with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations described in the embodiments are not necessarily essential to the invention.
[0029] (第 1の実施の形態) [0029] (First embodiment)
本発明の第 1の実施の形態は、同期整流方式の昇圧型スイッチングレギユレータに 関する。図 1は、第 1の実施の形態に係る昇圧型スイッチングレギユレータ 200の構 成を示す回路図である。昇圧型スイッチングレギユレータ 200は、制御回路 100、ィ ンダクタ Ll、出力キャパシタ Coを含む同期整流方式のスイッチングレギユレータであ る。
[0030] 入力端子 202には入力電圧 Vinが印加されている。本実施の形態に係る昇圧型ス イツチングレギユレータ 200は、入力電圧 Vinを所定の昇圧率で昇圧し、出力端子 20 4から出力電圧 Voutを出力する。 The first embodiment of the present invention relates to a synchronous rectification step-up switching regulator. FIG. 1 is a circuit diagram showing a configuration of a step-up switching regulator 200 according to the first embodiment. The step-up switching regulator 200 is a synchronous rectification switching regulator including a control circuit 100, an inductor Ll, and an output capacitor Co. An input voltage Vin is applied to the input terminal 202. The step-up switching regulator 200 according to the present embodiment steps up the input voltage Vin at a predetermined step-up ratio and outputs the output voltage Vout from the output terminal 204.
制御回路 100の第 1端子 102と、昇圧型スイッチングレギユレータ 200の入力端子 2 02間にはインダクタ L1が接続される。第 1端子 102には、インダクタ L1を介して入力 電圧 Vinが供給される。第 2端子 104と接地間には出力キャパシタ Coが接続される。 An inductor L1 is connected between the first terminal 102 of the control circuit 100 and the input terminal 202 of the step-up switching regulator 200. The input voltage Vin is supplied to the first terminal 102 via the inductor L1. An output capacitor Co is connected between the second terminal 104 and the ground.
[0031] 制御回路 100は、スイッチングトランジスタ SW1、同期整流用トランジスタ SW2、第 1トランジスタ Ml、第 2トランジスタ M2、ドライバ回路 10、スィッチ制御部 12、パルス 幅変調器 14を含み、 1つの半導体基板上に集積ィ匕されている。 [0031] The control circuit 100 includes a switching transistor SW1, a synchronous rectification transistor SW2, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a pulse width modulator 14, on one semiconductor substrate. Are collected.
[0032] スイッチングトランジスタ SW1は、 Nチャンネル MOSFETであって、ドレインが第 1 端子 102に接続され、ソースが接地されている。また、同期整流用トランジスタ SW2 は、 Pチャンネル MOSFETであって、ドレインが第 1端子 102に接続され、ソースが 第 2端子 104に接続される。スイッチングトランジスタ SW1、同期整流用トランジスタ S W2のゲートには、ドライバ回路 10から出力される第 1ゲート制御信号 Vgl、第 2ゲー ト制御信号 Vg2が入力される。 The switching transistor SW1 is an N-channel MOSFET, the drain is connected to the first terminal 102, and the source is grounded. The synchronous rectification transistor SW2 is a P-channel MOSFET, and has a drain connected to the first terminal 102 and a source connected to the second terminal 104. The first gate control signal Vgl and the second gate control signal Vg2 output from the driver circuit 10 are input to the gates of the switching transistor SW1 and the synchronous rectification transistor SW2.
[0033] 制御回路 100の電圧帰還端子 106には、昇圧型スイッチングレギユレータ 200の出 力電圧 Voutが帰還入力される。帰還された出力電圧 Voutは、パルス幅変調器 14 へと入力される。パルス幅変調器 14は、ハイレベルとローレベルの時間の比、すなわ ちデューティ比が変化するパルス幅変調信号 (以下 PWM信号 Vpwmと 、う)を生成 する。この PWM信号 Vpwmは、出力電圧 Voutが所定の基準電圧に近づくように、 そのデューティ比が制御される。 The output voltage Vout of the step-up switching regulator 200 is fed back to the voltage feedback terminal 106 of the control circuit 100. The output voltage Vout fed back is input to the pulse width modulator 14. The pulse width modulator 14 generates a pulse width modulation signal (hereinafter referred to as a PWM signal Vpwm) in which the ratio between the high level and the low level time, that is, the duty ratio changes. The duty ratio of the PWM signal Vpwm is controlled so that the output voltage Vout approaches a predetermined reference voltage.
[0034] ドライバ回路 10は、パルス幅変調器 14から出力される PWM信号 Vpwmにもとづ いて、第 1ゲート制御信号 Vgl、第 2ゲート制御信号 Vg2を生成し、それぞれスィッチ ングトランジスタ SW1、同期整流用トランジスタ SW2のゲートに出力する。スィッチン グトランジスタ SW1、同期整流用トランジスタ SW2は、 PWM信号 Vpwmのデューテ ィ比にもとづ 、て交互にオンオフを繰り返す。 [0034] The driver circuit 10 generates the first gate control signal Vgl and the second gate control signal Vg2 based on the PWM signal Vpwm output from the pulse width modulator 14, and the switching transistor SW1 and the Output to the gate of the rectifying transistor SW2. The switching transistor SW1 and the synchronous rectification transistor SW2 are alternately turned on and off based on the duty ratio of the PWM signal Vpwm.
[0035] 図 1に示すように、同期整流用トランジスタ SW2のバックゲートとドレイン間、あるい はバックゲートとソース間には、ボディダイオード (寄生ダイオード) Dl、 D2が存在す
る。以下、それぞれを第 1ボディダイオード Dl、第 2ボディダイオード D2という。通常 、この Pチャンネル MOSFETのバックゲートはソースに接続して使用されるため、第 2ボディダイオード D2の両端は短絡した状態で使用される。この場合に、昇圧停止 時において、第 1ボディダイオード D1を介して入力端子 202から出力端子 204に電 流が流れてしまうことは上述したとおりである。 [0035] As shown in FIG. 1, body diodes (parasitic diodes) Dl and D2 exist between the back gate and the drain of the synchronous rectification transistor SW2 or between the back gate and the source. The Hereinafter, these are referred to as a first body diode Dl and a second body diode D2. Normally, the back gate of this P-channel MOSFET is used connected to the source, so that both ends of the second body diode D2 are used in a short-circuited state. In this case, as described above, the current flows from the input terminal 202 to the output terminal 204 via the first body diode D1 when the boosting is stopped.
[0036] 一方、本実施の形態に係る制御回路 100では、同期整流用トランジスタ SW2のバ ックゲートをソースと接続する代わりに、第 1トランジスタ Ml、第 2トランジスタ M2を設 けている。 On the other hand, in the control circuit 100 according to the present embodiment, instead of connecting the back gate of the synchronous rectification transistor SW2 to the source, a first transistor Ml and a second transistor M2 are provided.
第 1トランジスタ Mlは、 Pチャンネル MOSFETであり、スイッチングトランジスタ SW 1のノ ックゲートと第 1端子 102間に設けられる。すなわち、第 1トランジスタ Mlのソー スは第 1端子 102に接続され、ドレインが同期整流用トランジスタ SW2のバックゲート に接続される。第 2トランジスタ M2も、 Pチャンネル MOSFETであり、スイッチングトラ ンジスタ SW1のノ ックゲートと第 2端子 104間に設けられる。すなわち、第 2トランジス タ M2のソースは同期整流用トランジスタ SW2のバックゲートに接続され、ドレインが 第 2端子 104に接続される。 The first transistor Ml is a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW 1 and the first terminal 102. That is, the source of the first transistor Ml is connected to the first terminal 102, and the drain is connected to the back gate of the synchronous rectification transistor SW2. The second transistor M2 is also a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW1 and the second terminal 104. That is, the source of the second transistor M2 is connected to the back gate of the synchronous rectification transistor SW2, and the drain is connected to the second terminal 104.
[0037] スィッチ制御部 12は、昇圧型スイッチングレギユレータ 200の動作状態に応じて、 第 1制御信号 Vcntl、第 2制御信号 Vcnt2を生成し、第 1トランジスタ Ml、第 2トラン ジスタ M2のゲート電圧を制御してそれぞれのオンオフを制御する。本実施の形態に おいて、昇圧型スイッチングレギユレータ 200は、昇圧動作を停止して負荷に対する 電力供給を停止する昇圧停止状態、昇圧動作により負荷に所定の出力電圧 Voutを 供給する昇圧動作状態、および昇圧停止状態から昇圧動作状態への遷移期間に対 応する起動状態の 3つの状態で動作する。 [0037] The switch control unit 12 generates the first control signal Vcntl and the second control signal Vcnt2 according to the operating state of the step-up switching regulator 200, and the gates of the first transistor Ml and the second transistor M2 Each voltage is controlled by controlling the voltage. In the present embodiment, the step-up switching regulator 200 is in a step-up stop state in which the step-up operation is stopped and power supply to the load is stopped, and a step-up operation state in which a predetermined output voltage Vout is supplied to the load by the step-up operation. And the start-up state corresponding to the transition period from the boost stop state to the boost operation state.
[0038] 以上のように構成された昇圧型スイッチングレギユレータ 200の動作にっ 、て説明 する。図 2は、昇圧型スイッチングレギユレータ 200の動作状態を示すタイムチャート である。同図は、説明を簡潔にするため、縦軸および横軸を適宜拡大、縮小して示し ている。 [0038] The operation of the step-up switching regulator 200 configured as described above will be described. FIG. 2 is a time chart showing the operating state of the step-up switching regulator 200. In the figure, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
[0039] 時刻 TO以前、昇圧型スイッチングレギユレータ 200は昇圧停止状態にある。このと き、スィッチ制御部 12は、第 1制御信号 Vcntl、第 2制御信号 Vcnt2をハイレベルと
して第 1トランジスタ Ml、第 2トランジスタ M2を両方ともオフとする。第 1トランジスタ M 1、第 2トランジスタ M2がともにオフとなると、同期整流用トランジスタ SW2の第 1ボデ ィダイオード Dl、第 2ボディダイオード D2に電流が流れなくなる。その結果、入力端 子 202と出力端子 204間で、同期整流用トランジスタ SW2のバックゲートを経由する 電流経路を遮断することができ、負荷に電流が流れ、あるいは出力端子 204に入力 電圧 Vinに近い電圧が現れるのを防止することができる。時刻 TO以前において、同 期整流用トランジスタ SW2のバックゲートの電位 Vbgはハイレベルとなって!/、る。 [0039] Prior to time TO, the step-up switching regulator 200 is in a step-up stop state. At this time, the switch control unit 12 sets the first control signal Vcntl and the second control signal Vcnt2 to high level. Then, both the first transistor Ml and the second transistor M2 are turned off. When both the first transistor M1 and the second transistor M2 are turned off, no current flows through the first body diode Dl and the second body diode D2 of the synchronous rectification transistor SW2. As a result, the current path via the back gate of the synchronous rectification transistor SW2 can be interrupted between the input terminal 202 and the output terminal 204, current flows through the load, or the output terminal 204 is close to the input voltage Vin. The voltage can be prevented from appearing. Before time TO, the potential Vbg of the back gate of the synchronous rectification transistor SW2 becomes high! /.
[0040] 時刻 TOに、図 1には図示しないスタンバイ信号 STBがローレベルからハイレベルと なり、昇圧型スイッチングレギユレータ 200の起動が指示される。スタンバイ信号 STB がハイレベルとなると、スィッチ制御部 12は第 1制御信号 Vcntlをローレベルとして 第 1トランジスタ Mlをオンする。また、スィッチ制御部 12は、第 2制御信号 Vcnt2を ハイレベルからローレベルへと緩やかに低下させる。その後、第 2制御信号 Vcnt2が 低下し、第 2トランジスタ M2のゲートソース間電圧がしきい値電圧 V り大きくなると 、第 2トランジスタ M2がオンする。第 2トランジスタ M2が徐々にオンすることにより、第 2端子 104に現れる出力電圧 Voutは、入力端子 202に印加される入力電圧 Vin付 近まで上昇していく。 [0040] At time TO, a standby signal STB (not shown in FIG. 1) changes from a low level to a high level, and activation of the step-up switching regulator 200 is instructed. When the standby signal STB becomes high level, the switch control unit 12 sets the first control signal Vcntl to low level and turns on the first transistor Ml. Further, the switch control unit 12 gradually decreases the second control signal Vcnt2 from the high level to the low level. Thereafter, when the second control signal Vcnt2 decreases and the gate-source voltage of the second transistor M2 becomes higher than the threshold voltage V, the second transistor M2 is turned on. As the second transistor M2 is gradually turned on, the output voltage Vout appearing at the second terminal 104 rises to near the input voltage Vin applied to the input terminal 202.
[0041] このように、本実施の形態に係る昇圧型スイッチングレギユレータ 200は、起動時に おいて、第 2トランジスタ M2を徐々にオンすることにより、突入電流の発生を抑制す ることがでさる。 As described above, the step-up switching regulator 200 according to the present embodiment can suppress the occurrence of the inrush current by gradually turning on the second transistor M2 at the time of startup. Monkey.
[0042] 時刻 T2に起動が完了すると、スィッチ制御部 12は第 1制御信号 Vcntlをハイレべ ルとして第 1トランジスタ Mlをオフする。その後、時刻 T3にパルス幅変調器 14およ びドライバ回路 10によってスイッチングトランジスタ SW1、同期整流用トランジスタ S W2のスイッチング動作を開始する。時刻 T3に昇圧動作を開始すると、出力電圧 Vo utは所定の基準電圧まで上昇する。 [0042] When the start-up is completed at time T2, the switch control unit 12 sets the first control signal Vcntl to high level and turns off the first transistor Ml. Thereafter, at time T3, the switching operation of the switching transistor SW1 and the synchronous rectification transistor SW2 is started by the pulse width modulator 14 and the driver circuit 10. When the boost operation is started at time T3, the output voltage Vout rises to a predetermined reference voltage.
本実施の形態に係る昇圧型スイッチングレギユレータ 200は、昇圧動作中において 、第 1トランジスタ Mlがオフ、第 2トランジスタ M2がオンの状態となる。これは、 Pチヤ ンネル MOSFETのバックゲートをソースと接続した状態と同様の回路状態であるた め、好適に昇圧動作を行うことができる。また、時刻 TOに起動を開始して力も所定の
期間経過後の時刻 T3に、昇圧動作を開始することにより、スイッチングトランジスタ S W1のバックゲート電圧 Vbgが低下して!/、る最中に、スイッチングトランジスタ SW1が オンしてラッチアップが発生するのを防止することができる。 In the step-up switching regulator 200 according to the present embodiment, the first transistor Ml is turned off and the second transistor M2 is turned on during the step-up operation. Since this is a circuit state similar to the state in which the back gate of the P-channel MOSFET is connected to the source, the boosting operation can be suitably performed. In addition, starting at time TO and the force By starting the boosting operation at time T3 after the lapse of the period, the back gate voltage Vbg of the switching transistor SW1 decreases! /, While the switching transistor SW1 is turned on and latch-up occurs. Can be prevented.
[0043] (第 2の実施の形態) [0043] (Second embodiment)
第 2の実施の形態は、同期整流方式の降圧型スイッチングレギユレータ 210に関す る。図 3は、第 2の実施の形態に係る降圧型スイッチングレギユレータ 210の構成を示 す回路図である。降圧型スイッチングレギユレータ 210は、制御回路 110、インダクタ Ll、出力キャパシタ Coを含む同期整流方式のスイッチングレギユレータである。同図 において、図 1と同一または同等の構成要素には同一の符号を付し、適宜説明を省 略する。 The second embodiment relates to a synchronous rectification step-down switching regulator 210. FIG. 3 is a circuit diagram showing a configuration of the step-down switching regulator 210 according to the second embodiment. The step-down switching regulator 210 is a synchronous rectification switching regulator including a control circuit 110, an inductor Ll, and an output capacitor Co. In this figure, the same or equivalent components as those in FIG.
[0044] 入力端子 212には入力電圧 Vinが印加されている。本実施の形態に係る降圧型ス イツチングレギユレータ 210は、入力電圧 Vinを降圧し、出力端子 214から出力電圧 Voutを出力する。制御回路 110の第 1端子 112と、降圧型スイッチングレギユレータ 210の出力端子 214間には、インダクタ L1が接続される。出力端子 214と接地間に は、出力キャパシタ Coが接続される。第 1端子 112は、外部に接続されるインダクタ L 1にスイッチング電圧 Vswを出力する。第 2端子 114には、外部から入力電圧 Vinが 供給される。 An input voltage Vin is applied to the input terminal 212. The step-down switching regulator 210 according to the present embodiment steps down the input voltage Vin and outputs the output voltage Vout from the output terminal 214. An inductor L1 is connected between the first terminal 112 of the control circuit 110 and the output terminal 214 of the step-down switching regulator 210. An output capacitor Co is connected between the output terminal 214 and the ground. The first terminal 112 outputs the switching voltage Vsw to the inductor L 1 connected to the outside. An input voltage Vin is supplied to the second terminal 114 from the outside.
[0045] 制御回路 110は、スイッチングトランジスタ SW3、同期整流用トランジスタ SW4、第 1トランジスタ Ml、第 2トランジスタ M2、ドライバ回路 10、スィッチ制御部 12、パルス 幅変調器 14を含む。 The control circuit 110 includes a switching transistor SW3, a synchronous rectification transistor SW4, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a pulse width modulator 14.
[0046] 同期整流用トランジスタ SW4は、 Nチャンネル MOSFETであって、ドレインが第 1 端子 112に接続され、ソースが接地されている。また、スイッチングトランジスタ SW3 は、 Pチャンネル MOSFETであって、ドレインが第 1端子 112に接続され、ソースが 第 2端子 114に接続される。スイッチングトランジスタ SW3、同期整流用トランジスタ S W4のゲートには、ドライバ回路 10から出力される第 1ゲート制御信号 Vg3、第 2ゲー ト制御信号 Vg4が入力される。 The synchronous rectification transistor SW4 is an N-channel MOSFET, and has a drain connected to the first terminal 112 and a source grounded. The switching transistor SW3 is a P-channel MOSFET, and has a drain connected to the first terminal 112 and a source connected to the second terminal 114. The first gate control signal Vg3 and the second gate control signal Vg4 output from the driver circuit 10 are input to the gates of the switching transistor SW3 and the synchronous rectification transistor SW4.
[0047] 制御回路 110の電圧帰還端子 116には、降圧型スイッチングレギユレータ 210の出 力電圧 Voutが帰還入力される。帰還された出力電圧 Voutは、パルス幅変調器 14
へと入力される。パルス幅変調器 14およびドライバ回路 10は、帰還された出力電圧 Voutにもとづき、スイッチングトランジスタ SW3、同期整流用トランジスタ SW4を駆動 する。 The output voltage Vout of the step-down switching regulator 210 is fed back to the voltage feedback terminal 116 of the control circuit 110. The feedback output voltage Vout is the pulse width modulator 14 Is input. The pulse width modulator 14 and the driver circuit 10 drive the switching transistor SW3 and the synchronous rectification transistor SW4 based on the feedback output voltage Vout.
[0048] 本実施の形態に係る制御回路 110では、スイッチングトランジスタ SW3のバックゲ ートをソースと接続する代わりに、第 1トランジスタ Ml、第 2トランジスタ M2を設けてい る。 [0048] In the control circuit 110 according to the present embodiment, instead of connecting the back gate of the switching transistor SW3 to the source, a first transistor Ml and a second transistor M2 are provided.
第 1トランジスタ Mlは、 Pチャンネル MOSFETであり、スイッチングトランジスタ SW 3のノ ックゲートと第 1端子 112間に設けられる。すなわち、第 1トランジスタ Mlのソー スは第 1端子 112に接続され、ドレインがスイッチングトランジスタ SW3のバックゲート に接続される。 The first transistor Ml is a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW 3 and the first terminal 112. That is, the source of the first transistor Ml is connected to the first terminal 112, and the drain is connected to the back gate of the switching transistor SW3.
第 2トランジスタ M2も、 Pチャンネル MOSFETであり、スイッチングトランジスタ SW 3のノ ックゲートと第 2端子 114間に設けられる。すなわち、第 2トランジスタ M2のソー スはスイッチングトランジスタ SW3のバックゲートに接続され、ドレインが第 2端子 114 に接続される。 The second transistor M2 is also a P-channel MOSFET, and is provided between the knock gate of the switching transistor SW3 and the second terminal 114. That is, the source of the second transistor M2 is connected to the back gate of the switching transistor SW3, and the drain is connected to the second terminal 114.
[0049] スィッチ制御部 12は、降圧型スイッチングレギユレータ 210の動作状態に応じて、 第 1制御信号 Vcntl、第 2制御信号 Vcnt2を生成し、第 1トランジスタ Ml、第 2トラン ジスタ M2のゲート電圧を制御してそれぞれのオンオフを制御する。本実施の形態に おいて、降圧型スイッチングレギユレータ 210は、降圧動作を停止して負荷に対する 電力供給を停止する降圧停止状態、降圧動作により負荷に所定の出力電圧 Voutを 供給する降圧動作状態、および降圧停止状態から降圧動作状態への遷移期間に対 応する起動状態の 3つの状態で動作する。 [0049] The switch control unit 12 generates the first control signal Vcntl and the second control signal Vcnt2 according to the operating state of the step-down switching regulator 210, and the gates of the first transistor Ml and the second transistor M2 Each voltage is controlled by controlling the voltage. In the present embodiment, the step-down switching regulator 210 is a step-down stop state in which the step-down operation is stopped to stop power supply to the load, and a step-down operation state in which a predetermined output voltage Vout is supplied to the load by the step-down operation. , And the start-up state corresponding to the transition period from the step-down stop state to the step-down operation state.
[0050] 以上のように構成された降圧型スイッチングレギユレータ 210の動作について説明 する。図 4は、降圧型スイッチングレギユレータ 210の動作状態を示すタイムチャート である。同図は、説明を簡潔にするため、縦軸および横軸を適宜拡大、縮小して示し ている。 [0050] The operation of the step-down switching regulator 210 configured as described above will be described. FIG. 4 is a time chart showing the operating state of the step-down switching regulator 210. In the figure, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
[0051] 時刻 TO以前、降圧型スイッチングレギユレータ 210は降圧停止状態にある。このと き、スィッチ制御部 12は、第 1制御信号 Vcntl、第 2制御信号 Vcnt2をハイレベルと して第 1トランジスタ Ml、第 2トランジスタ M2を両方ともオフとする。第 1トランジスタ M
1、第 2トランジスタ M2がともにオフとなると、スイッチングトランジスタ SW3の第 1ボデ ィダイオード Dl、第 2ボディダイオード D2に電流が流れなくなる。時刻 TO以前にお いて、同期整流用トランジスタ SW2のバックゲートの電位 Vbgはハイレベルとなって いる。 Prior to time TO, the step-down switching regulator 210 is in a step-down stop state. At this time, the switch control unit 12 sets the first control signal Vcntl and the second control signal Vcnt2 to high level to turn off both the first transistor Ml and the second transistor M2. 1st transistor M When both the first and second transistors M2 are turned off, no current flows through the first body diode Dl and the second body diode D2 of the switching transistor SW3. Before the time TO, the potential Vbg of the back gate of the synchronous rectification transistor SW2 is high.
[0052] 時刻 TOに、図 3には図示しないスタンバイ信号 STBがローレベルからハイレベルと なり、降圧型スイッチングレギユレータ 210の降圧動作の開始が指示される。スタンバ ィ信号 STBがハイレベルとなると、スィッチ制御部 12は第 1制御信号 Vcntlをノヽィレ ベルに維持しつつ、第 2制御信号 Vcnt2をハイレベルからローレベルへと緩やかに 低下させる。このとき、スイッチングトランジスタ SW3のバックゲート電圧 Vbgはハイレ ベルのまま保持される。 At time TO, a standby signal STB (not shown in FIG. 3) changes from a low level to a high level, and the start of the step-down operation of step-down switching regulator 210 is instructed. When the standby signal STB becomes high level, the switch control unit 12 gradually decreases the second control signal Vcnt2 from high level to low level while maintaining the first control signal Vcntl at the neutral level. At this time, the back gate voltage Vbg of the switching transistor SW3 is maintained at a high level.
[0053] このように、本実施の形態に係る降圧型スイッチングレギユレータ 210は、起動時に おいて、第 1トランジスタ Mlをオフしておくことにより、スイッチング電圧 Vswに入力電 圧 Vinが現れるのを防止することができる。 As described above, the step-down switching regulator 210 according to the present embodiment causes the input voltage Vin to appear in the switching voltage Vsw by turning off the first transistor Ml at the time of startup. Can be prevented.
[0054] 時刻 T1に起動が完了する。その後、時刻 T2にパルス幅変調器 14およびドライバ 回路 10によってスイッチングトランジスタ SW3、同期整流用トランジスタ SW4のスイツ チング動作を開始する。時刻 T2に降圧動作を開始すると、出力電圧 Voutは所定の 基準電圧 Vrefまで上昇する。 [0054] Startup is completed at time T1. After that, at time T2, the switching operation of the switching transistor SW3 and the synchronous rectification transistor SW4 is started by the pulse width modulator 14 and the driver circuit 10. When step-down operation is started at time T2, the output voltage Vout rises to the specified reference voltage Vref.
本実施の形態に係る降圧型スイッチングレギユレータ 210は、降圧動作中において 、第 1トランジスタ Mlがオフ、第 2トランジスタ M2がオンの状態となる。これは、 Pチヤ ンネル MOSFETのバックゲートをソースと接続した状態と同様の回路状態であるた め、好適に降圧動作を行うことができる。 In the step-down switching regulator 210 according to the present embodiment, the first transistor Ml is off and the second transistor M2 is on during the step-down operation. Since this is a circuit state similar to the state in which the back gate of the P-channel MOSFET is connected to the source, the step-down operation can be suitably performed.
[0055] (第 3の実施の形態) [0055] (Third embodiment)
図 1に示す制御回路 100と、図 3に示す制御回路 110は、同等の回路構成となって おり、外付けされるインダクタ Ll、出力キャパシタ Coの配置および入力電圧 Vin、出 力電圧 Voutの現れる位置が異なっている。そこで、第 3の実施の形態では、図 1の 制御回路 100と図 3の制御回路 110を、昇圧型、降圧型が切り替え可能なスィッチン グレギユレータの制御回路として利用する。 The control circuit 100 shown in FIG. 1 and the control circuit 110 shown in FIG. 3 have the same circuit configuration, and the arrangement of the external inductor Ll, output capacitor Co, input voltage Vin, and output voltage Vout appear. The position is different. Therefore, in the third embodiment, the control circuit 100 in FIG. 1 and the control circuit 110 in FIG. 3 are used as a control circuit for a switching regulator capable of switching between a step-up type and a step-down type.
[0056] 図 5は、第 3の実施の形態に係る制御回路 120の構成を示す回路図である。制御
回路 120は、第 1スイッチングトランジスタ SW5、第 2スイッチングトランジスタ SW6、 第 1トランジスタ Ml、第 2トランジスタ M2、ドライバ回路 10、スィッチ制御部 12、ノ ル ス幅変調器 14を含む。第 1スイッチングトランジスタ SW5は、昇圧モード時において スイッチングトランジスタとして機能し、降圧モード時において同期整流用トランジスタ として機能する。また、第 2スイッチングトランジスタ SW6は、昇圧モード時において 同期整流用トランジスタとして機能し、降圧モード時においてスイッチングトランジスタ として機能する。第 1トランジスタ Ml、第 2トランジスタ M2はいずれも Pチャンネル M OSFETである。電圧帰還端子 126には、出力電圧が帰還される。第 1端子 122は、 図 1の第 1端子 102あるいは図 3の第 1端子 112に対応し、第 2端子 124は、図 1の第 2端子 104あるいは図 3の第 2端子 114に対応する。 FIG. 5 is a circuit diagram showing a configuration of the control circuit 120 according to the third embodiment. control The circuit 120 includes a first switching transistor SW5, a second switching transistor SW6, a first transistor Ml, a second transistor M2, a driver circuit 10, a switch control unit 12, and a noise width modulator 14. The first switching transistor SW5 functions as a switching transistor in the step-up mode, and functions as a synchronous rectification transistor in the step-down mode. The second switching transistor SW6 functions as a synchronous rectification transistor in the step-up mode, and functions as a switching transistor in the step-down mode. The first transistor Ml and the second transistor M2 are both P-channel MOS FETs. The output voltage is fed back to the voltage feedback terminal 126. The first terminal 122 corresponds to the first terminal 102 in FIG. 1 or the first terminal 112 in FIG. 3, and the second terminal 124 corresponds to the second terminal 104 in FIG. 1 or the second terminal 114 in FIG.
[0057] 第 1トランジスタ Mlは、第 2スイッチングトランジスタ SW6のバックゲートとドレイン間 に設けられる。また、第 2トランジスタ M2は、第 2スイッチングトランジスタのバックゲー トとソース間に設けられる。 [0057] The first transistor Ml is provided between the back gate and the drain of the second switching transistor SW6. The second transistor M2 is provided between the back gate and the source of the second switching transistor.
[0058] モード端子 128には、昇圧モードあるいは降圧モードを指定するモード指示信号 M ODEが入力される。このモード指示信号 MODEは、スィッチ制御部 12に入力され ている。スィッチ制御部 12は、モード指示信号 MODEによって、昇圧モードで動作 すべきか、降圧モードで動作すべきかを判定し、判定した結果にもとづいて第 1トラン ジスタ Ml、第 2トランジスタ M2のオンオフを制御する。スィッチ制御部 12は、昇圧モ ード時においては、第 1の実施の形態で説明した方式で第 1トランジスタ Ml、第 2トラ ンジスタ M2を制御し、降圧モード時においては、第 2の実施の形態で説明した方式 で第 1トランジスタ Ml、第 2トランジスタ M2を制御する。 A mode instruction signal MODE for designating the step-up mode or the step-down mode is input to the mode terminal 128. The mode instruction signal MODE is input to the switch control unit 12. The switch control unit 12 determines whether to operate in the step-up mode or the step-down mode based on the mode instruction signal MODE, and controls on / off of the first transistor Ml and the second transistor M2 based on the determination result. . The switch control unit 12 controls the first transistor Ml and the second transistor M2 by the method described in the first embodiment in the step-up mode, and the second embodiment in the step-down mode. The first transistor Ml and the second transistor M2 are controlled by the method described in the embodiment.
[0059] このように構成された制御回路 120によれば、ユーザが昇圧型スイッチングレギユレ ータ、あるいは降圧型スイッチングレギユレータのいずれの制御回路として使用した 場合にも、第 1トランジスタ Ml、第 2トランジスタ M2を制御することができる。 [0059] According to the control circuit 120 configured as described above, even when the user uses the control circuit as either a step-up switching regulator or a step-down switching regulator, the first transistor Ml, The second transistor M2 can be controlled.
[0060] 図 6は、図 1、図 3、図 5の制御回路 100、 110、 120が好適に使用される電子機器 300の構成を示すブロック図である。電子機器 300は、たとえばデジタルスチルカメラ や携帯電話端末であり、電池 310、電源装置 320、アナログ回路 330、デジタル回路 340、マイコン 350、 LED360を含む。
電池 310は、たとえばリチウムイオン電池であり、電池電圧 Vbatとして 3〜4V程度 を出力する。アナログ回路 330は、電源電圧 Vcc = 3. 4V程度で安定動作する回路 ブロックを含む。また、デジタル回路 340は、各種 DSP (Digital Signal Processo r)などを含み、電源電圧 Vdd= 3. 4V程度で安定動作する回路ブロックを含む。マイ コン 350は、電子機器 300全体を統括的に制御するブロックであり、電源電圧 1. 5V で動作する。1^:0360は、1¾}83色の1^:0 ( 31^ Emitting Diode)を含み、液 晶のノ ックライトや、照明として用いられ、その駆動には、 4V以上の駆動電圧が要求 される。 FIG. 6 is a block diagram showing a configuration of an electronic device 300 in which the control circuits 100, 110, 120 of FIGS. 1, 3, and 5 are preferably used. The electronic device 300 is, for example, a digital still camera or a mobile phone terminal, and includes a battery 310, a power supply device 320, an analog circuit 330, a digital circuit 340, a microcomputer 350, and an LED 360. The battery 310 is, for example, a lithium ion battery, and outputs about 3 to 4 V as the battery voltage Vbat. The analog circuit 330 includes a circuit block that stably operates at a power supply voltage Vcc = 3.4V. The digital circuit 340 includes various DSPs (Digital Signal Processors) and the like, and includes a circuit block that stably operates at a power supply voltage Vdd = 3.4V. The microcomputer 350 is a block that comprehensively controls the entire electronic device 300, and operates at a power supply voltage of 1.5V. 1 ^: 0360 includes 1 ^} 83 (1 ^: 0) (31 ^ Emitting Diode) of 1¾}, and is used as a liquid crystal knock light or lighting. A drive voltage of 4V or more is required for driving. .
[0061] 電源装置 320は、多チャンネルのスイッチング電源であり、各チャンネルごとに、電 池電圧 Vbatを必要に応じて降圧、または昇圧するスイッチングレギユレータを備えて おり、アナログ回路 330、デジタル回路 340、マイコン 350、 LED360に対して適切 な電源電圧を供給する。 [0061] The power supply device 320 is a multi-channel switching power supply, and includes a switching regulator for stepping down or stepping up the battery voltage Vbat as necessary for each channel. The analog circuit 330, the digital circuit Supply appropriate power supply voltage to 340, microcomputer 350, and LED360.
本実施の形態に係る図 5の制御回路 120は、複数個、並列に配置して多チャンネ ル制御回路を構成することにより、こうした電源装置 320に好適に用いることができる 。すなわち、 4チャンネルの制御回路を構成した場合において、マイコン 350に電源 電圧を供給する第 3チャンネル CH3は、降圧モードとして動作させ、 LED360に電 源電圧を供給する第 4チャンネル CH4は、昇圧モードとして動作させればよ!、。 The control circuit 120 of FIG. 5 according to the present embodiment can be suitably used for such a power supply device 320 by arranging a plurality of control circuits 120 in parallel to constitute a multi-channel control circuit. That is, when a 4-channel control circuit is configured, the third channel CH3 that supplies the power supply voltage to the microcomputer 350 is operated in the step-down mode, and the fourth channel CH4 that supplies the power supply voltage to the LED 360 is in the step-up mode. Just make it work!
[0062] 上記実施の形態は例示であり、それらの各構成要素や各処理プロセスの組合せに いろいろな変形例が可能なこと、またそうした変形例も本発明の範囲にあることは当 業者に理解されるところである。 [0062] The above embodiment is merely an example, and it is understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. It is where it is done.
[0063] 実施の形態では、制御回路 100などがひとつの LSIに一体集積ィ匕される場合につ いて説明したが、これには限定されず、一部の構成要素が LSIの外部にディスクリー ト素子あるいはチップ部品として設けられ、あるいは複数の LSIにより構成されてもよ い。 In the embodiment, the case where the control circuit 100 or the like is integrated in one LSI has been described. However, the present invention is not limited to this, and some components are discretely provided outside the LSI. It may be provided as a chip element or chip component, or may be composed of multiple LSIs.
[0064] また、本実施の形態にお!、て、ハイレベル、ローレベルの論理値の設定は一例で あって、インバータなどによって適宜反転させることにより自由に変更することが可能 である。 [0064] In the present embodiment, the setting of the logic values of the high level and the low level is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.
[0065] 実施の形態にもとづき、本発明を説明したが、実施の形態は、本発明の原理、応用
を示しているにすぎないことはいうまでもなぐ実施の形態には、請求の範囲に規定さ れた本発明の思想を離脱しない範囲において、多くの変形例や配置の変更が可能 であることは 、うまでもな!/、。 [0065] Although the present invention has been described based on the embodiment, the embodiment describes the principle and application of the present invention. Needless to say, in the embodiment, many modifications and arrangements can be made without departing from the spirit of the present invention defined in the claims. It ’s ugly! /.
産業上の利用可能性 Industrial applicability
本発明に係るスイッチングレギユレータの制御回路は、電源装置に利用することが できる。
The control circuit of the switching regulator according to the present invention can be used for a power supply device.
Claims
[1] 同期整流方式の昇圧型スイッチングレギユレータの制御回路であって、 [1] A control circuit for a synchronous rectification step-up switching regulator,
外部に接続されるインダクタを介して入力電圧が供給される第 1端子と、 出力キャパシタが接続される第 2端子と、 A first terminal to which an input voltage is supplied via an externally connected inductor, a second terminal to which an output capacitor is connected,
前記第 1端子と接地間に設けられたスイッチングトランジスタと、 A switching transistor provided between the first terminal and the ground;
前記第 1端子と前記第 2端子間に設けられた同期整流用トランジスタと、 前記同期整流用トランジスタのバックゲートと前記第 1端子間に設けられた第 1トラ ンジスタと、 A synchronous rectification transistor provided between the first terminal and the second terminal; a first transistor provided between a back gate of the synchronous rectification transistor and the first terminal;
前記同期整流用トランジスタのバックゲートと前記第 2端子間に設けられた第 2トラ ンジスタと、 A second transistor provided between a back gate of the synchronous rectification transistor and the second terminal;
前記第 1、第 2トランジスタのオンオフを制御するスィッチ制御部と、 A switch controller for controlling on / off of the first and second transistors;
を備えることを特徴とする制御回路。 A control circuit comprising:
[2] 前記スィッチ制御部は、本制御回路により駆動される前記昇圧型スイッチングレギ ユレ一タの昇圧停止期間において、前記第 1トランジスタおよび前記第 2トランジスタ をオフし、昇圧動作期間において、前記第 1トランジスタをオフし、前記第 2トランジス タをオンすることを特徴とする請求項 1に記載の制御回路。 [2] The switch control unit turns off the first transistor and the second transistor during the boost stop period of the boost switching regulator driven by the control circuit, and the first controller during the boost operation period. 2. The control circuit according to claim 1, wherein one transistor is turned off and the second transistor is turned on.
[3] 前記スィッチ制御部は、前記昇圧型スイッチングレギユレ一タの昇圧停止状態から 昇圧動作状態に遷移する起動期間に、前記第 1トランジスタをオンした状態で、前記 第 2トランジスタを徐々にオンすることを特徴とする請求項 2に記載の制御回路。 [3] The switch control unit gradually turns on the second transistor while the first transistor is turned on during a start-up period in which the step-up switching regulator transitions from a boost stop state to a boost operation state. The control circuit according to claim 2, wherein:
[4] 前記同期整流用トランジスタ、前記第 1トランジスタおよび前記第 2トランジスタは、 P チャンネル MOSFET (Metal Oxide Semiconductor Field Effect Transis tor)であることを特徴とする請求項 1から 3のいずれかに記載の制御回路。 4. The synchronous rectification transistor, the first transistor, and the second transistor are P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), according to any one of claims 1 to 3. Control circuit.
[5] 同期整流方式の降圧型スイッチングレギユレータの制御回路であって、 [5] A control circuit for a synchronous rectification step-down switching regulator,
外部に接続されるインダクタにスイッチング電圧を出力する第 1端子と、 外部から入力電圧が供給される第 2端子と、 A first terminal for outputting a switching voltage to an externally connected inductor, a second terminal for supplying an input voltage from the outside,
前記第 1端子と前記第 2端子間に設けられたスイッチングトランジスタと、 前記第 1端子と接地間に設けられた同期整流用トランジスタと、 A switching transistor provided between the first terminal and the second terminal; a synchronous rectification transistor provided between the first terminal and the ground;
前記スイッチングトランジスタのノックゲートと前記第 1端子間に設けられた第 1トラ
ンジスタと、 A first transistor provided between a knock gate of the switching transistor and the first terminal. And
前記スイッチングトランジスタのバックゲートと前記第 2端子間に設けられた第 2トラ ンジスタと、 A second transistor provided between the back gate of the switching transistor and the second terminal;
前記第 1、第 2トランジスタのオンオフを制御するスィッチ制御部と、 A switch controller for controlling on / off of the first and second transistors;
を備えることを特徴とする制御回路。 A control circuit comprising:
[6] 前記スィッチ制御部は、本制御回路により駆動される前記降圧型スイッチングレギ ユレ一タの降圧停止期間において、前記第 1トランジスタおよび前記第 2トランジスタ をオフし、降圧動作期間において、前記第 1トランジスタをオフし、前記第 2トランジス タをオンすることを特徴とする請求項 5に記載の制御回路。 [6] The switch control unit turns off the first transistor and the second transistor in the step-down stop period of the step-down switching regulator driven by the control circuit, and turns off the first transistor and the second transistor in the step-down operation period. 6. The control circuit according to claim 5, wherein one transistor is turned off and the second transistor is turned on.
[7] 前記スィッチ制御部は、前記降圧型スイッチングレギユレ一タの降圧停止状態から 降圧動作状態に遷移する起動期間に、前記第 1トランジスタをオフした状態で、前記 第 2トランジスタを徐々にオンすることを特徴とする請求項 6に記載の制御回路。 [7] The switch control unit gradually turns on the second transistor while the first transistor is turned off during the start-up period in which the step-down switching regulator transitions from the step-down stop state to the step-down operation state. The control circuit according to claim 6, wherein:
[8] 前記スイッチングトランジスタ、前記第 1トランジスタおよび前記第 2トランジスタは、 P チャンネル MOSFET (Metal Oxide Semiconductor Field Effect Transis tor)であることを特徴とする請求項 5から 7のいずれかに記載の制御回路。 8. The control circuit according to claim 5, wherein the switching transistor, the first transistor, and the second transistor are P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). .
[9] 昇圧モードまたは降圧モードを切り替え可能なスイッチングレギユレータの制御回 路であって、 [9] A switching regulator control circuit capable of switching between step-up mode and step-down mode,
昇圧モード時にぉ 、てスイッチングトランジスタとして機能し、降圧モード時にぉ ヽ て同期整流用トランジスタとして機能する第 1スイッチングトランジスタと、 A first switching transistor that functions as a switching transistor in the step-up mode and functions as a synchronous rectification transistor in the step-down mode;
昇圧モード時において同期整流用トランジスタとして機能し、降圧モード時におい てスイッチングトランジスタとして機能する第 2スイッチングトランジスタと、 A second switching transistor that functions as a synchronous rectification transistor in the step-up mode and functions as a switching transistor in the step-down mode;
前記第 2スイッチングトランジスタのノックゲートとドレイン間に設けられた第 1トラン ジスタと、 A first transistor provided between a knock gate and a drain of the second switching transistor;
前記第 2スイッチングトランジスタのノックゲートとソース間に設けられた第 2トランジ スタと、 A second transistor provided between a knock gate and a source of the second switching transistor;
前記第 1、第 2トランジスタのオンオフを制御するスィッチ制御部と、 A switch controller for controlling on / off of the first and second transistors;
を備えることを特徴とする制御回路。 A control circuit comprising:
[10] 前記スイッチングトランジスタ、前記同期整流用トランジスタ、前記第 1トランジスタ、
前記第 2トランジスタならびに前記スィッチ制御部は、 1つの半導体基板上に一体集 積化されることを特徴とする請求項 1、 5、 9のいずれか〖こ記載の制御回路。 [10] The switching transistor, the synchronous rectification transistor, the first transistor, 10. The control circuit according to claim 1, wherein the second transistor and the switch control unit are integrated on a single semiconductor substrate.
[11] 請求項 1から 3のいずれかに記載の制御回路と、 [11] The control circuit according to any one of claims 1 to 3,
一端が前記制御回路の前記第 1端子に接続され、他端に入力電圧が印加されるィ ンダクタと、 An inductor having one end connected to the first terminal of the control circuit and an input voltage applied to the other end;
一端が前記制御回路の前記第 2端子に接続され、他端が接地された出力キャパシ タと、 An output capacitor having one end connected to the second terminal of the control circuit and the other end grounded;
を備え、前記出力キャパシタの一端の電圧を出力することを特徴とする昇圧型スィ ツチングレギユレータ。 A step-up switching regulator comprising: outputting a voltage at one end of the output capacitor.
[12] 電池と、 [12] batteries,
前記電池の電圧を昇圧もしくは降圧する請求項 11に記載のスイッチングレギユレ一 タと、 The switching regulator according to claim 11, wherein the voltage of the battery is increased or decreased.
を備えることを特徴とする電子機器。 An electronic device comprising:
[13] 一端が接地された出力キャパシタと、 [13] an output capacitor with one end grounded;
前記出力キャパシタの他端にその一端が接続されたインダクタと、 An inductor having one end connected to the other end of the output capacitor;
前記インダクタの他端に前記スイッチング電圧を供給する請求項 5から 7のいずれ かに記載の制御回路と、 The control circuit according to any one of claims 5 to 7, wherein the switching voltage is supplied to the other end of the inductor.
を備え、前記出力キャパシタの他端の電圧を出力することを特徴とする降圧型スィ ツチングレギユレータ。 And a step-down switching regulator that outputs a voltage at the other end of the output capacitor.
[14] 電池と、 [14] batteries,
前記電池の電圧を昇圧もしくは降圧する請求項 13に記載のスイッチングレギユレ一 タと、 The switching regulator according to claim 13, wherein the voltage of the battery is increased or decreased.
を備えることを特徴とする電子機器。
An electronic device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/995,781 US20090122585A1 (en) | 2005-07-15 | 2006-07-12 | Step-up/down switching regulator |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005206607A JP4652918B2 (en) | 2005-07-15 | 2005-07-15 | STEP-UP SWITCHING REGULATOR, ITS CONTROL CIRCUIT, AND ELECTRONIC DEVICE USING THE SAME |
JP2005-206607 | 2005-07-15 |
Publications (1)
Publication Number | Publication Date |
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WO2007010801A1 true WO2007010801A1 (en) | 2007-01-25 |
Family
ID=37668683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/313881 WO2007010801A1 (en) | 2005-07-15 | 2006-07-12 | Step-up/down switching regulator, its control circuit, and electronic apparatus using same |
Country Status (5)
Country | Link |
---|---|
US (1) | US20090122585A1 (en) |
JP (1) | JP4652918B2 (en) |
CN (1) | CN101218734A (en) |
TW (1) | TW200705788A (en) |
WO (1) | WO2007010801A1 (en) |
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Also Published As
Publication number | Publication date |
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TW200705788A (en) | 2007-02-01 |
JP2007028784A (en) | 2007-02-01 |
CN101218734A (en) | 2008-07-09 |
US20090122585A1 (en) | 2009-05-14 |
JP4652918B2 (en) | 2011-03-16 |
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