WO2007007478A1 - Polycrystalline silicon substrate, polycrystalline silicon ingot, and production process - Google Patents

Abstract

Regarding the impurity concentration of a polycrystalline silicon substrate, a region satisfying the following requirement is present in a substrate: Nspin ≤ 3.5E14 (condition 1) wherein Nspin represents the spin density at g value = 2.005 to 2.006 as measured at a temperature of about 10K by ESR (electron spin resonance) in a cleavage face of the substrate, spins/cm3. In the polycrystalline silicon substrate satisfying this condition, the electron spin density is lower than the threshold value, and the density of recombination level is small. Accordingly, the substrate has good quality and high photoelectric conversion efficiency.

Description

 Specification

 Polycrystalline silicon substrate, polycrystalline silicon ingot, and manufacturing method

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to a polycrystalline silicon substrate, a polycrystalline silicon ingot, and a manufacturing method thereof for realizing a polycrystalline silicon solar cell or the like having high photoelectric conversion efficiency. By using this polycrystalline silicon substrate, for example, a photoelectric conversion element or a photoelectric conversion module in which these are arranged can be manufactured.

In this specification, the notation aEn represents a X 10 ⁿ . “” Represents a power.

 Background art

 [0002] Currently, the mainstream solar cell product is a Balta type crystalline Si solar cell using a crystalline silicon substrate.

 In particular, the type using a polycrystalline silicon substrate has both maximum efficiency and low cost, and therefore has the largest production scale, and it is expected that the production volume will further increase in the future. Patent Document 1 below shows high energy conversion efficiency in consideration of the concentration relationship among light element impurities such as C, O, B, and P when manufacturing a polycrystalline silicon ingot from which a polycrystalline Si substrate is cut out. The results of examining the manufacturing conditions of the polycrystalline silicon ingot to obtain are shown.

 [0003] Patent Document 2 below describes a purification method for removing C and O at the stage of molten silicon in the production of silicon for solar cells.

 Patent Document 3 below describes a purification method for removing C and O at the molten silicon stage in the production of a solar cell silicon ingot, respectively.

 Patent Document 4 below shows a production method in which the ratio of O and C content is optimized in the production of silicon ingots for solar cells.

 Patent Document 1: Japanese Patent Laid-Open No. 10-251010

 Patent Document 2: Japanese Patent Laid-Open No. 10-265213

Patent Document 3: Japanese Patent Laid-Open No. 10-182134 Patent Document 4: JP-A-2-38305

 Disclosure of the invention

 Problems to be solved by the invention

[0004] As described above, currently mainstream solar cells are Balta type polycrystalline silicon solar cells using a polycrystalline silicon substrate (hereinafter simply referred to as "polycrystalline silicon solar cells" or "polycrystalline silicon elements"). The low cost is indispensable for further dissemination in the future.

 High efficiency (high performance) is very important for low cost (Solar cell market price and manufacturing cost are generally expressed in unit price per watt [yen / W]. Higher efficiency increases the output (W) of the denominator, which has the effect of reducing market prices and manufacturing costs).

 [0005] Various technical elements are related to the high efficiency of the polycrystalline silicon solar cell. Among them, the high quality of the polycrystalline silicon substrate is the most important.

 Regarding the quality of a polycrystalline silicon substrate, there are quality indexes based on various evaluation methods and various quality factors.

 For example, as representative quality evaluation methods and quality indicators, the minority carrier lifetime τ by the PCD method (microwave photoelectric attenuation method) and the minority carrier diffusion length L by the SPV method (surface photovoltaic method) are known. And

[0006] In addition, quality factors that are the origin of these quality indices include (1) intrinsic defects inherent in polycrystalline silicon such as grain boundaries, dislocations, or vacancy and interstitial Si, and ( 2) There are extrinsic defects due to metal impurities, light element impurities, and precipitates from various compounds.

 Conventionally, the lifetime and diffusion length L are used as the standard indicators of substrate quality, and in the direction of increasing these (in order to achieve high τ or high L substrates, aiming for high efficiency and high yield. Efforts have been made to improve board quality.

[0007] However, since the quality of the polycrystalline silicon substrate changes after the device fabrication process for manufacturing the solar cell, it was measured by, for example, the lifetime τ measured by the μ PCD method or the SPV method. Even substrates with low diffusion quality, such as diffusion length L, are not necessarily manufactured The efficiency of the pond was low, but it was limited.

 Therefore, a new substrate quality index that is directly related to device characteristics is currently being demanded. In other words, if the device characteristics can be predicted in advance in the state of the substrate before the device is made, it will be possible to rank the device according to the quality of the substrate, and more efficient manufacturing (depending on the substrate quality) This is because processes can be performed).

 [0008] Further, conventionally, control and management of light element concentrations such as oxygen 0, carbon C, and nitrogen N in a polycrystalline silicon substrate have been insufficient. For this reason, it is difficult to increase the solar cell efficiency sufficiently.

 In other words, it is already known that O, C, and N have little influence on substrate quality and solar cell efficiency. The specific conditions for how much the concentration should be set are not necessarily clear. Then I helped. Even if the concentration conditions to be targeted are clear, no sufficient control technology has been established to achieve this.

[0009] Therefore, the present invention is based on knowledge of a new substrate quality index that is directly related to device characteristics and knowledge of high-quality conditions of a polycrystalline silicon ingot and a substrate, and a high-quality polycrystalline silicon substrate, polycrystalline It is an object of the present invention to provide a silicon ingot and a method for manufacturing the silicon substrate.

 Another object of the present invention is to provide a highly efficient photoelectric conversion element and photoelectric conversion module using the polycrystalline silicon substrate.

 Means for solving the problem

The polycrystalline silicon substrate for photoelectric conversion elements of the present invention (hereinafter referred to as “polycrystalline silicon substrate”) is a cleavage plane of the substrate by an ESR (electron spin resonance) method with respect to the impurity concentration in the polycrystalline silicon substrate. , When the spin density at g value = 2.005 to 2.006 measured at a temperature of about 10 K is Nspin (where the spin density unit is [spins / cm ³ ]),

 Nspin ≤ 3.5E14 (Condition 1)

 A region that satisfies the above condition exists in the substrate.

[0011] Further, a polycrystalline silicon substrate of the present invention, in addition to the condition, the interstitial oxygen concentration measured by Fourier transform infrared spectroscopy _{[Oi] [a tom S /} C m 3], the substitution position carbon When the concentration is [Cs] [atom s / cm ³ ], [Oi] X [Cs] ^ ≤ 4E86 (Condition 2; represents power)

 A region that satisfies the above condition exists in the substrate.

Here, the interstitial oxygen concentration [Oi] represents the concentration of oxygen located between the lattice points of the silicon crystal, and the substitutional position carbon concentration [Cs] It represents the concentration of carbon substituted for lattice points.

In addition to the above conditions, the polycrystalline silicon substrate of the present invention has a nitrogen concentration measured by Fourier transform infrared spectroscopy or secondary ion mass spectrometry as [N] [ _a tom _S / _C m ³ ]. When

 [N] ≤ 4E15 (Condition 3)

 A region that satisfies the above condition exists in the substrate.

[0013] The "condition 1" is based on the fact that the inventor has found that there is a correlation between dangling bonds appearing on the cleavage plane of the substrate, solar cell characteristics, and impurity concentration. That is, the spin quantum number of dangling bonds appearing on the cleavage plane of the substrate s = iZ

Specifies the range of electron spin density Nspin in state 2. A polycrystalline silicon substrate that satisfies this condition 1 has a low recombination level density because its electron spin density is lower than the threshold value 3.5E14. Therefore, it becomes a board | substrate with high photoelectric conversion efficiency with the quality of a board | substrate. As a result, a low-cost, resource-saving and highly efficient polycrystalline silicon solar cell can be manufactured.

 The “condition 2” is a necessary condition for realizing the “condition 1”.

 The “Condition 3” is a more preferable condition for obtaining a higher quality substrate. The polycrystalline silicon substrate may be cut from an ingot.

 In this case, it is preferable that the polycrystalline silicon substrate satisfies the above conditions in at least a part of the region excluding the substrate end lcm width region. Further, the solidification rate of the ingot is 15 to 80%. It is preferred that the above conditions are satisfied!

[0015] Excluding the substrate edge lcm width region, the substrate edge region includes a solidified region in the initial stage of solidification, and the influence of solid-phase diffusion of impurities (thermal diffusion after solidification) of the vertical inner wall force Therefore, the influence of factors other than the quality degradation factor that is the subject of the present invention is large, and this is a force that may not be appropriate as the target region where the effect of the present invention is expected. Therefore, if the substrate quality is evaluated by excluding the lcm width region at the edge of the substrate, these factors outside of symmetry are almost eliminated. Since the influence can be ignored, it is suitable for correctly evaluating the effect of the present invention.

 [0016] In addition, in the region where the solidification rate of the ingot is less than 15%, the crystal quality is very low due to the large amount of oxygen precipitates generated and the influence of impurity diffusion from the bottom of the vertical mold. If the solidification rate exceeds 80%, the influence of the prayers of various impurities will increase rapidly, and the crystal quality will be extremely lowered. Therefore, it is suitable for correctly evaluating the effect of the present invention in a region where the solidification rate of the ingot is 15 to 80%.

 [0017] The polycrystalline silicon ingot of the present invention is an ingot that satisfies the above "condition 1" with respect to the impurity concentration in the polycrystalline silicon substrate.

 Furthermore, the polycrystalline silicon ingot of the present invention may be such that the “condition 2” or the “condition 3” is further satisfied in addition to the “condition 1”.

 In the method for producing a polycrystalline silicon substrate of the present invention, silicon is poured into a crucible, and silicon is melted while flowing Ar at a flow rate such that the gas residence time in the crucible is 25 sec or less. In this method, the molten silicon is transferred to a mold, the silicon is solidified and cooled to produce an ingot, and the produced ingot is cut out to obtain a polycrystalline silicon substrate.

 [0018] More preferably, Ar is flowed at a flow rate such that the gas residence time in the crucible is 19 sec or less.

The upper limit of the gas residence time _τ gas is actually limited by increasing the Ar gas cost by increasing τ gas, generating dust in the furnace, and the like.

 Furthermore, the present invention can also be applied to the in-mold melting and solidification method in which the silicon is melted in the above-mentioned mold without using a crucible and then solidified and cooled.

[0019] By flowing Ar under such conditions that the gas residence time is 25 sec or less, the following effects can be obtained. In conventional polycrystalline silicon fabrication methods, the ratio of the contact area of the furnace atmosphere to the amount of Si melt is large, so CO gas contamination is likely to occur. Therefore, the silicon is melted while flowing Ar at a flow rate such that the gas residence time in the crucible is 25 sec or less. As a result, it is possible to eliminate the contact of the CO gas existing in the furnace with the molten silicon at the Ar pressure during fabrication, and to reduce the carbon contamination of the silicon. Therefore, in order to easily obtain a polycrystalline silicon substrate that satisfies the above "condition 1" The necessary conditions can be realized.

 [0020] At the time of solidification / cooling of the silicon, it is preferable to forcibly solidify the side force by increasing heat removal from the side surface of the mold at the initial stage of solidification. If solidification from the side is forcibly performed, a thin initial solidified layer can be preferentially grown on the side surface of the vertical inner wall at the initial stage of the solidification process. This initial solidified layer acts as a barrier to prevent SiN from dissolving into the molten silicon, and can suppress excessive doping of nitrogen in the silicon ingot. When cutting the substrate from the ingot, the outer periphery of the ingot (the initial solidification part) that was in contact with the inner wall surface of the saddle must be cut as the end material.

 [0021] By the above method, [C] which degrades the substrate quality can be sufficiently reduced. [N] can also be controlled below a predetermined value. In addition, the device efficiency can be improved at the same time.

 The photoelectric conversion element of the present invention is a photoelectric conversion element using the polycrystalline silicon substrate of the present invention. This photoelectric conversion element can be expected to be thinner and have higher element efficiency than conventional photoelectric conversion elements.

 In addition, the photoelectric conversion module of the present invention is formed by electrically connecting the plurality of photoelectric conversion elements of the present invention in series or in parallel. Therefore, the photoelectric conversion module of the present invention is low in cost and has high characteristics. Become.

 The above-described or other advantages, features, and effects of the present invention will be made clear by the following description of embodiments with reference to the accompanying drawings.

 Brief Description of Drawings

 FIG. 1 is a cross-sectional view showing an example of the structure of a solar cell element 11 using a polycrystalline silicon substrate according to the present invention.

 FIG. 2 is a top view showing an example of an electrode shape viewed from the light receiving surface side of solar cell element 11.

 FIG. 3 is a top view showing an example of an electrode shape as seen from the non-light-receiving surface side force of solar cell element 11.

 [FIG. 4] FIGS. 4 (a) to 4 (d) are process diagrams for explaining the process from the start of the dissolution of silicon in the crucible to the transfer of the melt into a bowl.

FIG. 5 is a cross-sectional view showing the structure of a solar cell module. FIG. 6 is a top view of the solar cell module viewed from the light receiving surface side.

 1 Surface electrode

 la passbar electrode

 lb finger electrode

 3 Semiconductor area

 4 Reverse conductivity type region

 5 p-type Balta region

 6 Anti-reflective coating

7 p ⁺ type region

 8 Back collector

 9 Back output electrode

 11 Solar cell element

 12 Crucible body

 13 Crucible lid

 21 Vertical body

 24 Cold plate

 41 Wiring material

 42 Transparent material

 43 Back nife

 44 Front side filler

 45 Back side filler

 46 Output extraction wiring

 47 Terminal box

 48 frames

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a cross-sectional view showing an example of the structure of a solar cell element 11 using a polycrystalline silicon substrate according to the present invention. 2 and 3 are diagrams showing an example of the electrode shape of the solar cell element 11. FIG. 2 is a top view when FIG. 1 is viewed from the light receiving surface side, and FIG. 3 is the non-light receiving surface side of FIG. It is a bottom view of power. Hereinafter, the structure of the solar cell element 11 will be briefly described.

The p-type silicon substrate has a thin plate shape with a thickness of 350 m or less, and includes a p-type bulk region 5 as shown in FIG. On the light incident surface side of the p-type silicon substrate, P (phosphorus) atoms and the like are diffused at a high concentration to form an n-type reverse conductivity type region 4, and a pn junction between the p-type silicon region Is formed. The thickness of the reverse conductivity type region 4 is usually about 0.2 to 0.5 m. A powerful antireflection film 6 such as a silicon nitride film or an oxide silicon film is provided on the semiconductor on the light incident surface side. On the other side of the light incident surface, a P + type region 7 containing a large amount of p-type semiconductor impurities such as aluminum is provided. This p + type region 7 is also called a BSF (Back Surface Field) region and plays a role in reducing the rate at which photogenerated electron carriers reach the back collector 8 and lose recombination. Thereby, the photocurrent ¾sc is improved. In addition, since the minority carrier (electron) density is reduced in the p + type region 7, the diode current amount (dark current amount) in the region in contact with the P + type region 7 and the back collector electrode 8 is reduced. The open circuit voltage Voc is improved.

[0027] On the light incident surface side, a surface collecting electrode 1 whose main component is a metal material such as silver is provided.

 On the back side, a back side collecting electrode 8 mainly composed of aluminum or the like is provided. Further, a back surface output electrode 9 for collecting current from the back surface collecting electrode 8 is provided.

 As shown in FIG. 2, the front electrode 1 generally has a finger electrode lb (branch electrode) having a narrow line width and a bus bar electrode la (having a large line width to which at least one end of the finger electrode lb is connected. Stem electrode). In order to reduce the power loss at the collector electrode 1 as much as possible, a metal material is used for the collector electrode 1. It is desirable to use Ag paste based on silver (Ag), which has a low resistivity, as the metal. Usually, it is applied and fired by screen printing to form an electrode.

When light is incident from the side of the antireflection film 6, which is the light incident surface side of the solar cell element 11, in the semiconductor region 3 composed of the reverse conductivity type region 4, the p-type butter region 5, and the p + type region 7. Then, absorption and photoelectric conversion are performed to generate an electron-hole pair (electron carrier and hole carrier). Due to the electron carriers and hole carriers (photogenerated carriers) of this photoexcitation source, Photoelectric power is generated between the substantially linear collector electrode 1 provided on the side and the back electrodes 8 and 9 provided on the back side, and the generated photogenerated carriers are collected by these electrodes and output. Guided to the terminal. In addition, a dark current that is a diode current flows in the opposite direction to the photocurrent in accordance with the photovoltaic force.

 Next, a polycrystalline silicon ingot forging process for obtaining a polycrystalline silicon substrate of the present invention will be described.

 4 (a) to 4 (d) are schematic process diagrams for explaining the process from the start of the dissolution of silicon in the crucible to the transfer of the melt into a bowl.

 First, a silicon raw material is prepared. It is desirable to use a polysilicon material with a low impurity concentration as the silicon material, but in addition to this, for example, off-grade silicon called top and tail, which is generated during the production of CZ single crystal silicon ingots, or Residual silicon remaining in the crucible can also be used. However, if there is a problem of impurity contamination when off-grade silicon or residual silicon is used alone, an appropriate amount of polysilicon raw material is blended.

[0030] Hereinafter, the description will be continued with an example in which about 80 kg of Si raw material is prepared.

 Next, the silicon raw material is put into the crucible 12. Fig. 4 (a) shows a state in which the silicon raw material is put in the crucible 12. As the crucible 12, a quartz crucible generally used in the CZ method can be used.

 FIG. 4 (b) shows a state in which the raw silicon in the crucible 12 is melted by heating in a melting furnace. The inside of the furnace is Ar gas atmosphere, Ar flow rate is adjusted in the range of 10 ~: LOOLZmin, Ar gas pressure is in the range of lkPa ~: LOOkPa (atmospheric pressure).

[0031] In the present embodiment, when a quartz crucible is used, the oxygen concentration in the Si melt at the main melting stage is an extremely high value of about lE18 to 2E18 [atoms / cm ³ ] which is close to the saturation solubility value. ing. If the inner wall of the quartz crucible is coated with a non-acidic material such as SiN, the oxygen concentration in the Si melt will be smaller than this.

What should be noted in the silicon melting stage is carbon contamination of the Si melt by CO gas in the furnace. When the carbon concentration in the Si melt increases and reaches a certain value, SiC crystallizes in the melt, and if this is incorporated into the crystal during Si solidification, it acts as a structural defect, so the substrate Si quality is improved. Reduce. In addition, part of the c element taken into the crystalline Si without crystallizing is precipitated as SiC in the crystalline Si due to a decrease in the solid solubility in the crystalline Si accompanying cooling of the crystalline Si ingot. In this case as well, the crystalline Si quality is similarly reduced. In addition, SiC or solid-solution C also acts as oxygen precipitation nuclei, so that promoting the oxygen precipitation may also reduce the crystalline Si quality.

[0032] From the above, it is necessary to reduce carbon contamination of the Si melt as much as possible.

 In order to reduce carbon contamination of Si melt, three factors are important: (1) reduction of CO partial pressure, (2) reduction of dissolution time, and (3) timing of introduction of dopant material. is there. The reduction of the CO partial pressure in (1) can be realized by increasing the flow rate of Ar, which is the atmosphere, by increasing the gas exhaust speed in the furnace. At the same time, it is also effective to use a closed crucible with a lid 13 as shown in FIG. 4 (b). This is because sealing the crucible with the lid 13 prevents CO contamination from the furnace atmosphere and reduces the CO partial pressure in the sealed space in contact with the melt.

 [0033] Although not shown, the lid 13 of the closed crucible in Fig. 4 (b) is actually provided with a small hole for flowing Ar gas into the crucible. There is also a gap between the crucible 12 and the lid 13 for flowing Ar gas.

 Here, if the Ar flow rate is increased, it is of course important to sufficiently prepare the general conditions for reducing the partial pressure of CO gas, on the premise of obtaining a CO gas contamination reduction effect using a sealed crucible. That is, reducing the amount of residual gas (adsorbed gas) in the furnace, reducing the amount of air leakage into the furnace, reducing the amount of CO gas generated in the furnace, increasing the gas exhaust speed in the furnace, and optimizing the Ar gas flow path in the furnace It is important to take comprehensive measures such as optimization, optimization of the placement of carbon material heaters and insulation materials.

 [0034] Examples of the in-furnace CO gas generation source include a mechanism in which CO gas is generated when a heater or a heat insulating member made of a carbon material reacts with an oxygen-based gas. In particular,

 C material + air leak component (O H 0) → CO †,

 twenty two

 C material + SiO → SiC (or Si) + CO †

Is mentioned. Here, the latter is generated during melting and is generated by a large amount of SiO gas, and is an unavoidable reaction in a melting process using a quartz crucible.

In order to reduce the reaction between the former carbon material and oxygen-based gas, SiC coating on the carbon material surface may be effective (T. Fukuda et al: J. Electrochem. Soc, vol.141, No. .8, Augus t 1994, p.2216) ₀

 [0036] Although the increase in the Ar gas exhaust speed in the furnace can be realized by increasing the capacity of the exhaust pump, the pump exhaust capacity is limited, so in this case the effective volume in the furnace is limited. It is effective to reduce as much as possible (volume of the region where the gas in the furnace actually exists). This time,

 τ gas = Ar gas mol number in the furnace ZAr gas flow rate [molZsec]

 (However, the number of mols of Ar gas in the furnace is proportional to (effective volume in the furnace x Ar gas density in the furnace)). Is possible. Here, the Ar gas density in the furnace is an amount obtained by n / V = P / k T from the gas state equation PV = nkT. Note that it is somewhat time-consuming to estimate the actual effective volume in the furnace, so the design volume in the furnace (the internal space volume of the furnace itself) may be taken instead. At this time, the meaning of gas as a guide is also effective.

 [0037] Therefore, when the volume inside the furnace is taken as the volume inside the furnace, τ gas required to effectively reduce CO gas contamination is maximum 25 sec or less, preferably 19 sec or less, based on past experience. More desirably, it is 15 sec or less.

However, this condition can be relaxed when using a closed crucible. For example, if the effective volume in the furnace is lm ^{3 and} the effective volume of the closed crucible (the volume of the space between the lid and the melt) is (0.5 m) ³ = 0.125 m ³ , the same τ gas is given. The flow rate will be 0.125 times.

 [0038] The Ar gas flow path is also a very important design element. Basically, fresh Ar gas is sprayed on the surface of the Si melt, and there is no component that flows back, so that an L gas flow portion is formed in a laminar flow in which the Ar gas flow is aligned in one direction. Design the internal structure of the furnace so that it leads to the exhaust port.

In addition, it is necessary to find the optimum conditions for the arrangement of the carbon material heater and the heat insulating material from the relationship between the position of the silicon melt surface and the Ar flow path. [0039] Note that if this sealed crucible is employed, carbon contamination can be efficiently and extremely reduced with a small Ar flow rate without unnecessarily increasing the Ar flow rate.

 Next, regarding the shortening of the melting time of (2) above, by efficiently applying the thermal energy input for melting to the silicon raw material, the time from the start of melting to the complete melting is shortened, The amount of CO contamination can be reduced.

 [0040] Specifically, measures such as increasing the output of the heater for melting, optimizing the heater arrangement, optimizing the arrangement of the heat insulating material in the furnace, and preheating the members in the melting furnace if necessary. Can be realized. For example, in the dissolution of 80 kg of Si raw material, complete dissolution can usually be achieved with a heating time of about 2 to 4 hours.

 Finally, it is desirable that the dopant material (3) is introduced into the melt as much as possible in the final stage of the melting process (immediately before the pouring process). The C contamination of the melt tends to be reduced by delaying the introduction of the dopant material as much as possible.

 [0041] The number of minutes before the pouring of the dopant is specifically determined in consideration of the reference time T during which the dopant is sufficiently distributed inside the molten silicon. This reference time T can be determined as follows based on the amount of silicon and the convection velocity of the silicon melt.

 Differences in weight (cool → heavy, heat → light) occur depending on the cooling state of the silicon melt, which causes convection. At this time, the reference time T is obtained by dividing the third root of the weight (volume X density) of silicon by the convection velocity for the following reason.

[0042] For example, the convection velocity of the silicon melt is about lcmZs to lmmZs. Here, for example, silicon with a weight M = 80 kg corresponds to a volume (V = L ³ ) of about 30 cm × 30 cm × 30 cm in terms of a side length L cube (M = p−V; is the density of Si). In other words, it takes 0.5 to 5 minutes at the convection rate for the melt to move 30 cm (dopant moves to the end of one side). It takes 1.5 to 15 minutes, which is three times as long as it is assumed that it is enough to move one side of the melt by convection about 3 times to mix well.

[0043] If the approximate time T is expressed by an equation, (T: time (minutes), M: silicon content (kg), coefficient a: 0.35 to 3.5).

 In this way, by delaying the injection for T minutes before pouring, the CO gas contamination of the silicon melt can be further reduced compared to the case without applying the dopant delay injection method.

[0044] The doping amount is adjusted so that the doping element concentration in the solidified ingot is about IE 16 to IE 17 [atoms / cm ³ ] so as to maximize the solar cell characteristics described later (in this case, The specific resistance of the substrate obtained is about 0.2 to 2 Ω'cm).

Specifically, the doping amount must be adjusted in consideration of the segregation coefficient (distribution coefficient) for each doping element. For example, when B (boron) is taken as an example, the segregation coefficient of B is about 0. Therefore, if the B concentration in the initial solidified part (bottom of the ingot) of the solidified ingot is 1 E16 [atoms / cm ³ ], the B concentration in the melt is 1E16 + 0.8 = 1. 25E 16 Doping amount should be determined to be [atoms / cm ³ ]!

[0045] In order to maximize the efficiency of the solar cell, it is necessary to control the p-type or n-type by introducing an appropriate doping element and the doping concentration, as is well known.

 At this time, it is desirable to use B (boron) or Ga (gallium) as the p-type doping element and P (phosphorus) as the n-type doping element.

 Thereafter, as shown in FIG. 4 (d), the silicon melt that has been completely melted in the melting process is poured as quickly as possible into a vertical mold installed in the solidification furnace to solidify the silicon melt. (Cast method). At this time, the inside of the furnace should be in an Ar gas atmosphere, the Ar flow rate should be adjusted in the range of 10 to: L00LZmin, and the Ar gas pressure in the range of lkPa to 100kPa (atmospheric pressure).

[0046] The mold 21 can be made of a carbon-based material such as a graphite material or a carbon material, or can be made of a material such as quartz, quartz glass, or ceramic. A mold release material is applied in advance to the inner wall of the mold 21 so that the ingot can be easily removed from the mold after solidification and cooling. At this time, the release material also serves to prevent contact reaction between the cage material and the silicon melt, and prevents impurities in the cage material from being mixed into the silicon melt. As the mold release material, SiN powder can be used.

2 Mixing an appropriate amount can increase the strength of the release material and effectively prevent the release material from peeling or falling during solidification. In addition, the release material is applied to the vertical inner wall by mixing the release material powder raw material and an organic material such as PVA at an appropriate mixing ratio to make it viscous. Line in state!加熱 After application, heat treatment is performed to remove organic material components.

 Next, the silicon melt is solidified. The solidification is performed so that the bottom force of the bowl 21 is solidified upward and in one direction (in order to enhance the one-directional solidification property). At this time, the heat flow balance of the entire vertical silicon should be adjusted. Specifically, solidification from the bottom of the bowl

The cooling plate 24 is promoted by bringing it into contact with the bottom of the vertical mold, and heat removal from the silicon melt head due to thermal radiation is suppressed. Suppression of heat removal from the latter head can be adjusted by improving the heat insulation in the furnace at the top of the silicon melt, or by applying heat with a heater if necessary.

 [0048] In addition, regarding the shortening of the solidification time in this saddle type (the amount of carbon contamination is reduced if the time in which the melt exists is short as in the case of melting, it is desirable to solidify as short as possible) In order to achieve efficient heat removal from the bottom of the vertical plate, the contact area of the cold plate Z-type is increased (for example, the contact surface has a concave and convex shape), and the thickness of the cooling plate is reduced. Measures such as increasing the coolant flow rate, thinning the bottom material of the saddle and increasing the thermal conductivity (using high-density graphite, etc.) and, in some cases, improving the heat removal capability even if the unidirectional solidification is impaired. In order to increase the temperature, it is possible to take measures to cool from the vertical side as well as the vertical bottom.

 [0049] Further, if forging silicon ingots having the same weight, it is effective to increase the heat removal efficiency by making the ingot height as low as possible and making the saddle bottom area as large as possible. In order to increase the thermal conductivity of the release material, it is important to make the release material as thin as possible and to apply it in a dense state with a low porosity.

 Heat removal from the vertical side wall is effective when there is a lot of impurity contamination from the vertical mold through the mold release material or the mold release material. In other words, in the initial stage of the solidification process, the side wall force is intentionally removed to forcibly solidify the Si melt in the region in contact with the vertical side wall and solidify in contact with the inner surface of the vertical side wall. The silicon layer can function as a blocking layer for impurity diffusion with a release material force.

[0050] The heat removal of the saddle type side wall force is performed in anticipation that the crystalline silicon layer in the region in contact with the inside surface of the saddle type side wall is cut and removed as an end material during the subsequent ingot cutting. By removing heat with this saddle-shaped side wall force, the Si melt mainly using SiN mold release material The increase in the concentration of nitrogen (N) impurities in the silicon ingot due to the elution of nitrogen (N) into the inside can be effectively suppressed. In addition, elution of other impurities (such as iron (Fe), etc.) in the release material into the melt can be effectively suppressed.

 [0051] Note that the improvement in heat removal from the vertical side wall can be achieved by weakening the output of the side heater HI (see Fig. 4 (d)) or by improving the vertical side wall of the vertical wall (for example, carbon-based material). This can be achieved by selecting so-called CCM materials or graphite materials.

 The problem in the solidification process is the carbon contamination of the Si melt due to the CO gas in the furnace described in the melting stage. In order to reduce this carbon contamination, it is important to increase the gas exhaust speed to reduce the CO partial pressure in the furnace as much as possible and to complete the solidification in as short a time as possible, as described in the melting process. is there. Of course, it is also necessary to prepare the general conditions for reducing the partial pressure of CO gas described in the melting process.

 [0052] Regarding the reduction of the CO gas partial pressure, more preferably, as shown in Fig. 4 (b), a closed saddle type that can effectively reduce and block the contact between the CO gas and the Si melt. Use it! / ヽ. If silicon is solidified using this closed saddle type, the effect of reducing the CO partial pressure in the crucible can be obtained, so contact between the melt and CO gas can be reduced without increasing the Ar flow rate unnecessarily. wear. Therefore, carbon contamination can be reduced efficiently and extremely with a small Ar flow rate.

 [0053] Ideally, it is desirable that oxygen can be controlled to a certain value. This is because if the oxygen concentration is too high, the amount of oxygen precipitates generated will increase the crystal quality, while if the oxygen concentration is too low, the crystal strength (the yield stress value at which dislocations will occur) will decrease. Dislocations are likely to occur due to the thermal stress that occurs during the solidification process, and as a result, subgrain boundaries (subgrain boundaries) are frequently generated, which is also a force that degrades the crystal quality. In practice, it is difficult to control the oxygen concentration to an appropriate value unless a special method is taken. Normally, due to the phenomenon described below, the oxygen concentration is unilaterally (indexed) from the bottom of the ingot to the head. Shows a decreasing concentration profile (in a functionally close fashion).

[0054] Since the Si melt in the melting process is in contact with a crucible having a quartz force, the oxygen concentration in the melt is about lE18 to 2E18 [atoms / cm ³ ] close to the saturation value. In contrast, the silicon melt that is in the solidification process after being poured into the bowl is applied to the inner wall of the bowl. It is in contact with the clothed SiN release material. For this reason, the Si melt in the solidification process is substantially not supplied with oxygen even by the mold release material. In other words, the supply of oxygen to the S job fluid is almost cut off. On the other hand, SiO gas evaporates from the surface of silicon melt very rapidly. For this reason, in the solidification stage, the oxygen concentration of the Si melt decreases exponentially with time. For example, when is unidirectional solidification the Si melt 80kg in about 8 hours, was present at a concentration of about the initial silicon melt _{^{1E18 / C m 3 [a tom}} S / C m 3] immediately after tapping The concentration of oxygen decreases as early as 2 to 4E17 / cm ³ [atoms / cm ³ ] at a solidification rate of about 20%, and 4 to 8E 16 / cm ³ [atoms / cm at a solidification rate of about 40%. ³ ] Concentration drops to about

[0055] As described above, since the reduction of the oxygen concentration in the melt is caused by the evaporation of SiO gas with the surface strength of the Si melt, the pressure reduction of the atmospheric gas (Ar gas) promotes the evaporation of SiO and melts the melt. Reduce the oxygen concentration in the liquid. As described above, this lowers the strength (yield stress) of the crystal, so unless the measures to suppress the adverse effects are taken, it is preferable to reduce the atmospheric gas pressure.

 [0056] In the region where the solidification rate is 0 to 10%, the amount of generated oxygen precipitates is large, and the crystal quality is very low due to the influence of impurity diffusion from the bottom of the bowl. When the solidification rate is 85% or more, the influence of the various prayers of impurities rapidly increases, and the crystal quality is extremely lowered. In addition, the characteristics of elements using substrates in these regions are generally very low.

 For this reason, the effects of the present invention are difficult to achieve (the influence of other crystal quality lowering factors is great). These areas should be excluded from the scope of the present invention. Specifically, an area having a solidification rate of 15 to 80% may be an object of the present invention.

 As described above, silicon is completely solidified, and after a necessary cooling process, the mold is removed and the ingot is taken out.

 Next, an element forming process for forming a solar cell element using the polycrystalline silicon substrate of the present invention will be described.

First, as a one-conductivity type semiconductor substrate, a polycrystalline silicon substrate is prepared by slicing a p-type polycrystalline silicon ingot doped with B by about lE16 to lE17 [atoms / cm ³ ] in the polycrystalline silicon fabrication process. Here, the substrate thickness should be 300 / zm or less, more preferably 2 50 μm or less, more preferably 150 μm or less.

[0058] Thereafter, in order to remove the mechanical damage layer and the contamination layer on the surface layer portion of the substrate due to the slicing of the substrate, the surface layer portions on the front surface side and the back surface side of this substrate are made of NaOH, KOH, or hydrofluoric acid and nitric acid. Etch about 10-20 m each with a mixed solution, and then clean with pure water.

 Next, an uneven (roughened) structure having a light reflectance reduction function is formed on the surface side of the substrate that becomes the light incident surface (not shown). In forming this concavo-convex structure, an anisotropic wet etching method using an alkaline solution such as NaOH used for removing the substrate surface layer portion described above can be applied. In the case of a substrate, the crystal plane orientation in the substrate plane varies randomly from crystal grain to crystal grain, so that a good concavo-convex structure that effectively reduces the light reflectivity over the entire substrate area must be uniformly formed. It is difficult. In this case, for example, by performing gas etching by the RIE (Reactive Ion Etching) method or the like, it is relatively easy to form a good uneven structure uniformly over the entire substrate.

 [0059] It should be noted that the same effect can be obtained even when the heat treatment step and the laser recrystallization step for forming the low oxygen concentration region on the substrate surface layer described above are applied after the present concavo-convex structure forming process.

Next, an n-type reverse conductivity type region 4 is formed. It is desirable to use P (phosphorus) as the n-type doping element. The doping concentration is about lE18 to 5E21 [atoms / cm ³ ], and n + type with a sheet resistance of about ³⁰ to 300Ω. As a result, a pn junction is formed between the p-type butter region described above. Here, the pn junction is composed of a depletion region extending toward the p-type butter region and a depletion region extending toward the reverse conductivity region 4.

[0060] As a method of manufacturing the reverse conductivity type region 4, POC1 (phosphorus oxychloride) in a gas state is used as a diffusion source.

 Three

Using the thermal diffusion method described above, the doping element (P) is diffused in the surface layer portion of the p-type silicon substrate at a temperature of about 700 to L000 ° C. At this time, the thickness of the diffusion layer is about 0.2 to 0.5 m, and this can be realized by forming a desired doping profile file by adjusting the diffusion temperature and diffusion time. The sheet resistance value is preferably about 45 to about L00 Ω, more preferably about 65 to 90 Ω. [0061] In the above thermal diffusion method using a normal gas diffusion source, a diffusion region is also formed on the surface opposite to the target surface, but this portion is etched away later. I hope. At this time, the reverse conductivity type region 4 other than the surface side of the substrate is removed by applying a resist film on the surface side of the silicon substrate, etching away using a mixed solution of hydrofluoric acid and nitric acid, and then resist film. By removing. As will be described later, when the P + type region 7 (BSF region) on the back surface is formed with aluminum paste, the p-type dopant aluminum can be diffused to a sufficient depth at a sufficient concentration. The influence of the already diffused shallow n-type diffusion layer can be neglected, and it is not necessary to remove the n-type diffusion layer formed on the back side.

 Note that the method of forming the reverse conductivity type region 4 is not limited to the thermal diffusion method. For example, by using a thin film technology and conditions, a crystalline silicon film including a hydrogenated amorphous silicon film or a microcrystalline silicon film is used. Or the like may be formed at a substrate temperature of about 400 ° C. or lower.

In this way, when the reverse conductivity type region 4 is formed at a low temperature using thin film technology instead of the thermal diffusion method, the diffusion of oxygen to the substrate side in this process can be ignored. plate oxygen concentration is permitted to the extent the maximum _{lE18 [a tom S / C m} 3], also substrate table layer a heat treatment process or laser re-crystallization process described above when the oxygen concentration in the substrate is higher than this even when applied to parts, the oxygen concentration within the range of the depletion region of the pn junction is formed _{lE18 [a tom S / C m} 3] follows if possible Yogu pn junction formed before oxygen concentration required value of the substrate state Can be greatly relaxed. However, as long as the polycrystalline silicon substrate of the present invention is used, the upper limit value of oxygen concentration described here is not essential! /.

 [0063] When the reverse conductivity type region 4 is formed using thin film technology, the formation order is determined so that the process temperature is lower and the process temperature is lower in consideration of the temperature of each process described below. It is necessary to

Here, when the reverse conductivity type region 4 is formed using a hydrogenated amorphous silicon film, the thickness is 50 nm or less, preferably 20 nm or less, and when it is formed using a crystalline silicon film, the thickness is 500 nm or less, preferably 200 nm or less. When the reverse conductivity type region 4 is formed by the above thin film technology, if an i type silicon region (not shown) is formed with a thickness of 20 nm or less between the p type butter region and the reverse conductivity type region 4, the characteristics are improved. It is effective for. Next, the antireflection film 6 is formed. Anti-reflective coating 6 materials include Si N film, TiO film, S

 3 4 2 An iO film, MgO film, ITO film, SnO film, ZnO film, or the like can be used. Its thickness is

twenty two

 Appropriately selected according to the material to realize the non-reflection condition for the incident light (If the refractive index of the material is n and the wavelength of the spectral region to be made non-reflection is selected, (λ Zn) Z4 = d is the optimum anti-reflection film 6 Film thickness). For example, in the case of a commonly used Si N film (n = about 2)

 3 4

 If the wavelength to be made non-reflective is 600nm considering the solar spectrum characteristics, the film thickness should be about 75nm.

[0065] The antireflection film 6 is manufactured by PECVD, vapor deposition, sputtering, etc., and when the pn junction is formed by thermal diffusion, the temperature is about 400-500 ° C, and it is formed by thin film technology. In this case, it is formed at a temperature of 400 ° C or less. The antireflection film 6 is patterned with a predetermined pattern in order to form the surface collecting electrode 1 when the surface collecting electrode 1 is not formed by the fire through method described later. As a patterning method, an etching method (wet or dry) used for a mask such as a resist, or a method in which a mask is formed in advance when the antireflection film 6 is formed and then removed after the formation of the antireflection film 6 is used. Can do. On the other hand, when the so-called fire-through method is used in which the electrode material of the collector electrode 1 is directly applied and baked on the antireflection film 6 to electrically contact the collector electrode 1 and the reverse conductivity type region 4 There is no need for Jung. This Si N film is surface passivated during formation.

 3 4

 The Yon effect and the subsequent heat treatment have a Balta passivation effect and, together with an antireflection function, have the effect of improving the electrical characteristics of the solar cell element.

Next, a p + type region (BSF region) is formed. Specifically, an aluminum paste in which aluminum powder, organic vehicle, and glass frit are added in a paste form by adding 10 to 30 parts by weight and 0.1 to 5 parts by weight with respect to 100 parts by weight of aluminum, for example, Print by screen printing, and after drying, heat-treat at 600-850 ° C for several seconds to several tens of minutes. This forms a P + type region 7 (BSF region) that prevents aluminum from diffusing into the silicon substrate and recombining the carriers generated on the back surface. The aluminum dopant concentration in p + type region 7 is lE18 ~ 5E21 [at. ms / cm ³ ].

[0067] At this time, among the metal components in the paste, those not used for forming the p + type region 7 but remaining on the p + type region 7 can be used as a part of the back collector electrode 8 as they are. ,this In this case, it is not necessary to remove the remaining components with hydrochloric acid. In this specification, this

Although it is assumed that the back surface collecting electrode 8 whose main component is aluminum remaining on the P + type region 7 is present, an alternative electrode material may be formed when it is removed. As this alternative electrode material, it is desirable to use a silver paste that will be the back collector 8 described later in order to increase the reflectance of long wavelength light reaching the back. B (polon) can also be used as the p-type doping element.

[0068] Further, when the p + type region 7 is formed by using the printing and baking method, as already described, n is formed on the back surface side of the substrate simultaneously with the formation of the reverse conductivity type region 4 on the substrate surface side. There is no need to remove the mold area.

 Further, the p + -type region 7 (back surface side) can be formed by a thermal diffusion method using a gas instead of the printing and baking method. In this case, using BBr as the diffusion source, temperature 800 ~: L 100 ° C

 Three

Form with degree. At this time, diffusion noria such as an oxide film is preliminarily formed in the reverse conductivity type region 4 (surface side) already formed. Further, when the antireflection film 6 is damaged by this step, this step can be performed before the antireflection film 6 formation step. The doping element concentration is about lE18 to 5E21 [atoms / cm ³ ]. As a result, a low-high junction can be formed between the p-type Balta region and the P + type region.

[0069] Note that the method for forming the p + -type region is not limited to the printing and baking method or the thermal diffusion method using a gas. For example, a hydrogenated amorphous silicon film using a thin film technique includes a microcrystalline silicon phase. A crystalline silicon film or the like may be formed at a substrate temperature of about 400 ° C. or lower. In particular, if the pn junction is formed using thin film technology, the P + region is also formed using thin film technology. At this time, the film thickness is about 10 to 200 nm. At this time, if an i-type silicon region (not shown) having a thickness of 20 nm or less is formed between the p + type region and the p-type bulk region, it is effective for improving the characteristics. However, when forming using thin film technology, it is desirable to determine the order of formation so that the temperature of each subsequent process is lower and the process temperature is lower in consideration of the temperature of each process described below.

Next, a surface paste electrode 1 and a back surface output electrode 9 are formed by applying and baking a silver paste on the front surface and the back surface of the substrate. These are pastes of silver powder, organic vehicle and glass frit added to 10 to 30 parts by weight and 0.1 to 5 parts by weight, respectively, with respect to 100 parts by weight of silver. The silver paste thus formed is printed on the printed surface by, for example, printing by screen printing and drying, followed by baking at 600 to 800 ° C. for several seconds to several minutes.

[0071] Although it is desirable in terms of cost to fire the collector electrode 1 and the back surface output electrode 9 simultaneously (in one time), it is fired in two times, particularly because of the electrode strength characteristics of the back surface electrode. In some cases, it may be better (for example, the surface electrode 1 is first printed and fired, and then the back surface output electrode 9 is printed and fired).

 In addition to the printing and baking method, the manufacturing method can use vacuum film forming methods such as sputtering and vapor deposition. Particularly in the printing and baking method using paste, the antireflection film 6 is formed by the so-called fire through method. Without patterning, the metal-containing paste that will become the collector electrode 1 is printed directly on the antireflection film 6 and fired to make electrical contact between the collector electrode 1 and the reverse conductivity type region 4. It is very effective in reducing manufacturing costs. The surface collection electrode 1 may be formed prior to the formation of the P + type region 7 on the back surface side.

 [0072] Further, in order to particularly increase the bonding strength between the electrode and the semiconductor region, the paste printing method includes a slight amount of oxidic acid components such as TiO in the paste, and a vacuum film forming method.

 2

 Then, it is good to insert a metal layer mainly composed of Ti at the interface between the electrode and the semiconductor region. In the case of the back side electrode, it is desirable to suppress the reduction in reflectivity due to the insertion of the metal layer with the thickness of the Ti main component metal layer being 5 nm or less. It is desirable that the back collector 8 be formed on the entire back surface of the substrate in order to increase the reflectance of long-wavelength light reaching the back surface.

 [0073] Since the back collector electrode 8 and the back output electrode 9 overlap with each other and become thick, cracks and peels are not easily generated. Therefore, after forming the back output electrode 9 for output extraction, the back collector electrode 8 It is desirable to form the electrode 9 in such a state that it can conduct electricity so as not to cover as much as possible. Further, the order of forming the back surface output electrode 9 and the back surface collecting electrode 8 may be reversed. Further, the back side electrode may not have the above-described structure, and may have a structure composed of a bus bar portion and a finger portion having silver as a main component, similar to the surface collection electrode 1.

[0074] Even when the reverse conductivity type region 4 and the p + type region 7 are formed by using thin film technology, the front collector electrode 1, the back collector electrode 8, and the back output electrode 9 are formed by a printing method, a sputtering method, Force that can be formed using vapor deposition, etc.Process temperature should be 400 ° C or less in consideration of damage to the thin film layer. To do.

 Finally, a solder region is formed on the front electrode 1 and the back electrode by solder dipping as necessary (not shown). Note that the solder dipping process is omitted when using a solderless electrode that does not use solder material.

 As described above, the high-quality polycrystalline silicon substrate of the present invention can be realized, and further, a high-performance solar cell element and solar cell module using the same can be realized. A solar cell element, which is a photoelectric conversion element formed in this way, generally has a small electrical output generated by one solar cell element. Therefore, a solar cell in which a plurality of solar cell elements are generally connected in series. Used as a battery module. Further, by combining a plurality of solar cell modules, a practical electric output can be obtained.

 [0076] Representative structural diagrams of the solar cell module are shown in Figs.

 FIG. 5 is a cross-sectional view showing the structure of a general solar cell module, and FIG. 6 is a top view of the light receiving surface side of the solar cell module.

 11 is a solar cell element, 41 is a wiring member that electrically connects the solar cell elements, 42 is a transparent member such as glass, and 43 is polyethylene terephthalate (PET) or metal foil made of poly (fluorinated fluorinated resin) (PVF). Sandwiched back surface protective material, 44 is a powerful front side filler such as transparent ethylene butyl acetate copolymer (EVA), 45 is a powerful back side filler such as EVA, 46 is output lead wiring, 47 is a terminal box, Reference numeral 48 denotes a frame of the solar cell module.

 [0077] As shown in FIG. 5, a transparent ethylene butylacetate copolymer is formed on the transparent member 42.

 (EVA) and other front-side fillers 44, a plurality of solar cell elements 11 in which the front and back electrodes of adjacent solar cell elements are alternately connected by wiring members 41, and back-side fillers made of EVA, etc. 45 And, for example, polyethylene terephthalate (PET) or back surface protective material 43 in which a metal foil is sandwiched between polyvinyl fluoride (PVF), are laminated one after another, deaerated in a laminator, heated and pressed together To complete the solar cell module.

[0078] Then, if necessary, a frame 48 of aluminum or the like is fitted around the periphery. Further connected in series One end of the electrodes of the first element and the last element of the plurality of elements is connected to an terminal box 47 which is an output extraction portion by an output extraction wiring 46.

 As the wiring member 41 for connecting these solar cell elements, a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is generally coated with a solder material to a predetermined length. Cut and solder on the electrode of the solar cell element.

Although the embodiments of the present invention have been described above, the embodiments of the present invention are not limited to the above embodiments.

 For example, in the above description, the case where the casting method is used for the fabrication of the silicon ingot has been described, but the present invention is not limited to this. That is, in-mold melting and solidification method in which the raw material is melted and solidified as it is in the vertical mold, molten silicon is introduced into a sheet shape on, for example, a graphite material, solidified and solidified, or molten silicon force silicon is sheared. The present invention can also be applied to a ribbon method that solidifies and solidifies while being drawn out.

 [0080] In the above description, a solar cell using a p-type silicon substrate has been described. However, even when an n-type silicon substrate is used, the present invention can be performed by the same process if the polarity in the description is reversed. Can be applied.

 In the above description, the case of single junction has been described. However, the present invention can be applied to a multi-junction type in which a thin film junction layer such as a semiconductor multilayer film is laminated on a junction element using a Balta substrate. can do.

Further, in the above description, the Balta type silicon solar cell is taken as an example, but the present invention is not limited thereto, and can be in any form as long as it does not deviate from the principle of the invention. . That is, a photoelectric conversion element including a pn junction having a crystalline silicon having a light incident surface as a constituent element, and a solar cell that collects photogenerated carriers generated in the semiconductor region by light irradiation on the light incident surface as a current Applicable to general photoelectric conversion elements such as photosensors other than batteries.

 Example

[0082] Hereinafter, with respect to a Balta type polycrystalline silicon solar cell using a polycrystalline silicon substrate manufactured according to the above-described embodiment, a substrate appearing on the cleavage surface of the substrate in a substrate state (before elementization). This will be explained using experimental results that examine the relationship between the ESR spin density, light element concentration, and device characteristics based on ring rings.

 In the forging experiment, after comprehensive measures for reducing carbon contamination described in the above embodiment were taken, it was confirmed in advance that the carbon concentration in the ingot would change depending on the Ar gas pumping speed. went.

[0083] The silicon raw material was 80 kg, the B doping amount was an amount suitable for realizing the specific resistance p b = 2 Q'cm of the substrate butter, and the Ar gas pressure in the furnace was adjusted to lOkPa.

 Forging was carried out using the Ar gas flow rate during the melting and solidification process and the heat removal performance of the vertical side force at the initial stage of solidification (whether or not the side wall of the vertical inner wall was forcedly solidified) as parameters. Here, since the Ar gas pressure is fixed with respect to the Ar gas flow rate, an increase in the Ar flow rate means an increase in the gas displacement.

[0084] The forged ingot is as follows.

 Ingot No.1: Ar gas flow rate of 40L / min, no vertical side heat removal acceleration (forced solidification) in the initial stage of solidification

 Ingot No.2: Ar gas flow rate 80L / min, no vertical side heat removal acceleration (forced solidification) at the initial stage of solidification

 Ingot No.3: Ar gas flow rate 80L / min, vertical side heat removal promotion (forced solidification) in the initial stage of solidification

 Ingot No. 1 was manufactured by a conventional method, Ingot No. 2 was obtained by increasing the Ar gas flow rate compared to the conventional method, and Ingot No. 3 increased the Ar gas flow rate and the vertical side in the initial stage of solidification. A part-shaped side part with enhanced heat removal (forced coagulation).

[0085] Here, in order to promote heat removal from the vertical side, for example, the output of the side heater HI may be reduced. The output of the conventional side heater is about 10 to 20 when the upper heater output is 100 (relative value). To improve the heat release performance and forcibly solidify the Si melt at the part in contact with the vertical wall The output of this side heater HI should be reduced to about 0-10. Alternatively, forced solidification can also be realized by using a carbon-based material as the side saddle material.

[0086] The fabricated ingot was cured by a cutting and slicing process, and was about 250 μm thick. A flat polycrystalline silicon substrate of Xl 50 mm X 155 mm, was obtained.

In addition, a plurality of substrates used for elementization and analysis were collected from regions with a solidification rate of 15%, 20%, 40%, 60%, and 80% in the ingot. Here, the region of solidification rate x% is a region defined along the direction of solidification in the ingot, where the bottom of the ingot with the fastest solidification is _x = 0% and the top of the ingot with the slowest solidification is x = 100%. To do.

 [0087] Impurity concentration analysis of oxygen, carbon, and nitrogen on the substrate is performed using FTIR (Fourier Transform Infrared Spectrometer tens; Fourier Transform Infra Red spectrometer). It does not matter.) At this time, the analysis positions were four points arranged almost evenly in the substrate excluding the substrate edge lcm width, and the average impurity concentration at these four points was taken as the impurity concentration of the substrate. However, the distribution width of the impurity concentration within the substrate surface excluding the lcm width at the edge of the substrate is about ± 10%, and the past experience has already become sufficiently clear, especially in the ingots in question. If there is no reason to suspect this, the measured value at one point in the board, excluding the width at the edge of the board, should be represented by the average value of the measured values at multiple points (2 or 3 points). You can also.

 [0088] The defect level (spin density) at the cleavage plane of the substrate was examined using the ESR method. After removing the slice damage layer from the ingot from the ingot by the method described above, that is, by etching with NaOH, KOH, or a mixed solution of hydrofluoric acid and nitric acid for about 10 to 20 m. Mirror etching treatment with mixed acid so that the substrate thickness is about 200 m, followed by cleavage treatment (separation and division treatment using the ease of cracking on specific crystal planes due to the unique structure of the crystal). Eight pieces divided into small pieces were prepared and used as measurement samples.

 The cleavage treatment can be easily performed by slightly scratching the end portion of the substrate with a diamond cutter or the like and dividing it with the base point. As a result, a cleavage plane is obtained.

 Since the present invention is based on the knowledge that there is a correlation between the dangling bond appearing on the cleavage plane and the solar cell characteristics and impurity concentration, when performing ESR measurement related to the present invention, It is important not to perform acid treatment after cleaving (do not etch the cleaved surface).

[0090] At this time, the measurement temperature is about 10K, and Si corresponding to g = 2.005 to 2.006. The spin density considered to be based on dangling bonds existing on the cleavage plane was measured. As in the case of the impurity analysis described above, this ESR analysis is preferably performed by four points arranged almost evenly on the substrate surface except for the lcm width of the substrate edge. For the same reason, it can be represented by the average of the measured values of one point or the measured values of multiple points (2 or 3 points).

[0091] Next, main element fabrication conditions are as follows. The reverse conductivity type region 4 has a POC1 of POC1 with the aim of having a sheet resistance of 65 Ω.

 It was formed by the thermal diffusion method using 3 as the diffusion source. The surface electrode 1 was formed by printing and baking using an Ag paste mainly composed of silver. The front electrode 1 has two 2 mm wide bus bar electrodes la parallel to the edge of the 155 mm substrate and 63 μm wide finger electrodes lb parallel to the edge of the 150 mm substrate. This pattern was used. The number of fabricated elements was 10 samples from the solidification rate position for each experimental condition, and the average characteristic was defined as the element characteristic at the solidification ratio position.

[0092] In the following, a brief description of the analysis method described above and the current measurement conditions will be described.

 The ESR (Electron Spin Resonance) method solves the degeneracy of the spin state of an electron by applying an appropriate magnetic field (causing an energy level difference), and absorbs microwaves according to the magnetic field strength. This is a measurement method that measures the density of electron spins by examining. Here, the g value is a value specific to the defect type defined by g = hv / j8 H (hv is the microwave energy, β is the Bohr constant, and Η is the magnetic field strength), for example, Si dangling The g value corresponding to the bond is about 2.005-2.006.

[0093] In the ESR method, only electrons in the state of the spin quantum number S = 1Z2 are detected. In other words, in S = 0 state, there is no electron to absorb the microwave, so microwave absorption does not occur, while in S = 1, the electron is present in each of the two states where degeneracy is solved. In order to exist! /, Microwave absorption does not occur (for filling up seats). On the other hand, from the viewpoint of defect levels that cause carrier recombination, levels other than S = 1Z2 can generally function as recombination levels. Therefore, it is understood that the ESR method gives different information from the μPCD method that measures the lifetime corresponding to the recombination level density and the SPV method that measures the diffusion length. [0094] When measurement is difficult due to large noise at room temperature, measurement may be possible if the measurement is performed under the above-mentioned cryogenic conditions of about 10K. The polycrystalline silicon substrate currently used for high-efficiency polycrystalline silicon solar cells usually needs to be measured at very low temperatures.

 The measurement conditions this time are as follows.

 Equipment used: Bruker ESP350E

 Measurement temperature: 10K

 Central magnetic field: around 3368G

 Magnetic field sweep range: 100G

 Modulation: 100kHz, 2G

 Microwave: 9. 46GHz, 0.04mW

 Sweep time: 83. 886sec X 8times

 Time constant: 327. 68msec

 The measurement temperature of 10K is a temperature achieved using He gas. In this ESR measurement, the force at which the measurement temperature is 10K does not necessarily have to be set strictly at 10K. Usually, if measurement is performed in the range of about 10K to about 20K, it is considered that a measurement result almost the same as that measured at 10K (even if there is a difference, it falls within the error range) can be obtained.

 On the other hand, the FTIR includes a light source unit, an interferometer, a sample unit, a detection unit, and a data processing unit.

The light emitted from the light source unit enters the interferometer and passes through the sample as an interference wave. At that time, light having a specific frequency corresponding to the vibration energy of atoms or atomic groups in the molecules constituting the sample is absorbed. The signal obtained by the detector is Fourier transformed to obtain an infrared vector specific to the element. Oxygen in interstitial silicon carbon of 1106cm substitution lattice positions peak appears at 607cm ^1. The absolute concentration is measured by comparing this peak with a standard sample.

 [0096] The measurement conditions this time are as follows.

 Equipment used: Bruker IFS—66vZS

 Light source: SiC

Detector: DTGS Beam Splitter: Ge / KBr

Resolution: 8cm ¹

Integration count: 1024

Measurement mode: Transmission

Measurement area: 5mm φ

 SIMS (Secondary Ion Mass Spectrometry) is a method of irradiating a sample with a primary ion beam (oxygen, cesium, etc.) that has been accelerated and finely focused in a vacuum, and the surface force of the sample popping out by sputtering. Among these methods, secondary ions are extracted with an electric field and mass analysis is performed. The absolute concentration is converted by comparison with a standard sample. The measurement conditions this time are as follows.

Equipment used: Cameca IMS—4f

Primary ion species: Cs +

Primary ion acceleration voltage: 14.5 kV

Primary ion current: 120nA

Raster area: 125 m

Analysis area: 30 / ζ πι φ

Measuring vacuum: IE-7

 Table 1 shows the experimental results. The numerical values in Table 1 are the average values of the measured values for the four points that are arranged almost evenly in the board surface excluding the lcm width at the edge of the board.

[table 1]

Experiment Forging conditions Solidification rate Solidification rate Solidification rate Solidification rate Solidification rate

 No 1 5% 20% 40% 60% 80%

 1 Conventional [Οί] 4.2E17 2.4E17 6.7E16 2.2E16 0.7E16

 (Ar flow rate = (Csl 1.8E17 2.3E1 3.9EI 7 4.2E17 3.8E17

 40 / min) (oil- 4.4E86 6.7E86 15.5E86 6.8E86 1.5E86

 [Cs] ^ 4 <2E15 2.3E15 5.2E15 4.9E15 5.5E15

 [N] 3.5E14 5.1 E14 6.2E14 4.4E14 3.8E14

 Nspin 35.36 35.27 34.83 35.35 35.41

 Jsc 0.613 0.612 0.609 0.61 1 0.612

 Voc 0.755 0.756 0.756 0.756 0.755

 FF 16.37 16.32 16.04 16.33 16.36 Efficiency

 2 Ar flow increase [Oi] 3.8E17 2.3E17 6.9E16 2.3E16 0.7E16

 (80l_ / min) [Cs] 0.6E17 0.7E17 2.1E17 3.2E17 4.1E17

 [Oi]-4.9E84 5.5E84 1.3E86 2.4E86 2.0E86

 [Cs] "4 <2E15 2.4E15 4.9E15 5.1E15 4.9E15

 [N] 2.3E14 2.3E14 3.6E14 3.7E14 3.6E14

 Nspin 35.63 35.61 35.49 35.46 35.48

 Jsc 0.615 0.613 0.61 1 0.612 0.613

 Voc 0.756 0.756 0.757 0.756 0.755

 FF 16.57 16.50 16.42 16.41 16.42 Efficiency

 3 Ar flow increase [Oi] 4.4E17 2.5E17 7.2E16 2.3E16 0.7E16

 C80IVmin) [Cs] 0.6E17 0.7E1 F 2.0E17 3.1 E17 3.8E17

 [Oi] '5.7E84 6.0E84 1.2E86 2.1E86 1.5E86 Solidification process [Cs] "4 <2E15 <2E15 <2E15 2.3E15 3.4E15 Early [N] 2.2E14 2.3E14 2.3E14 2.9E14 2.7E14 Saddle side Strong Nspin 35.65 35.62 35.60 35.52 35.57

 Heat control heat Jsc 0.615 0.614 0.612 0.614 0.615

 (Te gas = 19sec) Voc 0.757 0.756 0.756 0.755 0.755

 FF 16.60 16.53 16.47 16.47 16.52 Efficiency Unit

 [0 '] [atoms / cm3] [Gs] [atoms / cm3] [N] [atoms / cm3] Nspin [spins / cm3]

Jsc [mA m2] Voc [V], efficiency [%] Ingot No. l, spin density Nspin at g = 2.005 to 2.006 measured by ESR (electron spin resonance) method at a temperature of 10K is solidified The substrates with rates of 20%, 40%, 60%, and 80% are all in excess of 3.5E14 (spins / cm ³ ) and are therefore out of the scope of the present invention. The spin density Nspin is 3.5E14 (spins / cm ³ ) only for a substrate with a solidification rate of 15%, which is within the scope of the present invention. In addition, when the interstitial oxygen concentration analyzed by FTIR is [Oi] and the substitutional position carbon concentration is [Cs], [Oi] X [Csr4] exceeds 4E86 (atoms m ³ ). Nitrogen concentration [N] measured by SIMS exceeds 4E15 (a toms / cm ³ ) for substrates with solidification rates of 40%, 60%, and 80%. Only substrates with a solidification rate of 15% and 20% are 4E15 (atoms / cm ³ ) or less. [0099] In ingot No. 2, the spin density Nspin is 3.5E14 (spins / cm ³ ) or less for all substrates with a solidification rate of 15%, 20%, 40%, 60%, and 80%. Are within the scope of the present invention. When the interstitial oxygen concentration analyzed by FTIR is [Oi] and the carbon concentration at the substitution position is [Cs], [Oi] X [Csr4] is all 4E86 or less. The nitrogen concentration [N] is 4E15 (atoms / cm ³ ) or less only for substrates with a solidification rate of 15% and 20%.

[0100] In ingot No. 3, the spin density Nspin is 3.5E14 (spins / cm ³ ) or less for all substrates with solidification rates of 15%, 20%, 40%, 60%, and 80%. Are within the scope of the present invention. Compared with Ingot No. 2, the spin density Nspin is getting smaller especially on substrates with a high solidification rate. [Oi] X [Csr4 is also below 4E86. The nitrogen concentration [N] is also all below 4 E15 (atoms / cm ³ ).

 [0101] The average element efficiency of the solar cell element was 16.28% for the substrate element taken from Ingot No. 1, and 16.46% for the board element taken from Ingot No. 2. Yes. From this, it can be estimated that an increase in Ar flow rate leads to an increase in element efficiency. In addition, the average value of the element efficiency of the substrate element taken from Ingot No. 2 is 16.46%, while that of the board element taken from Ingot No. 3 is 16.52%. Yes. From this, it can be presumed that heat removal from the vertical side surface in the initial stage of solidification leads to an increase in element efficiency.

Claims

The scope of the claims  [1] A polycrystalline silicon substrate for a photoelectric conversion element, Concerning the impurity concentration in the polycrystalline silicon substrate, the spin density at the g value = 2.005 to 2.006 when the cleaved surface of the substrate is measured at a temperature of about 10 K by the ESR (electron spin resonance) method is expressed as Nspin Is [spins / cm ³ ])  Nspin ≤ 3.5E14 (Condition 1)  A polycrystalline silicon substrate in which a region satisfying the condition exists in the substrate. [2] The polycrystalline silicon substrate according to [1], which is cut out from an ingot. [3] The polycrystalline silicon substrate according to [2], wherein the “condition 1” is satisfied in at least a part of the substrate region excluding the lcm width region of the substrate end. [4] A substrate region having an ingot solidification rate of 15 to 80%, wherein at least a part of the substrate region excluding the substrate end portion lcm width region satisfies the “condition 1”. Item 3. The polycrystalline silicon substrate according to item 2. [5] When the interstitial oxygen concentration measured by Fourier transform infrared spectroscopy is [Oi] [atoms / cm ³ ] and the substitutional carbon concentration is [Cs] [atoms / cm ³ ],  [Oi] X [Csr4 ≤ 4E86 (Condition 2; represents power)  2. The polycrystalline silicon substrate according to claim 1, wherein a region satisfying the condition exists in the substrate. 6. The polycrystalline silicon substrate according to claim 5, cut out from the ingot. 7. The polycrystalline silicon substrate according to claim 6, wherein the “condition 1” and the “condition 2” are satisfied in at least a part of the substrate area excluding the lcm width area of the substrate edge. [8] The above-mentioned "Condition 1" and "Condition 2" are satisfied in at least a part of the substrate region excluding the substrate end lcm width region, which is a region having an ingot solidification rate of 15 to 80%. Term 6. The polycrystalline silicon substrate according to 6. [9] When the nitrogen concentration measured by Fourier transform infrared spectroscopy or secondary ion mass spectrometry is [N] [a toms / cm ³ ],  [N] ≤ 4E15 (Condition 3)  2. The polycrystalline silicon substrate according to claim 1, wherein a region satisfying the condition exists in the substrate. 10. The polycrystalline silicon substrate according to claim 9, cut out from the ingot. 11. The polycrystalline silicon substrate according to claim 10, wherein the “condition 1” and the “condition 3” are satisfied in at least a part of the substrate area excluding the lcm width area of the substrate edge. [12] The above-mentioned "Condition 1" and "Condition 3" may be satisfied in at least a part of the region excluding the lcm width region of the substrate edge portion, in an ingot solidification rate of 15 to 80%. 10. The polycrystalline silicon substrate according to 10. [13] When the nitrogen concentration measured by Fourier transform infrared spectroscopy or secondary ion mass spectrometry is [N] [a toms / cm ³ ],  [N] ≤ 4E15 (Condition 3)  6. The polycrystalline silicon substrate according to claim 5, wherein a region satisfying the condition exists in the substrate. 14. The polycrystalline silicon substrate according to claim 13, cut out from the ingot. [15] Substrate edge part At least a part of the substrate region excluding the lcm width region, the “condition 1” 15. The polycrystalline silicon substrate according to claim 14, wherein “condition 2” and “condition 3” are satisfied. [16] The above-mentioned “Condition 1”, “Condition 2” and “Condition 3” are satisfied in at least a part of the region excluding the lcm width region of the substrate edge, which is a region having an ingot solidification rate of 15 to 80%. The polycrystalline silicon substrate according to claim 14. [17] A polycrystalline silicon ingot for a photoelectric conversion element, Concerning the impurity concentration in the polycrystalline silicon substrate, the spin density at the g value = 2.005 to 2.006 when the cleaved surface of the substrate is measured at a temperature of about 10 K by the ESR (electron spin resonance) method is expressed as Nspin Is [spins / cm ³ ])  Nspin ≤ 3.5E14 (Condition 1)  Polycrystalline silicon ingot that exists in S ingot. [18] A polycrystalline silicon ingot for a photoelectric conversion element, When the interstitial oxygen concentration measured by Fourier transform infrared spectroscopy is [Oi] [atoms / cm ³ ] and the substitutional carbon concentration is [Cs] [atoms / cm ³ ],  [Oi] X [Cs] ^ ≤ 4E86 (Condition 2; represents power)  The polycrystalline silicon ingot according to claim 17, wherein the polycrystalline silicon ingot is present in a region force S ingot that satisfies the condition. [19] When the nitrogen concentration measured by Fourier transform infrared spectroscopy or secondary ion mass spectrometry is [N] [a toms / cm ³ ], [N] ≤ 4E15 (Condition 3)  The polycrystalline silicon ingot according to claim 17, wherein the polycrystalline silicon ingot is present in a region force S ingot that satisfies the condition. [20] A method of manufacturing a polycrystalline silicon substrate, comprising:  Throw silicon into the bank,  While flowing Ar at a flow rate such that the gas residence time in the crucible is 25 sec or less, the silicon is melted,  Transfer the melted silicon to a mold, solidify and cool the silicon to make an ingot,  A method of manufacturing a polycrystalline silicon substrate by cutting out the fabricated ingot to obtain a polycrystalline silicon substrate.  21. The method for producing a polycrystalline silicon substrate according to claim 20, wherein when the silicon is solidified and cooled, the heat removal from the side face of the saddle is enhanced in the initial stage of solidification to solidify the side face force of the saddle.  [22] A method of manufacturing a polycrystalline silicon substrate, comprising:  Throw silicon into the recording,  While flowing Ar at a flow rate such that the gas residence time in the saddle is less than 25 seconds , Melt silicon,  The molten silicon is solidified and cooled to produce an ingot,  A method of manufacturing a polycrystalline silicon substrate by cutting out the fabricated ingot to obtain a polycrystalline silicon substrate.  23. The method for producing a polycrystalline silicon substrate according to claim 22, wherein when the silicon is solidified and cooled, the heat removal from the side face of the saddle is enhanced in the initial stage of solidification to forcibly solidify the side face force of the saddle.  24. A photoelectric conversion element using the polycrystalline silicon substrate according to claim 1. [25] A photoelectric conversion module formed by electrically connecting a plurality of the photoelectric conversion elements according to claim 24 in series or in parallel.