WO2007004428A1

WO2007004428A1 - Signal transmission circuit and endoscope

Info

Publication number: WO2007004428A1
Application number: PCT/JP2006/312437
Authority: WO
Inventors: Kazunori Segawa
Original assignee: Olympus Medical Systems Corp.
Priority date: 2005-07-04
Filing date: 2006-06-21
Publication date: 2007-01-11
Also published as: JPWO2007004428A1; JP4512639B2

Abstract

A signal transmission circuit and an endoscope in which communication by a plurality of differential signals of different signal standards can be achieved through a simpler arrangement than before. The signal transmission circuit comprises a pulse transformer (52) including a primary winding consisting of coils (52a, 52b) connected in series and a secondary winding consisting of coils (52c, 52d) connected in series, a switch (53a) having one end connected with a predetermined potential and the other end connected with the joint of the coils (52a, 52b), a switch (53b) having one end connected to the ground side and the other end connected with the joint of the coils (52c, 52d), a pair of first signal lines being connected with the opposite ends of the primary winding, respectively, a pair of capacitors (54) being connected with the opposite ends of the secondary winding, respectively, and a pair of second signal lines being connected with the other end of the pair of capacitors (54), respectively.

Description

Specification

Signal transmission circuit and endoscope apparatus

Technical field

The present invention relates to a signal transmission circuit that transmits a differential signal and an endoscope apparatus that includes a signal transmission circuit that transmits a differential signal.

Background art

Endoscopic devices are widely used in the medical field, industrial field, and the like. In general, an endoscope apparatus has an imaging device having specifications according to various uses, and converts reflected light from an illuminated observation site into an imaging signal. The generated imaging signal is transmitted to a video processing circuit of a camera control unit (hereinafter abbreviated as “ecu”), converted into a video signal, and output to a monitor. For example, in an endoscope apparatus, when an observation site is fine and complicated, an image sensor that captures images with high resolution and high image quality and a video processing circuit corresponding to the image sensor are required. Therefore, an endoscope device is required to have an imaging element corresponding to an observation site and application.

[0003] However, in order to support a plurality of different image sensors, a drive circuit for driving the image sensor, a CDS (Correlated Double Sampling) circuit that converts analog image signals to digital, and AZD conversion There is a problem that a circuit, a signal transmission circuit that transmits an imaging signal, and a signal transmission path must be provided with a driving frequency and a driving method that are different for each imaging device.

[0004] Therefore, for example, in Japanese Patent Application Laid-Open No. 2003-224743, an imaging device, a converter for digitally converting an imaging signal, a serializer for serially converting a digital signal, and a serial signal converted into a differential signal are transmitted. An image system having an intelligent camera head equipped with a transmission means is proposed.

[0005] By the way, as signal standards for differential signals, for example, CML (Current Mode Logic) and LVDS (Low Voltage Differential Signaling) such as offset voltage, differential amplitude voltage, driving principle, and the like are different from each other. There are standards. Therefore, for example, an image equipped with an intelligent camera head disclosed in Japanese Patent Laid-Open No. 2003-224743. When configuring a system that can communicate with multiple differential signals with different signal standards, such as an image system, separate signal transmission circuits that are compatible with the signal standards of the multiple differential signals. As a result, if the circuit configuration of the system becomes complicated, a problem arises.

[0006] The present invention has been made in view of the above-described circumstances, and a signal transmission circuit and an endoscope that enable communication using a plurality of differential signals, each having a different signal standard, with a simpler configuration than in the past. An object is to provide a mirror device.

Disclosure of the invention

Means for solving the problem

[0007] The signal transmission circuit of the present invention is connected in series with a pair of first signal lines that transmit a first differential signal and a pair of second signal lines that transmit a second differential signal. A primary winding constituted by the first coil and the second coil, and a secondary winding constituted by the third coil and the fourth coil connected in series, A pulse transformer in which both ends of the primary winding are connected to one end of each of the pair of first signal lines, one end is connected to a predetermined potential, and the other ends are connected to the first coil and the second coil. A first switch connected to the connection point; a second switch having one end connected to the ground side and the other end connected to the connection point of the third coil and the fourth coil; and the secondary switch A pair of capacitors that connect both ends of the cable and one end of each of the pair of second signal lines; It characterized the door.

Brief Description of Drawings

FIG. 1 is a schematic schematic configuration diagram of an endoscope apparatus according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of the endoscope apparatus according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of a twisted pair cable, a transmission circuit, and a reception circuit according to the embodiment of the present invention.

FIG. 4 is a signal transmission circuit diagram in the case where the first differential signal is CML according to the embodiment of the present invention.

FIG. 5 is a signal transmission circuit diagram when the first differential signal is LVDS according to the embodiment of the present invention. [Fig. 6] CML transmission / reception circuit diagram.

[Fig. 7] LVDS transmission / reception circuit diagram.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an endoscope apparatus provided with a signal transmission circuit according to an embodiment of the present invention will be described with reference to the drawings. The signal standards for differential signals that can be transmitted by the signal transmission circuit of the present invention include, for example, CML, LVDS, and ECL (Emitter Coupled Logic). Endoscope device equipped with a transmission circuit uses CML or LVDS as the first differential signal to be transmitted on the transmitting side, and CML as the second differential signal to be received on the receiving side! The case where communication is carried out using is described.

FIG. 1 to FIG. 5 relate to an embodiment of the present invention. FIG. 1 is a schematic schematic configuration diagram of an endoscope apparatus. FIG. 2 is a block diagram of the endoscope apparatus. Fig. 3 is a circuit diagram of the twisted pair cable, transmission circuit, and reception circuit. FIG. 4 is a signal transmission circuit diagram in the case of the first differential signal strength SCML. Figure 5 is a signal transmission circuit diagram when the first differential signal is LVDS.

First, FIG. 1 shows a schematic configuration diagram of an endoscope apparatus, which will be described below.

As shown in FIG. 1, an endoscope apparatus 1 includes an endoscope 10, a camera control unit (hereinafter abbreviated as “C CU”) 11, a light source device 12, and a monitor 13. Is configured. The endoscope 10 includes an operation unit 14 and an insertion unit 15. Further, the operation unit 14 includes an endoscope circuit unit 20. On the other hand, the insertion section 15 includes an objective lens 16, a solid-state imaging element 17, a light guide fiber 19, and a cable 21.

[0013] The CCU 11 and the light source device 12 described above can connect a plurality of types of endoscopes 10 including a plurality of differential signals, in this embodiment CML or LVDS, by a cable 18. ing. The CCU 11 is connected to the monitor 13 via the coaxial cable 22.

The illumination light generated in the light source device 12 illuminates the subject through a light guide cable (not shown) in the cable 18 and a light guide fiber 19 in the insertion portion 15. The illuminated reflected light of the subject power is an objective lens 1 provided at the distal end of the insertion section 15. 6 forms an image on the light receiving surface of the solid-state imaging device 17.

[0015] The solid-state imaging device 17 images reflected light from the imaged subject based on the drive signal received from the endoscope circuit unit 20 via the cable 21, and generates an imaging signal. In addition, the solid-state imaging device 17 transmits an imaging signal to the endoscope circuit unit 20 via the cable 21.

The endoscope circuit unit 20 performs a predetermined process on the received imaging signal. Further, the endoscope circuit unit 20 transmits the processed imaging signal as CML or LVDS of the first differential signal to the CCU 11 via the cable 18.

[0017] The CCU 11 has a circuit for receiving the received first differential signal as CML of the second differential signal. Then, the CCU 11 performs a predetermined process on the obtained second differential signal to generate a video signal. This video signal is transmitted to the monitor 13 via the coaxial cable 22 and displayed on the monitor 13. Details of the predetermined processing for the above-described imaging signal and details of signal transmission will be described later.

Next, a detailed configuration of the endoscope apparatus 1 will be described below.

FIG. 2 is a block configuration diagram of the endoscope apparatus 1.

First, the CCU 11 includes a crystal oscillator 30 as a synchronization signal generation unit, a synchronization signal generation circuit 31, a transmission circuit 41, a reception circuit 42, and a serial-parallel conversion circuit (hereinafter referred to as a digital imaging signal generation unit). , SZP conversion circuit) 43, clock phase change (hereinafter referred to as line memory) 44 as storage means and digital image signal generation means 44, video processing circuit 45, digital analog conversion circuit (hereinafter DZA) (Abbreviated as a conversion circuit) 46 and an operation node 47.

In addition, the endoscope 10 includes an analog digital circuit to which a drive circuit 33, a coaxial cable 34, a solid-state imaging device 17 as an imaging means, a coaxial cable 35, an amplifier circuit 36, and a CDS circuit are added. A conversion circuit (hereinafter abbreviated as “CDS + AZD conversion circuit”) 37, a normal serial conversion circuit (hereinafter abbreviated as “PZS conversion circuit”) 38, and a transmission circuit 39.

Furthermore, the cable 18 includes two coaxial cables 32a, a coaxial cable 32b, and a twisted pair cable 40. Note that the driving circuit 33, the amplifier circuit 36, the CDS + AZD conversion circuit 37, the PZS conversion circuit 38, and the transmission circuit 39 constitute an endoscope circuit unit 20. Further, the coaxial cable 34 and the coaxial cable 35 constitute a cable 21.

The crystal oscillator 30 generates a clock signal (hereinafter abbreviated as CLK). Further, the crystal oscillator 30 transmits CLK to the synchronization signal generation circuit 31 and the video processing circuit 45. Further, the crystal oscillator 30 transmits CLK to the drive circuit 33 via the coaxial cable 32b.

[0025] The synchronization signal generation circuit 31 uses a horizontal synchronization signal (hereinafter abbreviated as HD) 1 used in the solid-state imaging device 17 based on the received CLK, a vertical synchronization signal (hereinafter abbreviated as VD), HD2 used in the video processing circuit 45 is generated. The synchronization signal generation circuit 31 transmits HD1 and VD to the drive circuit 33 via the coaxial cable 32a. Further, the synchronization signal generation circuit 31 transmits HD2 to the video processing circuit 45.

On the other hand, the drive circuit 33 generates a drive signal based on the received CLK, HD1, and VD. Further, the drive circuit 33 transmits a drive signal to the solid-state imaging device 17 via the coaxial cable 34. Further, the drive circuit 33 transmits HD1 to the PZS conversion circuit 38.

[0027] The solid-state imaging device 17 images reflected light having a subject power based on the received drive signal, and generates an analog imaging signal. The solid-state imaging device 17 transmits an analog imaging signal to the amplifier circuit 36 via the cable 35.

The amplifier circuit 36 amplifies the received analog imaging signal by the amount attenuated by transmission / reception. The amplifier circuit 36 transmits the amplified analog image signal to the CDS + AZD conversion circuit 37.

[0029] Then, the CDS + AZD conversion circuit 37 converts the received analog imaging signal into a digital imaging signal. Further, the CDS + AZD conversion circuit 37 transmits a digital imaging signal to the PZS conversion circuit 38.

Next, the PZS conversion circuit 38 generates a first serial signal having the received digital imaging signal and HD 1 received from the drive circuit 33. The reason for generating the first serial signal including HD1 as well as the digital imaging signal will be described later. Then, the P / S conversion circuit 38 transmits the first serial signal to the transmission circuit 39.

[0031] The transmission circuit 39 converts the received first serial signal into CML or LV of the first differential signal. DS is transmitted to the receiving circuit 42 via the twisted pair cable 40 and the transmission circuit 41. The reception circuit 42 receives the first differential signal as CML of the second differential signal through the transmission circuit 41. The receiving circuit 42 generates a second serial signal based on the received second differential signal. Further, the reception circuit 42 transmits the second serial signal to the SZP conversion circuit 43. Details of the differential signal transmission described above will be described later.

On the other hand, the SZP conversion circuit 43 includes a clock data recovery circuit for using a clock data recovery method (hereinafter abbreviated as CDR). CDR is a method in which only the serial signal is transmitted and the CLK is regenerated on the receiving side according to the signal interval. Normally, differential signal transmission sends data and CLK separately. However, when the signal transmission speed increases, a skew occurs between the data and CLK, and the problem arises that data cannot be restored properly. Therefore, CDR is mainly used in high-speed signal transmission. However, when the CLK is reproduced by the CDR of the serial signal that is transmitted at high speed, the reproduced CLK (hereinafter abbreviated as “reproduced CLK”) is the CLK used in the downstream circuit, which is the video in this embodiment. It may not match the CLK used in the processing circuit 45 (hereinafter abbreviated as processing CLK). The difference between the reproduction CLK and the processing CLK causes an abnormal image such as an image inversion or a color shift to be output by the video processing in the video processing circuit 45. Therefore, it is necessary to convert the digital imaging signal based on the reproduction CLK into a digital imaging signal based on the processing CLK that can be processed by the video processing circuit 45.

[0033] Therefore, the SZP conversion circuit 43 also reproduces the CLK of the received second serial signal power, and restores the digital imaging signal (parallel signal, for example, 12 bits) and HD1. Also, the S / P converter circuit 43, based on HD1 included in the serial signal, writes a write enable signal (indicated as W_Enable in the figure) as a timing signal, a write reset signal (indicated as W-Reset in the figure), , Generate.

Furthermore, the SZP conversion circuit 43 writes the digital imaging signal to the line memory 44 at a timing determined based on the reproduction CLK, the write enable signal, and the write reset signal. The line memory 44 is configured by a dual port RAM as a multiport RAM. Dual-port RAM is a storage device that can write to and read from a single RAM based on different CLKs from two systems.

Further, the video processing circuit 45 generates a processing CLK based on the CLK received from the crystal oscillator 30. Further, the video processing circuit 45 generates a read enable signal (shown as R-Enable in the figure) and a read reset signal (shown as R_Reset in the figure) as timing signals based on the processing CLK and HD2.

Subsequently, the video processing circuit 45 reads the digital imaging signal written in the line memory 44 at a timing determined based on the processing CLK, the read enable signal, and the read reset signal.

[0038] In other words, by using HD1 and HD2 as a reference for writing and reading timing

The digital imaging signal based on the reproduction CLK can be appropriately converted into a digital imaging signal based on the processing CLK.

[0039] The video processing circuit 45 performs video processing on the read digital imaging signal to generate a digital video signal. In addition, the video processing circuit 45 transmits a digital video signal to the DZA conversion circuit 46.

[0040] Further, the DZA conversion circuit 46 performs analog conversion on the received digital video signal to generate an analog video signal. Further, the DZA conversion circuit 46 transmits an analog video signal to the monitor 13 as a video output.

[0041] The operation panel 47 is configured to include a plurality of switches such as signal switching switches provided on the exterior surface of the CCU 11, for example. The operation panel 47 outputs a signal switching signal to the transmission circuit 41 in response to the operation of the signal switching switch.

[0042] Here, the details of the differential signal transmission in the present embodiment will be described below.

First, FIG. 3 shows a circuit diagram of the twisted pair cable 40, the transmission circuit 41, and the reception circuit 42, and the configuration will be described below.

[0043] The twisted pair cable 40 is a communication cable in which two signal lines are twisted together to make a pair, and the influence of noise can be suppressed as compared to signal lines arranged in parallel.

[0044] In addition, the transmission circuit 41 as a signal transmission circuit includes a resistor 50, a resistor 51, and an insulation in the transmission path. A pulse transformer 52 as an edge element, a switch 53a as a first switch, a switch 53b as a second switch, and a pair of capacitors 54 for AC coupling are configured. . The pulse transformer 52 includes a coil 52a as a first coil that is a primary winding, a coil 52b as a second coil, a coil 52c as a third coil that is a secondary winding, and a fourth coil. And a coil 52d as the coil. Further, the switches 53a and 53b are switched between ON and OFF! And between based on the signal switching signal output from the operation panel 47.

[0045] Further, the receiving circuit 42 includes one constant current source, two re-reflection preventing resistors, two n-channel field effect transistors (hereinafter referred to as FETs), a 50 Ω resistor 8 la and a resistor. 8 lb, and comprising.

[0046] The two signal lines extended from the twisted pair cable 40 constitute a pair of first signal lines. These two signal lines are connected to one end of the coil 52a and one end of a coil 52b connected in series to the coil 52a. Furthermore, the connection part between the coil 52a and the coil 52b is connected to a switch 53a connected to the high potential circuit part via the resistor 50. In addition, two signal lines extending from one end of the coil 52 c and one end of the coil 52 d connected in series to the coil 52 c are input to the receiving circuit 42 via the pair of capacitors 54. Further, the connection between the coil 52c and the coil 52d is connected to the switch 53b that is grounded via the resistor 51. In addition, the coil 52a and the coil 52b, and the coil 52c and the coil 52d connected in series are arranged at positions that are affected by the magnetic field generated when a current flows in each, and constitute one pulse transformer 52. To do.

On the other hand, the two signal lines input to the receiving circuit 42 constitute a pair of second signal lines.

One of these two signal lines is connected to the high potential circuit section through the resistor 81a and the other through the resistor 8 lb. One of these two signal lines is connected to the gate of one n-channel FET, and the other is connected to the gate of another n-channel FET. The sources of the one n-channel FET and the other n-channel FET are connected to each other and grounded through one constant current source. The drains of the one n-channel FET and the other n-channel FET are connected to one ends of two re-reflection preventing resistors, respectively. In addition, the other ends of the two anti-reflective resistors are connected to each other and have a high potential. Connect to the circuit section.

[0048] The transmission circuit 41 described above receives the CML or LVDS of the first differential signal from the transmission circuit 39 via the pair of first signal lines connected to the twisted pair cable 40, and receives the second differential signal. The CML of the differential signal is transmitted to the receiving circuit 42 via a pair of second signal lines. When the first differential signal is CML, it is assumed that the switch 53a and the switch 53b are turned on based on the signal switching signal output from the operation panel 47 and are closed. Further, in the case of the first differential signal force ^S LVDS, it is assumed that the switch 53a and the switch 53b are turned off and opened based on a signal switching signal output from the operation panel 47. Details of differential signal transmission will be described later.

[0049] Next, before explaining the details of the differential signal transmission in this embodiment, for comparison, in the case where both the transmitting and receiving circuits are CML and in the case where both the transmitting and receiving circuits are LVDS, Details of the signal flow will be described below.

[0050] First, FIG. 6 shows details of the signal flow when both the transmission and reception circuits are CML.

[0051] The transmission circuit 70 and the reception circuit 71 have the same configuration as the above-described reception circuit 42 in FIG. The two n-channel FETs of the transmission circuit 70 are transistors 95a and 95b, respectively. Further, the resistor 81a and the resistor 81b in the receiving circuit 42 correspond to the resistor 85a and the resistor 85b in the receiving circuit 71, respectively. Further, the signal line 64 and the signal line 65 extending from the connection points in the two series circuits including the two re-reflection preventing resistors of the transmission circuit 70 and the transistors 95a and 95b are respectively received. Connected to the gates of the two n-channel FETs in circuit 71.

[0052] The CML differential signal is transmitted by alternately turning on and off the transistors 95a and 95b. For example, when the transistor 95a is turned on, the current I flows from the high-potential circuit section so as to pass through the transistor 95a of the transmission circuit 70 via the signal line 64 connected to one resistor 85a of the reception circuit 71. Flowing. Similarly, when transistor 95b is turned on,

31

A current flows through the transistor 95b of the transmission circuit 70 via the signal line 65 to which the resistor 85b of the reception circuit 71 is connected. As a result, a voltage is applied to one of the two n-channel FETs of the receiving circuit 71, and the signal is transmitted by being turned on. The above is the details of the signal flow when the transceiver circuit is CML. Next, FIG. 7 shows the details of the signal flow when both the transmission and reception circuits are LVDS.

The transmission circuit 75 includes two constant current sources, a transistor 96a and a transistor 96b that are p-channel FETs, and a transistor 97a and a transistor 97b that are n-channel FETs. The sources of the transistors 96a and 96b are connected to each other, and are connected to the high potential circuit section through a constant current source. The sources of the transistors 97a and 97b are connected to each other and grounded through a constant current source. Further, the drains of the transistors 96a and 96b are connected to the drains of the transistors 97a and 97b, respectively. Signal line 66 and signal line 67 are connected to the gates of the four FETs of receiving circuit 76 from the two connection points. The signal line 66 and the signal line 67 are respectively connected to both ends of a 100 Ω termination resistor 86 immediately before the receiving circuit 76.

[0055] The differential signal of LVDS is transmitted by alternately turning on / off one of the power of the transistors 96a and 96b and one of the power of the transistors 97a and 97b. For example, when the transistor 96b and the transistor 97a of the transmission circuit 75 are turned on, the current from the high potential circuit unit passes through the transistor 96b, the signal line 66, the termination resistor 86, the signal line 67, and the transistor 97a of the transmission circuit 75. I flows. As a result, the termination resistance is 86 mm.

41

When a voltage is generated, a voltage is applied to the gate of each of the two n-channel FETs and p-channel FETs of the receiving circuit 76, and one of each of the p-channel FET and n-channel FET is turned on to transmit a signal. Will be. The above is the details of the signal flow when the transceiver circuit is LVDS.

[0056] Here, details of differential signal transmission in the present embodiment will be described below.

[0057] In the present embodiment, the reception circuit 42 receives the CML as the second differential signal by the transmission circuit 41 even if the first differential signal on the transmission side is CML or LVDS. It can be done.

[0058] First, FIG. 4 shows details of the signal flow when the first differential signal is CML, that is, when the transmission circuit 39 is CML, and will be described below.

As shown in FIG. 4, the CML transmission circuit 39 has the same configuration as the transmission circuit 70 in FIG. 6 described above. The two n-channel FETs of the transmission circuit 39 are transistors 90a and 90b, respectively. Sarakuko, two anti-rereflection resistors for transmitter circuit 39 and transistor 90a The signal line 60 and the signal line 61 extending from the connection point in the two series circuits including the transistor 90b are connected to the twisted pair cable 40, respectively. When the transmission circuit 39 is CML, the switch 53a and the switch 53b are turned on and closed.

[0060] The CML as the first differential signal is transmitted by alternately turning on and off the transistor 90a and the transistor 90b in the same manner as the above-described CML transmission / reception circuit. For example, when the transistor 90a of the transmitter circuit 39 is turned on, it passes through the transistor 90a of the transmitter circuit 39 via the switch 53a connected to the resistor 50, the coil 52b, and the signal line 61 in the twisted pair cable 40. In addition, a current I flows from the high potential circuit. This current I force S

11 When the current flows through the coil 52b, a magnetic field due to the current I is generated around the coil 52b. At this time,

11

A current I flows in the coil 52d arranged so as to be affected by the generated magnetic field in a direction that creates a magnetic field that cancels the generated magnetic field. This current I is a resistance of the receiving circuit 42.

12 12

It flows from the high potential circuit connected to the anti-81a to the ground through the coil 52d and the resistor 51.

Similarly, when the transistor 90b is turned on, the transistor 90b passes through the transistor 90b of the transmission circuit 39 via the switch 53a connected to the resistor 50, the coil 52a, and the signal line 60 in the twisted pair cable 40. High-potential circuit force current flows. When this current flows through the coil 52a, a magnetic field due to the current is generated around the coil 52a. At this time, a current flows in the coil 52c arranged so as to be affected by the generated magnetic field in a direction that creates a magnetic field that cancels the generated magnetic field. This current flows from the high potential circuit connected to the resistor 8 lb of the receiving circuit 42 to the ground through the coil 52c and the resistor 51.

As a result, one of the two n-channel FETs of the receiving circuit 42 is turned on, and a signal is transmitted by changing the current flowing through the two n-channel FETs. That is, the same voltage as when the transmission / reception circuit shown in FIG. 6 is CML is applied to the n-channel FET of the reception circuit 42. As a result, the CML of the first differential signal is transmitted as the CML of the second differential signal.

Next, FIG. 5 shows details of the signal flow when the first differential signal is LVDS, that is, when the transmission circuit 39 is LVDS, and will be described below.

As shown in FIG. 5, the LVDS transmission circuit 39 has the same configuration as the transmission circuit 75 of FIG. It is completed. The two p-channel FETs of the transmission circuit 39 are transistors 9la and 91b, respectively, and the two n-channel FETs are transistors 92a and 92b, respectively. Furthermore, the transistor 9 la and 9 lb of the transmission circuit 39, the transistor 92a and the transistor 92b, and the signal line 62 and the signal line 63, which extend the connection point in the two series circuits that are also power, are respectively connected to the twisted pair cable 40. Connected. When the transmission circuit 39 is LVDS, the switch 53a and the switch 53b are turned off and opened.

[0065] Then, the LVDS as the first differential signal is transmitted by alternately turning on and off the transistor 9la and the transistor 92b and the transistor 9lb and the transistor 92a in the same manner as the LVDS transmission / reception circuit described above. Is done.

[0066] For example, when the transistor 9 lb and the transistor 92a of the transmission circuit 39 are turned on, the transistor 91b, the signal line 62 in the twisted pair cable 40, the coil 52a, the coil 52b, and the signal line 63 in the twisted pair cable 40 Current I flows from the high potential circuit section of the transmission circuit section 39 so as to pass through the transistor 92a. This current I force coil 52a and coil 52b

21 21

When a current flows through the, a magnetic field due to the current I is generated. At this time, it is affected by the generated magnetic field.

twenty one

Currents I flow through the coils 52c and 52d arranged to create a magnetic field that cancels out the generated magnetic field.

twenty two

[0067] Similarly, when the transistor 91a and the transistor 92b are turned on, the transistor 91a, the signal line 63 in the twisted pair cable 40, the coil 52b, the coil 52a, the signal line 62 in the twisted pair cable 40, and the transistor A current flows from the high potential circuit section of the transmission circuit section 39 so as to pass through 92b. That is, the current direction in the coil 52b and the coil 52a is opposite to the current I, and the current in the opposite direction to the current I flows in the coils 52c and 52d.

21 22

It will be awkward.

[0068] As a result, one of the two n-channel FETs of the receiving circuit 42 is turned on, and a signal is transmitted by changing the current flowing through the two n-channel FETs. That is, the same voltage is applied to the two n-channel FETs of the receiving circuit 42 as when the transmitting circuit 39 in FIG. 4 is CML. As a result, the LVDS of the first differential signal is transmitted as CML of the second differential signal.

[0069] Further, the pair of capacitors 54 add an appropriate bias voltage in the receiving circuit 42. Therefore, it plays a role in absorbing the difference in offset voltage between CML and LVDS of differential signals.

[0070] As described above, according to the present embodiment, the transmission circuit 41 has the second differential signal regardless of whether the first differential signal transmitted from the transmission side is CML or LVDS. It can be transmitted as CML of the signal so that the receiving side can receive it. As a result, the transmission circuit 41 as a signal transmission circuit in the present embodiment can perform communication using a plurality of differential signals having different signal standards with a simpler configuration than the conventional one.

[0071] Also, according to the present embodiment, it is possible to provide an endoscope apparatus including a signal transmission circuit capable of converting a plurality of different differential signals into predetermined differential signals and transmitting them. it can. Therefore, the degree of freedom in circuit design in the endoscope 10 increases.

Furthermore, according to this embodiment, it is possible to convert a digital imaging signal based on the reproduction CLK into a digital imaging signal based on the processing CLK.

[0073] In the present embodiment, the PZS conversion circuit 38 may generate a serial signal in which, for example, unique optical information or the like is added to a plurality of endoscopes 10 having different characteristics. In this case, in the CCU 11, correction control is added to the video processing performed by the video processing circuit 45 based on the received information.

[0074] Further, in the present embodiment, the optical image obtained by the objective lens 16 is split into red, blue, and green light via a spectral prism, and each of the three lights is imaged. You may make it the structure which images by an element and obtains a power error image. In this case, the transmission path for transmitting the imaging signal from the endoscope 10 to the CCU 11 as shown in FIG.

[0075] In addition, the transmission / reception time of each transmission path differs depending on the length of the twisted pair cable 40 of each of the plurality of transmission paths, the length of the differential pattern on the board, and the like, resulting in a time difference. There is. In this case, the time difference generated can be adjusted by using a configuration in which the writing timing is generated based on HD1 that is transmitted together with the imaging signal, as in this embodiment.

Furthermore, in the present embodiment, the line memory 44 may be configured by various storage devices having similar functions that are not limited to the multiport RAM or the dual port RAM. It should be noted that according to the present embodiment, means for generating a digital image pickup signal based on a different CLK from a digital image pickup signal based on a reproduction CLK not in the line memory 44 may be used. Good.

Further, the signal transmission circuit of the present invention may be configured as a repeater or a connection terminal in various signal transmission apparatuses.

[0079] Furthermore, the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

[0080] This application is filed on the basis of the priority claim of Japanese Patent Application No. 2005-195409 filed in Japan on July 4, 2005. It shall be cited in the scope of the drawing.

Claims

The scope of the claims

[1] a pair of first signal lines for transmitting a first differential signal;

A pair of second signal lines for transmitting a second differential signal;

A primary winding composed of a first coil and a second coil connected in series, and a secondary winding composed of a third coil and a fourth coil connected in series. And a panoramic resistor in which both ends of the primary winding are connected to respective one ends of the pair of first signal wires, and

A first switch having one end connected to a predetermined potential and the other end connected to a connection point of the first coil and the second coil;

A second switch having one end connected to the ground side and the other end connected to a connection point of the third coil and the fourth coil;

A pair of capacitors connecting both ends of the secondary winding and one end of each of the pair of second signal lines;

A signal transmission circuit comprising:

[2] The signal transmission circuit according to [1], wherein the second differential signal is CML.

[3] When the first switch and the second switch are switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch 2. The signal transmission circuit according to claim 1, wherein when each switch is switched on, CM L can be transmitted as the first differential signal.

[4] When the first switch and the second switch are switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch 3. The signal transmission circuit according to claim 2, wherein CM L can be transmitted as the first differential signal when each switch is switched on.

[5] A pair of first signal lines for transmitting the first differential signal, a pair of second signal lines for transmitting the second differential signal, the first coil and the first connected in series A primary winding composed of two coils, and a secondary winding composed of a third coil and a fourth coil connected in series, and both ends of the primary winding are Each of the pair of first signal lines A pulse transformer connected to one end, a first switch having one end connected to a predetermined potential, the other end connected to the connection point of the first coil and the second coil, and one end to the ground side. A second switch connected at the other end to the connection point of the third coil and the fourth coil, both ends of the secondary winding, and one end of each of the pair of second signal lines And a signal transmission circuit comprising a pair of capacitors for connecting

Synchronization signal generating means for generating a synchronization signal;

Imaging means for imaging an object based on the synchronization signal and generating an analog imaging signal;

Analog-to-digital conversion means for converting the analog imaging signal into a digital imaging signal;

Parallel-serial conversion means for generating a first serial signal including the digital imaging signal and the synchronization signal;

Transmitting means for converting the first serial signal into the first differential signal and transmitting the first differential signal through the pair of first signal lines;

A receiver that receives the second differential signal obtained by converting the first differential signal by the signal transmission circuit and receives the pair of second signal lines to generate a second serial signal. Means,

Serial-parallel conversion that generates the digital imaging signal based on the second serial signal and a timing signal for storing the digital imaging signal based on the synchronization signal included in the second serial signal Means,

An endoscope apparatus comprising: storage means for storing the digital imaging signal based on the timing signal.

6. The endoscope apparatus according to claim 5, wherein the storage unit includes a multi-port RAM.

[7] The endoscope apparatus according to [5], wherein the second differential signal is CML.

[8] The endoscope apparatus according to [6], wherein the second differential signal is CML.

[9] When the first switch and the second switch are switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch 6. The endoscope apparatus according to claim 5, wherein when each switch is switched on, CM L can be transmitted as the first differential signal.

[10] When the first switch and the second switch are respectively switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch described above. 7. The endoscope apparatus according to claim 6, wherein CM L can be transmitted as the first differential signal when each switch is switched on.

[11] When the first switch and the second switch are switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch 8. The endoscope apparatus according to claim 7, wherein when each switch is switched on, CM L can be transmitted as the first differential signal.

[12] When the first switch and the second switch are respectively switched off, LVDS can be transmitted as the first differential signal, and the first switch and the second switch described above. 9. The endoscope apparatus according to claim 8, wherein when each switch is switched on, CM L can be transmitted as the first differential signal.

[13] A pair of first signal lines for transmitting the first differential signal, a pair of second signal lines for transmitting the second differential signal, the first coil and the first connected in series A primary winding composed of two coils, and a secondary winding composed of a third coil and a fourth coil connected in series, and both ends of the primary winding are A pulse transformer connected to one end of each of the pair of first signal lines, one end connected to a predetermined potential, and the other end connected to a connection point of the first coil and the second coil. 1 switch, one end connected to the ground side, the other switch connected to the connection point of the third coil and the fourth coil, both ends of the secondary winding, and the above A signal transmission circuit including one end of each of the pair of second signal lines and a pair of capacitors connecting the two;

Imaging means for imaging a subject and generating an analog imaging signal;

Analog-to-digital conversion means for converting the analog imaging signal into a digital imaging signal; Parallel-serial conversion means for generating a first serial signal including the digital imaging signal;

A first digital imaging signal generation means for generating a digital imaging signal based on the regenerated clock by regenerating the clock based on the second serial signal by the clock data recovery method;

Second digital imaging signal generation means for generating a digital imaging signal based on a clock different from the reproduced clock from a digital imaging signal based on the reproduced clock;

An endoscope apparatus characterized by comprising: