[go: up one dir, main page]

WO2007003639A3 - Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche - Google Patents

Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche Download PDF

Info

Publication number
WO2007003639A3
WO2007003639A3 PCT/EP2006/063858 EP2006063858W WO2007003639A3 WO 2007003639 A3 WO2007003639 A3 WO 2007003639A3 EP 2006063858 W EP2006063858 W EP 2006063858W WO 2007003639 A3 WO2007003639 A3 WO 2007003639A3
Authority
WO
WIPO (PCT)
Prior art keywords
film
substrate
obtaining
coated
silicon nitride
Prior art date
Application number
PCT/EP2006/063858
Other languages
English (en)
Other versions
WO2007003639A2 (fr
Inventor
Patrick Soukiassian
Original Assignee
Commissariat Energie Atomique
Univ Paris Sud
Patrick Soukiassian
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique, Univ Paris Sud, Patrick Soukiassian filed Critical Commissariat Energie Atomique
Priority to US11/988,284 priority Critical patent/US20100012949A1/en
Priority to EP06792480A priority patent/EP1900014A2/fr
Priority to JP2008519929A priority patent/JP2009500837A/ja
Publication of WO2007003639A2 publication Critical patent/WO2007003639A2/fr
Publication of WO2007003639A3 publication Critical patent/WO2007003639A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium steochiométrique, pour la fabrication de composants électroniques, et procédé d'obtention d'une telle couche . Pour obtenir la couche sur le substrat (1) en présence d'au moins un gaz azoté, le substrat est recouvert d'une couche (2) d'un matériau qui est perméable à ce gaz et la couche de nitrure de silicium est apte à se former à l'interface entre le substrat et la couche du matériau. L'invention s'applique par exemple en microélectronique.
PCT/EP2006/063858 2005-07-05 2006-07-04 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche WO2007003639A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/988,284 US20100012949A1 (en) 2005-07-05 2006-07-04 Substrate, in particular made of silicon carbide, coated with a thin stoichiometric film of silicon nitride, for making electronic components, and method for obtaining such a film
EP06792480A EP1900014A2 (fr) 2005-07-05 2006-07-04 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche
JP2008519929A JP2009500837A (ja) 2005-07-05 2006-07-04 化学量論組成の窒化シリコン薄膜によって被覆され、かつ電子部品の製造に用いられる基板、特に炭化珪素基板、及び前記膜を形成する方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0552060A FR2888399B1 (fr) 2005-07-05 2005-07-05 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche
FR0552060 2005-07-05

Publications (2)

Publication Number Publication Date
WO2007003639A2 WO2007003639A2 (fr) 2007-01-11
WO2007003639A3 true WO2007003639A3 (fr) 2007-03-15

Family

ID=36146953

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/063858 WO2007003639A2 (fr) 2005-07-05 2006-07-04 Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche

Country Status (5)

Country Link
US (1) US20100012949A1 (fr)
EP (1) EP1900014A2 (fr)
JP (1) JP2009500837A (fr)
FR (1) FR2888399B1 (fr)
WO (1) WO2007003639A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10446681B2 (en) 2017-07-10 2019-10-15 Micron Technology, Inc. NAND memory arrays, and devices comprising semiconductor channel material and nitrogen
US10297611B1 (en) 2017-12-27 2019-05-21 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells
US10559466B2 (en) 2017-12-27 2020-02-11 Micron Technology, Inc. Methods of forming a channel region of a transistor and methods used in forming a memory array
JP7304577B2 (ja) * 2019-11-27 2023-07-07 国立大学法人大阪大学 絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法
JP7259139B2 (ja) * 2020-03-17 2023-04-17 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト 絶縁ゲート構造、それを伴うワイドバンドギャップ材料パワーデバイス、およびその製造方法
US11538919B2 (en) 2021-02-23 2022-12-27 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells
CN114429898B (zh) * 2021-12-17 2025-04-08 浙江富芯微电子有限公司 一种用于制备氮化物单晶薄膜的碳化硅复合衬底

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039257A2 (fr) * 1999-11-25 2001-05-31 Commissariat A L'energie Atomique Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
US20040101625A1 (en) * 2002-08-30 2004-05-27 Das Mrinal Kanti Nitrogen passivation of interface states in SiO2/SiC structures
US20050064639A1 (en) * 2001-10-15 2005-03-24 Yoshiyuki Hisada Method of fabricating SiC semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3998662A (en) * 1975-12-31 1976-12-21 General Electric Company Migration of fine lines for bodies of semiconductor materials having a (100) planar orientation of a major surface
US4735921A (en) * 1987-05-29 1988-04-05 Patrick Soukiassian Nitridation of silicon and other semiconductors using alkali metal catalysts
US4900710A (en) * 1988-11-03 1990-02-13 E. I. Dupont De Nemours And Company Process of depositing an alkali metal layer onto the surface of an oxide superconductor
FR2757183B1 (fr) * 1996-12-16 1999-02-05 Commissariat Energie Atomique Fils atomiques de grande longueur et de grande stabilite, procede de fabrication de ces fils, application en nano-electronique
US20020088970A1 (en) * 2001-01-05 2002-07-11 Motorola, Inc. Self-assembled quantum structures and method for fabricating same
FR2823770B1 (fr) * 2001-04-19 2004-05-21 Commissariat Energie Atomique Procede de traitement de la surface d'un materiau semiconducteur, utilisant notamment l'hydrogene, et surface obtenue par ce procede
FR2823739B1 (fr) * 2001-04-19 2003-05-16 Commissariat Energie Atomique Procede de fabrication de nanostructures unidimensionnelles et nanostructures obtenues par ce procede

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039257A2 (fr) * 1999-11-25 2001-05-31 Commissariat A L'energie Atomique Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche
US20030102490A1 (en) * 2000-12-26 2003-06-05 Minoru Kubo Semiconductor device and its manufacturing method
US20050064639A1 (en) * 2001-10-15 2005-03-24 Yoshiyuki Hisada Method of fabricating SiC semiconductor device
US20040101625A1 (en) * 2002-08-30 2004-05-27 Das Mrinal Kanti Nitrogen passivation of interface states in SiO2/SiC structures

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AMY F ET AL: "Oxynitridation of cubic silicon carbide (100) surfaces", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY A. VACUUM, SURFACES AND FILMS, AMERICAN INSTITUTE OF PHYSICS, NEW YORK, NY, US, vol. 17, no. 5, September 1999 (1999-09-01), pages 2629 - 2633, XP012004757, ISSN: 0734-2101 *
GANEM J-J ET AL: "NRA AND XPS CHARACTERIZATIONS OF LAYERS FORMED BY RAPID THERMAL NITRIDATION OF THIN SIO2 FILMS", NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH, SECTION - B: BEAM INTERACTIONS WITH MATERIALS AND ATOMS, ELSEVIER, AMSTERDAM, NL, vol. 1364, no. 1-4, 1992, pages 744 - 749, XP008032645, ISSN: 0168-583X *

Also Published As

Publication number Publication date
US20100012949A1 (en) 2010-01-21
WO2007003639A2 (fr) 2007-01-11
EP1900014A2 (fr) 2008-03-19
FR2888399A1 (fr) 2007-01-12
FR2888399B1 (fr) 2008-03-14
JP2009500837A (ja) 2009-01-08

Similar Documents

Publication Publication Date Title
WO2004101177A3 (fr) Procede pour revetir des substrats avec un materiau a base de carbone
WO2007003639A3 (fr) Substrat, notamment en carbure de silicium, recouvert par une couche mince de nitrure de silicium stoechiometrique, pour la fabrication de composants electroniques, et procede d'obtention d'une telle couche
WO2008017472A3 (fr) Procédé pour la préparation d'une couche superficielle céramique poreuse
WO2004075248A3 (fr) Procede de revetement d'une surface, fabrication d'interconnexions en microelectronique utilisant ce procede, et circuits integres
WO2003026005A3 (fr) Obtention de nitrures de metaux refractaires par voie de chimisorption
WO2005109473A3 (fr) Amelioration de l'adhesion entre des dielectriques a faible constante dielectrique et des materiaux conducteurs
EP1868241A4 (fr) Montage auxiliaire et procédé de fabrication de celui-ci
SG131872A1 (en) Layer arrangement for the formation of a coating on a surface of a substrate,coating method,and substrate with a layer arrangement
TW200737400A (en) Etch resistant wafer processing apparatus and method for producing the same
WO2005050714A3 (fr) Dispositifs electroniques haute temperature
EP1930966A3 (fr) Couche barrière, article composite la comprenant, dispositif électroactif et procédé
TWI264121B (en) A display device, a method of manufacturing a semiconductor device, and a method of manufacturing a display device
WO2005091370A8 (fr) Méthode de fabrication d'un circuit intégré
WO2005069353A3 (fr) Revetement barriere de diffusion pour composants a base de silicium
WO2001061071A3 (fr) Procede de production de revetement par condensation
DK1921119T3 (da) Pletbestandig overtrækssammensætning, pletbestandig overtræksfilm, substrat med overtræksfilm, pletbestandig substrat, fremgangsmåde til dannelse af overtræksfilm på overflade af substrat og fremgangsmåde til at gøre substrat pletbestandigt
WO2006073435A3 (fr) Revetements nanocomposites multicouche d'extreme durete
WO2006125825A3 (fr) Procede de formation de nanofils conducteurs
TW200746354A (en) Multi-step anneal of thin films for film densification and improved gap-fill
WO2007124209A3 (fr) Intégration d'élément de contrainte et procédé associé
WO2010065457A3 (fr) Procédé de formation d'un dispositif à semi-conducteurs pourvu d'une couche diélectrique et dispositif à semi-conducteurs obtenu
TW200605163A (en) Fabrication of crystalline materials over substrates
TW200629374A (en) Patterning substrates employing multi-film layers defining etch-differential interfaces
TW200717713A (en) Advanced forming method and structure of a semiconductor device
WO2007046841A3 (fr) Composants en ceramique, structures enduites et procedes de fabrication correspondants

Legal Events

Date Code Title Description
DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2006792480

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2008519929

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWP Wipo information: published in national office

Ref document number: 2006792480

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 11988284

Country of ref document: US