WO2006085241A1

WO2006085241A1 - Active matrix display devices

Info

Publication number: WO2006085241A1
Application number: PCT/IB2006/050330
Authority: WO
Inventors: Mark T. Johnson; Gerrit Oversluizen
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-02-14
Filing date: 2006-01-31
Publication date: 2006-08-17
Also published as: TW200638147A

Abstract

An active matrix device comprises an array of rows and columns of pixels disposed over a common substrate. Each pixel comprises a row conductor (30), a first in- plane electrode pattern (32) and a first diode device (36) between the row conductor and the first in-plane electrode pattern (32). A reset conductor (42) is provided and a second diode device (40) is defined between the first in-plane electrode terminal (32) and the reset conductor (42). A column conductor (46) connects to a second in-plane electrode pattern (34) formed from the same layer as the first in-plane electrode pattern (32). The invention provides a diode based active matrix in-plane switching device in which the pixel layout is defined on a single substrate and has a double-diode configuration. The device of the invention is compatible with low cost manufacturing processes, such as roll-to-roll manufacturing.

Description

ACTIVE MATRIX DISPLAY DEVICES

This invention relates to active matrix devices, in particular electrophoretic active matrix display devices.

Electrophoretic display devices use the movement of particles within an electric field to provide a selective light transmission or light blocking function. The particles may themselves be coloured, and the electric field can be used to bring the coloured particles to the surface of the device so that they are seen. Alternatively, an underlying layer may have coloured regions, and the particles may then block the passage of light to the underlying colour or else permit this passage of light. The particles are then typically black or white.

It has been recognized that electrophoretic display devices enable low power consumption and thin display devices to be formed. They may also be made from plastics materials, and there is also the possibility of low cost reel-to reel processing in the manufacture of such displays. An electrophoretic display typically comprises a lower electrode layer, a display medium layer, and an upper electrode layer. Biasing voltages are applied selectively to electrodes in the upper and/or lower electrode layers to control the state of the portion(s) of the display medium associated with the electrodes being biased.

In the simplest form, a passive matrix addressing scheme is used. Figure 1 shows a known passive matrix display layout for generating perpendicular electric fields between the top column electrodes 10 and the bottom row electrodes 12. The electrodes are generally situated on two separate substrates.

The passive matrix electrophoretic display comprises an array of electrophoretic cells arranged in rows and columns and sandwiched between the top and bottom electrode layers. The column electrodes 10 are transparent.

Cross bias is a problem in the design of passive matrix displays. Cross bias refers to the bias voltages applied to electrodes that are associated with display cells that are not in the scanning row (the row being updated with display data). For example, to change the state of cells in a scanning row in a typical display, bias voltages might be applied to column electrodes in the top electrode layer for those cells to be changed, or to hold cells in their initial state. Such column electrodes are associated with all of the display cells in their column, including the many cells not located in the scanning row.

A further problem associated with the use of passive matrix addressing is that the driving signals must be introduced to the display sequentially, typically one line at a time, along the (orthogonal) selection rows and data columns. Once the line is no longer being addressed, the electrical field is reduced to a level whereby the particles will not move. As a consequence, the particles only move whilst a line is addressed, and it will take a long time to complete addressing the display (in general, the response speed of the pixel times the number of rows in the display). As the display operates using the physical movement of particles, there is a limit to the speed at which a pixel can be addressed.

In order to speed up the addressing and to overcome the cross bias problem, it is known to use active matrix addressing, which ensures that the driving voltage is maintained during the time that other lines of the display are being selected, and also provides electrical isolation of pixels from the signal lines when not being addressed.

In an active matrix display, switching elements such as diodes or transistors are used, either alone or in conjunction with other elements, to control pixel electrodes associated with the display cell or cells associated with an individual pixel.

In one typical active matrix display configuration, for example, a common potential (e.g., ground potential) may be applied to a common electrode in the top layer and pixel electrodes located in the bottom layer are controlled by associated switching elements to either apply a biasing voltage to the pixel electrode or to isolate the pixel electrode to prevent an electric field from being generated that would cause the associated display cell(s) to change state. Electrophoretic display devices can use the movement of particles in a number of ways. In a system generating transverse electric fields, as shown in Figure 1, the particles are controlled to move selectively up and down the display material layer. When the particles are at the top, they are visible, and when they are at the bottom, then they are not visible, and the medium supporting the particles is then visible. The particles may be white, and the supporting medium may be red, green or blue.

Another type of electrophoretic display device uses so-called "in plane switching". This type of device uses movement of the particles selectively laterally in the display material layer. When the particles are moved towards lateral electrodes, an opening appears between the particles, through which an underlying surface can be seen. When the particles are randomly dispersed, they block the passage of light to the underlying surface and the particle colour is seen. The particles may be coloured and the underlying surface black or white, or else the particles can be black or white, and the underlying surface coloured. An advantage of in-plane switching is that the device can be adapted for transmissive operation, or transflective operation. In particular, the movement of the particles creates a passageway for light, so that both reflective and transmissive operation can be implemented through the material.

This invention relates specifically to the use of in-plane switching in active matrix electrophoretic displays.

A problem with the known in-plane switching active matrix devices is the complexity of the manufacturing process, and the incompatibility of such processes with roll to roll fabrication techniques. An object of the invention is to provide an active matrix device, which can be made by a simplified process, and to provide the process itself.

According to the invention, there is provided an active matrix device, comprising an array of rows and columns of pixels disposed over a common substrate, each pixel comprising: a portion of a row conductor, the row conductor extending past all the pixels of a row; a first electrode pattern including a first in-plane electrode terminal; a first diode device defined at a first cross over between the row conductor portion and a second conductor portion, the second conductor portion being connected electrically to the first in-plane electrode terminal; a portion of a reset conductor; a second diode device defined at a second cross over between portions of the layer defining the row conductor portions and the layer defining the second conductor portions, and connected electrically between the first in-plane electrode terminal and the reset conductor portion; a portion of a column conductor, the column conductor extending past all the pixels of a column; a second electrode pattern including a second in-plane electrode terminal formed from the same layer as the first in-plane electrode terminal, and electrically connected to the column conductor portion.

The invention provides a diode based active matrix in-plane switching device in which the pixel layout is defined on a single substrate and has a double-diode configuration. The device of the invention is compatible with low cost manufacturing processes, such as roll-to-roll manufacturing.

The structure of each pixel can be defined with only two conducting layers, which together define the row conductors, the column conductors, the in-plane electrode terminals and the reset conductors, and with the two diode devices each defined at crossovers between the two conducting layers. This enables low cost manufacturing.

The first and second in-plane pixel electrode terminals may comprise comb patterns and may be formed from the same layer as the second conductor portion. These comb patterns provide a good quality display and reduce the distances particles need to move during operation of the display.

In a preferred embodiment, the in-plane pixel electrode terminals and the row conductors are formed from a common metal layer, and this is the first deposited layer. The first in-plane electrode terminals may comprise substantially parallel comb lines, and the first electrode pattern then further comprises a substantially perpendicular connecting portion connecting the parallel comb lines, defined by the second conducting portion.

This enables the comb pattern to be defined from the two layers, each of which can use straight parallel lines only. Similarly, the second in-plane electrode terminals may comprise comb lines substantially parallel to the comb lines of the first in-plane electrode terminal, and the column conductor portions then connect the parallel comb lines of the second in-plane electrode terminal and are formed from the layer of the second conducting portions.

The structure can be arranged so that all conductors in any single layer of the layer or layers forming the row conductors, the reset conductors, the first electrode patterns, the column conductors and the second electrode patterns, are formed from substantially parallel lines. All patterned layers are then simple one dimensional patterns. The most complicated pattern, of the comb lines, can be the first layer deposited, and this facilitates alignment of the layers.

Each pixel may further comprise a capacitor terminal, and this can also be formed from one of the two layers. The addition of a storage capacitor into the pixel design improves the circuit performance. By forming this from one of the layers already needed, this can be achieved without additional processing complexity.

For example, the capacitor terminal of each pixel can provide capacitive coupling between the first and second in-plane electrode terminals. The invention is of particular benefit for use in an electrophoretic active matrix display device.

The invention also provides a method of manufacturing an active matrix device, comprising an array of rows and columns of pixels disposed over a common substrate, the method comprising forming, over the substrate, and using first and second layers: a row conductor array; a reset conductor array; an array of first electrode patterns each including a first in-plane electrode terminal and an array of second electrode patterns each including a second in-plane electrode terminal, the first and second in-plane electrode terminals being formed from the same layer; and a column conductor array and an array of second conductor portions formed from the same layer, the second conductor portions connected electrically to the first in-plane electrode terminals and the column conductors electrically connected to the second in-plane electrode terminals, the method comprising forming first and second diode devices at respective cross-overs between the portions of the first and second layers, the first diode device being connected between the row conductor and the first in-plane electrode terminal and the second diode device being connected electrically between the reset conductor and the first in-plane electrode terminal.

The first and second layers may be the only conducting layers needed, and this enables low cost manufacturing.

Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

Figure 1 shows a known passive matrix display layout;

Figure 2 shows a known circuit configuration for providing active matrix addressing using diodes; Figure 3 shows a first example of pixel structure for a device of the invention; Figure 4 shows a second example of pixel structure for a device of the invention;

Figure 5 shows a third example of pixel structure for a device of the invention; Figure 6 shows a fourth example of pixel structure for a device of the invention;

Figure 7 shows a fifth example of pixel structure for a device of the invention; Figure 8 shows a sixth example of pixel structure for a device of the invention; and

Figure 9 shows a seventh example of pixel structure for a device of the invention.

The same references are used in different Figures to denote the same layers or components, and description is not repeated.

This invention relates to the structure of active matrix array devices, such as display devices, and relates in particular to diode-based active matrix circuitry.

Diodes have been used in active matrix LCDs to provide the active matrix switching function, and one known architecture is termed a "double diode with reset (D2R)" configuration.

Figure 2 is used to explain the operation of the D2R pixel circuit. The diode matrix has two diodes arrangements per pixel, a first diode arrangement 20 to charge the pixel 22 via a data line 24, and a second diode arrangement 26 to discharge the pixel 22 via a common reset line 28. The blocking range, that is the voltage range where the diodes are nonconducting, is determined by the external voltages and therefore adjustable. This is a major advantage where higher operating voltages are required, as is the case for in-plane switching electrophoretic displays. This allows for larger separation between electrodes without reducing the electric field strength. Higher voltages can easily be accommodated by providing diodes in series, as this prevents breakdown of separate diodes at high reverse voltage. The pixel to the right in Figure 2 has two series diodes for each diode arrangement 20,26. In this case, the voltage is split across the diodes. The number of external connections is equal to the number of rows plus columns plus one (the common reset line 28). The circuit is very independent of the diode characteristics, and accordingly PESf or Schottky diodes can be chosen.

The circuit can be made tolerant of short or open circuit errors by using extra diodes in series (as shown in the right hand pixel in Figure 2) or parallel (as shown in the center pixel in Figure 2).

The rows can be driven using a reset method with five voltage levels, and this will be known to those skilled in the art, and will not be described in detail in this application.

A PIN (or Schottky) diode can be formed using a simple 3 -layer process. An amorphous semiconductor layer, a stack of p-doped, intrinsic, and n-doped regions, is sandwiched between top and bottom metal lines, which are oriented perpendicularly. Also metal oxide PESf (or Schottky) diodes can be applied. The electrical properties are very insensitive to alignment tolerance.

The D2R pixel configuration has been proposed for use in driving LCDs that operate with the normal layout where the electric fields are aligned perpendicular to the plane of the display.

This invention relates to the implementation of the D2R circuit configuration for use in an in-plane switched active matrix layout.

In order to create an in-plane electric field, the electrodes within a pixel must be situated adjacent to each other in the plane of the display.

A first example of pixel layout of the invention is shown Figure 3.

The pixels are arranged as an array of rows and columns of pixels disposed over a common substrate. The pixel shown includes a portion of a first row conductor 30, and this functions as the data line to the pixel. The metal layer of this row conductor is also used to define a first in-plane electrode terminal 32 and a second in-plane electrode terminal 34. These are shaped as meshed comb structures.

The data line 30 connects to the first in-plane terminal 32 through a diode device 36 (corresponding to arrangement 20 of Figure 2), and this is defined as a diode stack between the cross over of the row conductor 30 and a second conductor portion 38. This second conductor portion is part of a second metal layer, and the row conductor layer and the second metal layer are the only two metal layers in the structure.

The first in-plane terminal also connects to the common reset line 42 through a second diode device 40 (corresponding to the diode arrangement 26 and line 28 of Figure 2). The common reset line 42 is formed from the metal of the row conductor layer, and is itself patterned as an array of row lines (which are connected together outside the display area). The reset line may instead be defined as an array of column lines, or as a mesh or grid configuration.

The second diode device 40 is defined at a second cross over between the row conductor layer which forms the first in-plane terminal and another portion 44 of the second metal layer.

The second metal layer also defines a portion of a column conductor 46, and this connects to the second in-plane terminals 34 (by overlying directly the material of the first metal layer of the row conductors). These column conductors thus define the select line of the pixel, as shown in

Figure 2.

The column conductors 46 are insulated from the row conductors and the reset lines 42 by cross-over insulators 48.

This diode structure is thus formed by separating two metal layers by a thin stack of semiconductor layers, and is conveniently realized in the form of a cross over structure. Such a cross over structure is preferred for roll-to-roll manufacturing, as it makes the alignment of the electrodes less critical.

This arrangement also has the advantage that the alignment sensitive layers (particularly the in-plane electrode terminals) are structured in the same processing step. It is difficult to accurately align two structured layers relative to each other. In traditional in-plane switching layouts (using thin film transistors, for example for application in LCDs) the pixel electrodes are formed in separate metal layers. In such a case, it is difficult to arrange the second pixel electrodes to be positioned precisely between the first pixel electrodes. The relative alignment of the second metal layer is less critical. Figure 4 shows the same pixel layout as Figure 3, but shows the first and second in-plane terminals 32,34 arranged as blocks of metal layer.

In the embodiment of Figure 3, complex patterns are used (i.e. 2-dimensional structured patterns) for the two metal layers.

It is, however, desirable with roll-to-roll manufacturing (or other low cost manufacturing, such as printing based) to create simple lines rather than complex patterns.

The complex pattern of the second metal layer in Figure 3 can easily be changed into a one dimensional pattern, and indeed only the portion 44 has any row-direction component. By making the second metal layer pattern into a simple arrangement of one dimension lines, the structure has only a single complex pattern, and this pattern is also the first structured layer in the process. This means that all further layers can be patterned in the form of simple one- dimensional lines, or blocks (including the cross over insulator 48, which can be considered as short line sections).

Figure 5 shows a further improvement, in which the layout is exclusively patterned in any one patterning step in the form of simple one- dimensional lines or blocks.

In Figure 5, the in-plane electrode terminals 32,34 are each formed from a combination of the portions of the two metal layers. Row- wise portions of the first in-plane pixel electrode terminals 32, the row conductors 30, the reset conductors 42 and row- wise portions of the second in-plane pixel electrode terminals 34 are all formed from the first metal layer. These portions all run parallel to the rows, so that the pattern of the first metal layer is simply a pattern of horizontal lines.

These horizontal lines thus form the comb lines of the comb patterns. The comb lines of the first in-plane pixel electrode terminal 32 are connected by an extension of the second conductor portion 38, which reaches to all of the comb lines within the pixel. The comb lines of the second in-plane pixel electrode terminal 34 are connected by the column conductors 46 (the select lines). The second conductor portions 38 and the column conductors 46 are formed from the second metal layer, which has lines oriented exclusively in the vertical direction.

As shown in Figure 5, the second diode device uses extra portions of each metal layer, as the same PIN stack is used for the two diodes, and the layout in Figure 5 provides the required diode orientation.

The first (row direction) common metal layer is disposed first over the substrate, and the insulator portions 48 are disposed over the common metal layer as well as the diode devices 36,40.

In Figure 5, alignment tolerance is realized by extending the pixel electrodes comb lines beyond the location of the perpendicular connecting lines. In this way, a crossover contact is realized between the comb lines and the column conductor 46 and portions 38. This embodiment has an improved roll-to-roll compatible layout with only 1- dimensional patterned structures, which for each metal layer are oriented in only a single direction.

It is known that the performance of diodes can be improved by incorporating an insulating layer in the form of a frame surrounding the diode and covering the edges of the semiconductor (PESf) stack. The function of this insulator is to reduce the leakage of the diode in the reverse biased situation (leakage can occur by surface conductions along e.g. the p-type layer).

Figure 6 shows a layout in which an additional thick insulator 60 is added as a frame covering the edges of the diode. As indicated, this insulating layer can be realized in the same insulating layer as is used for the cross over insulators 48, for example a printed photo-resist or other polymeric insulator.

As mentioned above, the D2R circuit can be made tolerant to short or open circuit errors by using extra diodes in series or parallel. A layout suitable for roll-to-roll manufacturing of such diode arrangements is shown in Figure 7.

The modification of Figure 7 can be realized without increasing the number of mask steps or by introducing any more complicated structuring. Series diodes are also very useful for obtaining higher voltages, as the series connection prevents breakdown of separate diodes at high reverse voltage - the voltage being split across the diodes. Figure 7 shows how series connected diodes 70 can be implemented as well as parallel-connected diodes 72.

The performance of active matrix displays is improved by adding a storage capacitor to the active matrix pixel circuit. However, this should be achieved without adding additional processing steps. The provision of both electrodes which drive the electro-optic effect on the same substrate enables a design containing a storage capacitor to be realized in a simple way.

Figure 8 shows an example of active matrix layout, which incorporates a storage capacitor.

In Figure 8 a second insulator layer 80 is provided between the cross over of the two metal layers, and this insulator layer extends over substantially all of the substrate, and is used to form a capacitor dielectric layer. The insulator layer 80 is continuous but has openings, for example to enable connection of the diodes to the metal of the row conductors.

The first layer deposited is the layer defining the row conductors 30,42, and this layer is also used to form a capacitor terminal 82. This material of the row conductors may be transparent, to provide a transparent capacitor terminal.

The second metal layer defines both in-plane electrode terminals 32,34 as well as the column conductors 46 (and a connection line 84 for the diode 40). This second metal layer is provided over the insulator layer. As shown in section A-A, the storage capacitor is formed from the layer of row metal underlying the crossover dielectric, and is formed as two capacitors in series between the two in-plane pixel electrode terminals. The capacitor dielectric is therefore effectively twice the crossover dielectric thickness. If desired, the capacitance can be increased by making a via from one of the pixel electrode terminals down to the capacitor metal, as this will effectively half the thickness of the dielectric layer (to the thickness of the crossover dielectric).

An issue may be that in the area of the storage capacitor the lateral field will be disturbed by the presence of the capacitor terminal under the inter-electrode space. One way to reduce this effect is to position the capacitor conductor to one side of the pixel.

The only patterning of capacitor/crossover dielectric layer 80, which is required, is to make holes for the diodes to fit in. This patterning does not require very accurate dimensions or alignment, making it compatible with the roll-to-roll process.

In the layout of Figure 8, the storage capacitor is formed as a single structure from the first (row) metal layer separated by the crossover dielectric from the pixel electrodes. If for any reason the pixel electrodes are short circuited via the storage capacitor, then the pixel will stop functioning. This may be the result of localized defects in the dielectric layer. If one defect causes one in-plane electrode terminal to be shorted to the capacitor terminal, and another defect causes the other in-plane electrode terminal to be shorted to the capacitor terminal, the pixel will be short-circuited.

Figure 9 shows a modification to the capacitor terminal 82, in which the terminal is formed as a number of pads which extend between adjacent comb lines of the two in-plane electrode terminals. These pads extend between and beneath the adjacent pairs of comb lines. If there is a localized defect in the dielectric layer, this will result in a short between one pad of the capacitor terminal 82 and one in-plane electrode terminal. However, this short circuit will be localized, as the pads of the capacitor terminal 82 are not connected together. In this case, only short circuits in two adjacent parts of the dielectric layer will cause a short circuit between the electrode terminals.

The examples above have the intermediate capacitor terminal formed as the first layer. It is also possible for the capacitor terminal to provided at the top of the structure.

The examples above use two in-plane electrodes to control the movement of particles. It is also possible to introduce additional control terminals. For example, a third control terminal can be provided between the two other terminals and can be used to halt the movement of particles, once a desired grey level has been achieved. Alternatively, an additional control terminal can be used to accelerate the movement of particles so that addressing can be achieved more rapidly. There may, for example, be a high voltage control terminal and a low voltage control terminal.

With reference to Figure 4, an additional control terminal may be provided between the terminals 32 and 34, and can be used to halt the movement of particles between the terminals.

The additional control terminals may also be situated on a second substrate, situated opposite to the first substrate. In this case, the use of additional control terminals can also enable a hybrid system to be developed which combines in-plane switching with orthogonal switching. The particles can then be moved to locations adjacent the in-plane electrodes at one vertical position within the material layer, or to locations randomly dispersed and at another vertical position within the material layer.

The additional, third, electrode may be connected to an associated row or column conductor by a further associated diode device. In all of the examples above, the select or scanning electrode (which defines the pixels being addressed at any time) is defined as a column electrode, whilst the data electrodes (which provide the information to the pixel) are considered to be the row electrodes. In alternative arrangements, the select and data electrodes could be chosen to be differently oriented, for example in the column and row directions respectively, or even in a honeycomb arrangement without altering the electrical operation of the pixel circuit. Thus, the invention is intended to cover this possibility.

The examples above relate to an electrophoretic display device. The invention can be used in other in-plane switching devices for active matrix addressing, for example IPS LC displays. The mere fact that certain measures are mentioned in different claims below does not indicate that a combination of these measures cannot be used to advantage.

Electrophoretic display systems can form the basis of a variety of applications where information may be displayed, for example in the form of information signs, public transport signs, advertising posters, pricing labels, billboards etc. In addition, they may be used where a changing non-information surface is required, such as wallpaper with a changing pattern or colour, especially if the surface requires a paper like appearance.

Various modifications will be apparent to those skilled in the art.

Claims

CLAIMS:

1. An active matrix device, comprising an array of rows and columns of pixels disposed over a common substrate, each pixel comprising: a portion of a row conductor (30), the row conductor extending past all the pixels of a row; a first electrode pattern (32) including a first in-plane electrode terminal; a first diode device (36) defined at a first cross over between the row conductor portion (30) and a second conductor portion (38), the second conductor portion (38) being connected electrically to the first in-plane electrode terminal (32); a portion of a reset conductor (42); a second diode device (40) defined at a second cross over between portions of the layer defining the row conductor portions and the layer defining the second conductor portions, and connected electrically between the first in-plane electrode terminal (32) and the reset conductor portion (42); a portion of a column conductor (46), the column conductor extending past all the pixels of a column; a second electrode pattern (34) including a second in-plane electrode terminal formed from the same layer as the first in-plane electrode terminal, and electrically connected to the column conductor portion (46).

2. A device as claimed in claim 1, wherein the reset conductor (42) extends in the row or column direction past a respective row or column of pixels.

3. A device as claimed in any preceding claim, wherein all of said conductor portions (30,38,42) and electrode patterns (32,34) are formed from two layers, the layer defining the in-plane electrode terminals being defined before the other layer.

4. A device as claimed in claim 3, wherein each pixel further comprises an insulator portion (48) at a crossing of the row conductor portion (30) and the column conductor portion (46).

5. A device as claimed in any preceding claim, wherein the first in-plane pixel electrode terminal comprises a comb pattern.

6. A device as claimed in claim 5, wherein the second in-plane pixel electrode terminal comprises a comb pattern.

7. A device as claimed in any preceding claim, wherein the in-plane electrode terminals are formed from the same layer as the second conductor portion (38) .

8. A device as claimed in any preceding claim, wherein the column conductor portions (46) and the in-plane electrode terminals are formed from the same layer as the second conductor portion (38).

9. A device as claimed in any one of claims 1 to 6, wherein the in-plane pixel electrode terminals and the row conductors (30) are formed from a common metal layer.

10. A device as claimed in claim 9, wherein the first in-plane electrode terminals comprise substantially parallel comb lines, and wherein the first electrode pattern further comprises a substantially perpendicular connecting portion connecting the parallel comb lines, defined by the second conducting portion (38).

11. A device as claimed in claim 10, wherein the second in-plane electrode terminals comprise comb lines substantially parallel to the comb lines of the first in-plane electrode terminal, and wherein the column conductor portions connect the parallel comb lines of the second in-plane electrode terminal and are formed from the layer of the second conducting portions.

12. A device as claimed in claim 11, wherein the common metal layer of the in- plane electrode terminals and the row conductors is disposed over the substrate, the first and second diode devices (36,40) are disposed over respective portions of the common metal layer, and the column conductor portions (46) and connecting portions (38) are disposed over the diode devices.

13. A device as claimed in claim 11 or 12, wherein the column conductors (46) and the connecting portions (38) cross over the respective comb lines, the comb lines thereby extending beyond the location of the column conductors and the connecting portions.

14. A device as claimed in any one of claims 9 to 13, wherein the common metal layer is formed from an array of substantially parallel lines.

15. A device as claimed in claim 14, wherein the column conductors (46) and the connecting portions (38) are formed from a further common metal layer comprising an array of parallel lines.

16. A device as claimed in claim 15, wherein the lines of the further common metal layer are substantially perpendicular to the parallel lines of the common metal layer.

17. A device as claimed in any preceding claim, wherein all conductors in any single layer of the layers forming the row conductors (30), the reset conductors (42), the first electrode patterns (32), the column conductors (46) and the second electrode patterns (34), are formed from substantially parallel lines.

18. A device as claimed in any preceding claim, wherein each diode device

(36,40) is provided within an insulator island (60).

19. A device as claimed in any preceding claim, wherein at least one of the diode devices comprises at least two diodes (70) in series.

20. A device as claimed in any preceding claim, wherein at least one of the diode devices comprises at least two diodes (72) in parallel.

21. A device as claimed in any preceding claim, wherein each pixel further comprises a capacitor terminal (82).

22. A device as claimed in claim 21, wherein the capacitor terminal (82) of each pixel provides a capacitive coupling between the first and second in-plane electrode terminals.

23. A device as claimed in claim 21 or 22, wherein the row conductor portions (30) are disposed over the substrate, wherein the first in-plane pixel electrode terminals, the column conductors (46), the second in-plane pixel electrode terminals and the second conductor portions (38) are all formed from a common metal layer, and wherein the layer of the row conductor portions (30) further defines an array of capacitor terminals, with a capacitor terminal (82) for each pixel.

24. A device as claimed in claim 23, wherein each capacitor terminal (82) comprises a plurality of non-connected sub-terminals, each sub-terminal being associated with a respective pair of comb lines of the first and second in-plane electrode terminals.

25. A device as claimed in any preceding claim, comprising an electrophoretic active matrix device.

26. A device as claimed in any preceding claim, comprising a display device.

27. A method of manufacturing an active matrix device, comprising an array of rows and columns of pixels disposed over a common substrate, the method comprising forming, over the substrate, and using first and second layers: a row conductor array (30); a reset conductor array (42); an array of first electrode patterns (32) each including a first in-plane electrode terminal and an array of second electrode patterns (34) each including a second in-plane electrode terminal, the first and second in-plane electrode terminals being formed from the same layer; and a column conductor array (46) and an array of second conductor portions (38) formed from the same layer, the second conductor portions (38) connected electrically to the first in-plane electrode terminals and the column conductors (46) electrically connected to the second in-plane electrode terminals, the method comprising forming first and second diode devices (36,40) at respective cross-overs between the portions of the first and second layers, the first diode device (36) being connected between the row conductor (30) and the first in-plane electrode terminal and the second diode device (40) being connected electrically between the reset conductor (42) and the first in-plane electrode terminal.

28. A method as claimed in claim 27, further comprising forming an insulator portion (48) between the overlap of the row conductors (30) and the column conductors (46).

29. A method as claimed in claim 27 or 28, wherein the column conductors (46) and the second in-plane electrode terminals are formed from the same layer.

30. A method as claimed in claim 27 or 28, wherein the first in-plane pixel electrode terminals, the row conductors and the second in-plane pixel electrode terminals are all formed from the same layer.

31. A method as claimed in claim 30, wherein the first in-plane electrode terminals are defined as substantially parallel comb lines formed from one of the layers, and wherein the first electrode pattern further comprises substantially perpendicular connecting portions (38) connecting the parallel comb lines, and formed from the other of the layers.

32. A method as claimed in claim 31 , wherein the second in-plane electrode terminals comprise comb lines substantially parallel to the comb lines of the first in-plane electrode terminals and formed from the same layer, and wherein the column conductors connect the parallel comb lines of the second in-plane electrode terminal and are formed from said other of the layers.

33. A method as claimed in claims 27 to 32, wherein the first and second layers are each formed as an array of substantially parallel lines.

34. A method as claimed in claim 33, wherein the parallel lines of the first common layer are formed substantially perpendicular to the parallel lines of the second common layer.

35. A method as claimed in any one of claims 27 to 34, wherein the method further comprises forming an array of capacitor terminals (82) from the layers not used to form the array of first and second in-plane electrode terminals, and wherein the method further comprises providing a dielectric in the spacing between the layers at least in the area of the capacitor terminals.