[go: up one dir, main page]

WO2006066962A3 - Selective oxidation and selective etching of allnn layers for manufacturing group iii nitride semiconductor devices - Google Patents

Selective oxidation and selective etching of allnn layers for manufacturing group iii nitride semiconductor devices Download PDF

Info

Publication number
WO2006066962A3
WO2006066962A3 PCT/EP2005/013966 EP2005013966W WO2006066962A3 WO 2006066962 A3 WO2006066962 A3 WO 2006066962A3 EP 2005013966 W EP2005013966 W EP 2005013966W WO 2006066962 A3 WO2006066962 A3 WO 2006066962A3
Authority
WO
WIPO (PCT)
Prior art keywords
group iii
allnn
layers
selective
semiconductor devices
Prior art date
Application number
PCT/EP2005/013966
Other languages
French (fr)
Other versions
WO2006066962A2 (en
Inventor
Hans-Joerg Buehlmann
Julien Dorsaz
Jean-Francois Carlin
Original Assignee
Ecole Polytech
Hans-Joerg Buehlmann
Julien Dorsaz
Jean-Francois Carlin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytech, Hans-Joerg Buehlmann, Julien Dorsaz, Jean-Francois Carlin filed Critical Ecole Polytech
Publication of WO2006066962A2 publication Critical patent/WO2006066962A2/en
Publication of WO2006066962A3 publication Critical patent/WO2006066962A3/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241III-V semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method for including an oxide region in a layered structure being grown epitaxially on a substrate, comprising the steps of epitaxially forming a Group III-nitride precursor layer, and selectively oxidizing the precursor layer, thereby forming the oxide region.
PCT/EP2005/013966 2004-12-24 2005-12-23 Selective oxidation and selective etching of allnn layers for manufacturing group iii nitride semiconductor devices WO2006066962A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63902604P 2004-12-24 2004-12-24
US60/639,026 2004-12-24

Publications (2)

Publication Number Publication Date
WO2006066962A2 WO2006066962A2 (en) 2006-06-29
WO2006066962A3 true WO2006066962A3 (en) 2007-03-29

Family

ID=36602113

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/013966 WO2006066962A2 (en) 2004-12-24 2005-12-23 Selective oxidation and selective etching of allnn layers for manufacturing group iii nitride semiconductor devices

Country Status (1)

Country Link
WO (1) WO2006066962A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2454655A (en) * 2007-11-09 2009-05-20 Sharp Kk Nitride structures with AlInN current confinement layers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1235279A2 (en) * 2001-02-27 2002-08-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device using nitride compound and method for fabricating the same
US20040188693A1 (en) * 2003-03-25 2004-09-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1235279A2 (en) * 2001-02-27 2002-08-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device using nitride compound and method for fabricating the same
US20040188693A1 (en) * 2003-03-25 2004-09-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same

Also Published As

Publication number Publication date
WO2006066962A2 (en) 2006-06-29

Similar Documents

Publication Publication Date Title
WO2005050716A3 (en) High-temperature devices on insulator substrates
WO2007058715A3 (en) Method of fabricating a silicon nitride stack
WO2004059751A3 (en) Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
WO2005114719A3 (en) Method of forming a recessed structure employing a reverse tone process
WO2006110204A3 (en) Thick semi-insulating or insulating epitaxial gallium nitride layers and devices incorporating same
WO2009055572A4 (en) Semiconductor structure and method of manufacture
WO2010151857A3 (en) Method for forming iii-v semiconductor structures including aluminum-silicon nitride passivation
WO2009031858A3 (en) Semiconductor light emitting device and method of fabricating the same
EP1235279A3 (en) Semiconductor device using nitride compound and method for fabricating the same
WO2007002028A3 (en) Layer growth using metal film and/or islands
WO2003034560A1 (en) Method for fabricating semiconductor light emitting element, semiconductor light emitting element, method for fabricating semiconductor element, semiconductor element, method for fabricating element and element
TW200612484A (en) Etch stop structure and method of manufacture, and semiconductor device and method of manufacture
TW200618432A (en) Semiconductor device and semiconductor device manufacturing method
TW200741959A (en) A die and method fabricating the same
WO2009082121A3 (en) Semiconductor light emitting device and method of fabricating the same
EP2144278A3 (en) Method of fabricating a quantum well structure
WO2006037933A3 (en) Method for providing mixed stacked structures, with various insulating zones and/or electrically conducting zones vertically localized
TW200620537A (en) Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
WO2007025277A3 (en) Methods for dual metal gate complementary metal oxide semiconductor integration
WO2008111518A1 (en) Method for forming nitride semiconductor laminated structure and method for manufacturing nitride semiconductor element
CA2475966A1 (en) Crystal production method
TW200603272A (en) Semiconductor device and method for fabricating the same
WO2007076250A3 (en) Semiconductor device fabricated using sublimation
WO2010098606A3 (en) Method for fabricating light emitting device
WO2005106985A3 (en) Improved substrate buffer structure for group iii nitride devices

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: COMMUNICATION PURSUANT TO RULE 69(1) EPC (FORM 1205A OF 31.08.07)

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 05826463

Country of ref document: EP

Kind code of ref document: A2

122 Ep: pct application non-entry in european phase

Ref document number: 05826463

Country of ref document: EP

Kind code of ref document: A2