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WO2005086370A1 - Method and apparatus for code tracking in code division multipe access (cdma) systems - Google Patents

Method and apparatus for code tracking in code division multipe access (cdma) systems Download PDF

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Publication number
WO2005086370A1
WO2005086370A1 PCT/US2004/005628 US2004005628W WO2005086370A1 WO 2005086370 A1 WO2005086370 A1 WO 2005086370A1 US 2004005628 W US2004005628 W US 2004005628W WO 2005086370 A1 WO2005086370 A1 WO 2005086370A1
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Prior art keywords
error signal
samples
loop
integral
sample
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PCT/US2004/005628
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French (fr)
Inventor
Wen Gao
Zoran Kostic
Alton Shelbourne Keel
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Thomson Licensing S.A.
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Priority to PCT/US2004/005628 priority Critical patent/WO2005086370A1/en
Publication of WO2005086370A1 publication Critical patent/WO2005086370A1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7073Synchronisation aspects
    • H04B1/7085Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop

Definitions

  • the present invention generally relates to wireless Code Division Multiple Access (CDMA) systems and, more particularly, to code tracking in CDMA systems.
  • CDMA Code Division Multiple Access
  • code tracking is an important synchronization procedure in receivers.
  • UMTS Universal Mobile Telecommunications System
  • the Common Pilot CHannel (CPICH) pilot signal is used for code tracking. Processing of the CPICH pilot signal enables the receiver to maintain the code synchronization between the transmitter scrambling code sequence and the local scrambling code sequence.
  • the code tracking is accomplished using delay-lock loop techniques. In a delay-lock code tracking loop, the local scrambling code sequence correlates with two versions of the received signal, where one version of the received signal is less than or equal to one chip earlier than the other version of the received signal.
  • the two versions of the received signal are referred to as the early branch and the late branch.
  • the outcomes of the two correlation operations are subjected to a subtraction operation and further filtered to generate an error signal for the delay-lock code tracking loop.
  • the quality of the error signal directly affects the performance of the delay-lock code tracking loop. Accordingly, the way in which the error signal is generated is an important issue in the loop design.
  • the correlation results from the early and late branch are subtracted and filtered using a first-order or second-order loop filter to generate the error signal.
  • this type of error signal usually has a large variation, even after the following filtering operation and, thus, makes the code-track loop unstable. Accordingly, it would be desirable and highly advantageous to have delay-lock loops for code synchronization in CDMA systems that overcome the above-described problems of the prior art.
  • the present invention is directed to code tracking in Code Division Multiple Access (CDMA) systems.
  • CDMA Code Division Multiple Access
  • a method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system Sign information relating to phase differences between samples of a received code sequence is accumulated. The accumulated sign information is compared against adaptable threshold levels. The loop error signal is generated when at least one of the adaptable threshold levels is satisfied.
  • a method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system there is provided.
  • FIG. 1 is a diagram illustrating a delay-lock code tracking loop 300 for a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention
  • FIG. 2 is a diagram illustrating a method 200 for code tracking in a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention.
  • the present invention is directed to a robust delay-lock loop for code synchronization in Code Division Multiple Access (CDMA) systems.
  • the delay-lock loop of the present invention can accommodate the channel distortion effects of the wireless channel used in CDMA systems.
  • the channel distortion effects accommodated by the present invention include, but are not limited to, fading, which undesirably changes the phase and the magnitude of the received signal.
  • the delay-lock loop of the present can advantageously mitigate the undesirable effects of the channel distortion on the behavior of the hardware components in a CDMA receiver.
  • the undesirable effects mitigated by the present invention include, but are not limited to, the generation of frequencies that are not exactly the same as the frequency of the transmitter.
  • CDMA systems to which the present invention may be applied include, but are not limited to, Universal Mobile Telecommunications Systems. It is to be understood that the present invention may be implemented in various forms of hardware, software, firmware, special purpose processors, or a combination thereof. Preferably, the present invention is implemented as a combination of hardware and software. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage device. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (CPU), a random access memory (RAM), and input/output (I/O) interface(s). The computer platform also includes an operating system and microinstruction code.
  • CPU central processing units
  • RAM random access memory
  • I/O input/output
  • the received signal is usually sampled by an Analog-to-Digital Converter (ADC) at a rate that is equal to or higher than two times the chip rate.
  • ADC Analog-to-Digital Converter
  • the sample rate is two, four, or eight times that of the chip rate.
  • a sample rate equal to eight times the chip rate is used to illustrate the invention.
  • the present invention is not limited to the samples rates used and disclosed herein and, thus, other sample rates may also be employed while maintaining the spirit of the present invention.
  • FIG. 1 is a diagram illustrating a delay-lock code-tracking loop 300 for a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a method for code tracking in a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention.
  • the delay-lock code-tracking loop 300 includes a receiver sample buffer 302, an arithmetic module 304, an accumulator and decimator 306, a Low Pass Filter (LPF) 308, a gain module 310, a timing controller 312, a local scrambling code generator 370, multipliers 380, and integrators 390.
  • the sample buffer 302 stores a plurality of filtered samples 100 that correspond to a signal received by a CDMA receiver.
  • the received signal includes a non-locally generated scrambling code sequence (generated at the transmitter) that is to be correlated with a locally generated scrambling code sequence output from the local scrambling code generator 370.
  • the received signal is sampled by, e.g., an Analog-to-Digital Converter (ADC), and filtered by, e.g., a pulse shaping filter, prior to the samples 100 of the received signal being stored in the sample buffer 302.
  • ADC Analog-to-Digital Converter
  • the filtered samples 100 from the buffer 302 are synchronized with a locally generated scrambling code sequence generated by the local scrambling code generator 370.
  • the phase of the received signal to which the samples correspond may vary due to the Doppler effect or the variation of the transmitter or local oscillator (not shown) that generate the timing of the scrambling code sequence.
  • the code-tracking loop is needed to track this variation and maintain the synchronization between the received scrambling code sequence and the local scrambling code sequence.
  • the local scrambling code sequence (generated by the local scrambling code generator 370) is correlated with the two versions of the received signal, i.e., the early (Tc/8 Early) and late (Tc/8 Late) branch signals, at the chip rate.
  • the early and late branch signals are the samples in the buffer 302 that occur "Tc/8 Early” and "Tc/8 Late” with respect to the on-time sample.
  • Samples Tc/8 Early and Tc/8 Late are denoted as R n] and R ⁇ n], respectively, where n is the index of the samples in the chip rate.
  • the integration time which is also referred to as the code tracking dwell time, is denoted as ⁇ / D . If the local scrambling code sequence is denoted as then the sample error signal e[m] is obtained as follows:
  • n n--i ⁇ [m] R E [mN D + n]Sc[mN D + n] - T R mN D + n]Sc[mN D + n]
  • m is an index for the sample error signal e[m]. It is to be appreciated that the arithmetic module 304 performs subtraction (early sample minus late sample) and so forth, as necessary to compute the sample error signal e[m]. It is to be further appreciated that while separate multipliers 380 and integrators 390 are shown in the loop 300, the arithmetic module 304 may perform these and other functions necessary for computation of the sample error signal e[m] and for proper operation of the loop 300.
  • the on time sample which is not needed by the arithmetic unit 304 to compute the sample error signal e[m], is provided to a demodulation block (not shown, as it is not part of the loop 300) for demodulation.
  • the sample error signal e[m] is noisy and its magnitude and phase may have large variations due to the fading effect in the wireless channel. This is generally the case even though the timing between the received code sequence and local scrambling code sequence is the same.
  • the present invention advantageously extracts the sign value (step 202) from the sample error signal e[m], for use in maintaining code synchronization between the received scrambling code sequence and the local scrambling code sequence.
  • the accumulator value Acc[m] that is output from the accumulator and decimator 306 is compared against two thresholds (+a and -b) (step 206). If one of the thresholds is satisfied, then a loop error signal is generated and the accumulator value ACC is reset to zero (step 208).
  • a positive constant loop error signal +X is generated. If the accumulator value ACC is less than the threshold -b, then a negative constant loop error signal -y is generated.
  • the comparison step and the generation of the error signal are both performed by the accumulator and decimator 306.
  • a separate comparator may be disposed in between the accumulator and decimator 306 and the LPF 308 to perform the comparing and generating steps. In the case that the thresholds are not satisfied, then the accumulator and decimator 306 continues to accumulate values without resetting. It is to be noted that the values +x and -y act as gains in the loop 300.
  • the accumulator and decimator 306 in addition to performing accumulation, also performs decimation.
  • the decimator for every f (threshold) input samples, the decimator is reset to zero, and at the same interval, the output of the buffer 302 is passed as a loop error signal to the LPF 308.
  • the LPF 308 In this case, as opposed to the previously described one, there are no fixed gains +x and -y that need to be additionally determined. Moreover, in this case, there are no thresholds +a and -b that need to be applied.
  • a decimator having a certain input rate will correspondingly have a reduced output rate, with each input symbol or bit being "stretched” or repeated at the output to form a continuous output at the reduced rate.
  • the accumulator and decimator 306 performs both accumulation and decimation, in contrast to other embodiments wherein the accumulator and decimator 306 is simply an accumulator that performs accumulation but not decimation.
  • the threshold values +a, -b and the constant loop error signals +x, -y can be adjusted to change the code-tracking loop characteristics. These adjustments can take place during the calibration of the receiver, or can be adaptively changed based on the values of the channel Doppler and other parameters.
  • the threshold values +a, -b and the constant loop error signals +x, -y are most often chosen experimentally such that the bandwidth and response of the control loop can properly track the behavior of the channel and the receiver components.
  • the loop error signal (either +x or -y when decimation is not employed or the output of the buffer 302 when decimation is employed) is further passed into the LPF 308 to limit the noise in the signal (step 210).
  • the output of the LPF 308, as scaled by the gain module 310, is used by the timing controller 312 to adjust the position in the high-speed buffer 302 from which the early, late and on time branch samples are retrieved.
  • the adjustment of the position is computed by properly scaling the output of the LPF 308 via the gain module 310 such that the obtained value represents the sample index n pointing to the right location in the sample buffer 302 for early and late samples.
  • the scaling is done by setting the gains in the loop.
  • the LPF 308 is usually a low pass filter.
  • the commonly used loop filter is a second order low pass filter, as follows:
  • ⁇ and ⁇ are the filter coefficients
  • l[n] is the integral part of the filter
  • ⁇ *e[n] is the proportional
  • out[n] is the loop filter output .
  • the positions in the buffer 302 from which the samples are retrieved are adjusted by the timing controller 312 based on an output of the LPF 308 (step 212).
  • the output of the LPF 308 is scaled such that the obtained value represents the offset from the sample index pointing to the right location in the sample buffer for early and late samples. Scaling is performed by setting the gains in the gain module

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Abstract

There is provided a method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system. Sign information relating to phase differences between samples of a received code sequence is accumulated. The accumulated sign information is compared against adaptable threshold levels. The loop error signal is generated when at least one of the adaptable threshold levels is satisfied.

Description

METHOD AND APPARATUS FOR CODE TRACKING IN CODE DIVISION MULTIPLE ACCESS (CDMA) SYSTEMS
BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention generally relates to wireless Code Division Multiple Access (CDMA) systems and, more particularly, to code tracking in CDMA systems.
BACKGROUND OF THE INVENTION In communication systems, code tracking is an important synchronization procedure in receivers. For example, in Universal Mobile Telecommunications System (UMTS) cellular systems, after the slot synchronization, frame synchronization and the identification of the scrambling code used in the cell has been accomplished, the Common Pilot CHannel (CPICH) pilot signal is used for code tracking. Processing of the CPICH pilot signal enables the receiver to maintain the code synchronization between the transmitter scrambling code sequence and the local scrambling code sequence. The code tracking is accomplished using delay-lock loop techniques. In a delay-lock code tracking loop, the local scrambling code sequence correlates with two versions of the received signal, where one version of the received signal is less than or equal to one chip earlier than the other version of the received signal. For convenience, the two versions of the received signal are referred to as the early branch and the late branch. The outcomes of the two correlation operations are subjected to a subtraction operation and further filtered to generate an error signal for the delay-lock code tracking loop. The quality of the error signal directly affects the performance of the delay-lock code tracking loop. Accordingly, the way in which the error signal is generated is an important issue in the loop design. In a conventional delay-lock loop, the correlation results from the early and late branch are subtracted and filtered using a first-order or second-order loop filter to generate the error signal. However, due the severe fading effect in wireless channels, this type of error signal usually has a large variation, even after the following filtering operation and, thus, makes the code-track loop unstable. Accordingly, it would be desirable and highly advantageous to have delay-lock loops for code synchronization in CDMA systems that overcome the above-described problems of the prior art.
SUMMARY OF THE INVENTION The problems stated above, as well as other related problems of the prior art, are solved by the present invention, which is directed to code tracking in Code Division Multiple Access (CDMA) systems. According to an aspect of the present invention, there is provided a method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system. Sign information relating to phase differences between samples of a received code sequence is accumulated. The accumulated sign information is compared against adaptable threshold levels. The loop error signal is generated when at least one of the adaptable threshold levels is satisfied. According to another aspect of the present invention, there is provided a method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system. Sign information relating to phase differences between samples of a received code sequence is accumulated. The accumulated sign information is decimated. An output of the decimating step is utilized as the loop error signal for the delay-lock code tracking loop. These and other aspects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a delay-lock code tracking loop 300 for a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention; and FIG. 2 is a diagram illustrating a method 200 for code tracking in a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a robust delay-lock loop for code synchronization in Code Division Multiple Access (CDMA) systems. Advantageously, the delay-lock loop of the present invention can accommodate the channel distortion effects of the wireless channel used in CDMA systems. The channel distortion effects accommodated by the present invention include, but are not limited to, fading, which undesirably changes the phase and the magnitude of the received signal. Moreover, the delay-lock loop of the present can advantageously mitigate the undesirable effects of the channel distortion on the behavior of the hardware components in a CDMA receiver. The undesirable effects mitigated by the present invention include, but are not limited to, the generation of frequencies that are not exactly the same as the frequency of the transmitter. CDMA systems to which the present invention may be applied include, but are not limited to, Universal Mobile Telecommunications Systems. It is to be understood that the present invention may be implemented in various forms of hardware, software, firmware, special purpose processors, or a combination thereof. Preferably, the present invention is implemented as a combination of hardware and software. Moreover, the software is preferably implemented as an application program tangibly embodied on a program storage device. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (CPU), a random access memory (RAM), and input/output (I/O) interface(s). The computer platform also includes an operating system and microinstruction code. The various processes and functions described herein may either be part of the microinstruction code or part of the application program (or a combination thereof) that is executed via the operating system. In addition, various other peripheral devices may be connected to the computer platform such as an additional data storage device and a printing device. It is to be further understood that, because some of the constituent system components and method steps depicted in the accompanying Figures are preferably implemented in software, the actual connections between the system components (or the process steps) may differ depending upon the manner in which the present invention is programmed. Given the teachings herein, one of ordinary skill in the related art will be able to contemplate these and similar implementations or configurations of the present invention. In a CDMA receiver (such as, e.g., a UMTS cellular receiver), the received signal is usually sampled by an Analog-to-Digital Converter (ADC) at a rate that is equal to or higher than two times the chip rate. The higher the sample rate, the finer the obtained code tracking resolution. Usually, the sample rate is two, four, or eight times that of the chip rate. In the following example, a sample rate equal to eight times the chip rate is used to illustrate the invention. However, it is to be appreciated that the present invention is not limited to the samples rates used and disclosed herein and, thus, other sample rates may also be employed while maintaining the spirit of the present invention. After passing through a pulse-shaping filter (such as, e.g., a root raised cosine filter), the samples are fed into a high-speed sample buffer (also known as a "match filter") with a clock rate at eight times the chip rate. The sample buffer provides a way to conveniently access the received samples with different delays. FIG. 1 is a diagram illustrating a delay-lock code-tracking loop 300 for a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention. FIG. 2 is a diagram illustrating a method for code tracking in a Code Division Multiple Access (CDMA) system, according to an illustrative embodiment of the present invention. The delay-lock code-tracking loop 300 includes a receiver sample buffer 302, an arithmetic module 304, an accumulator and decimator 306, a Low Pass Filter (LPF) 308, a gain module 310, a timing controller 312, a local scrambling code generator 370, multipliers 380, and integrators 390. The sample buffer 302 stores a plurality of filtered samples 100 that correspond to a signal received by a CDMA receiver. The received signal includes a non-locally generated scrambling code sequence (generated at the transmitter) that is to be correlated with a locally generated scrambling code sequence output from the local scrambling code generator 370. As noted above, the received signal is sampled by, e.g., an Analog-to-Digital Converter (ADC), and filtered by, e.g., a pulse shaping filter, prior to the samples 100 of the received signal being stored in the sample buffer 302. The filtered samples 100 from the buffer 302 are synchronized with a locally generated scrambling code sequence generated by the local scrambling code generator 370. However, the phase of the received signal to which the samples correspond may vary due to the Doppler effect or the variation of the transmitter or local oscillator (not shown) that generate the timing of the scrambling code sequence. Hence, the code-tracking loop is needed to track this variation and maintain the synchronization between the received scrambling code sequence and the local scrambling code sequence. In the delay-lock code-tracking loop 300, the local scrambling code sequence (generated by the local scrambling code generator 370) is correlated with the two versions of the received signal, i.e., the early (Tc/8 Early) and late (Tc/8 Late) branch signals, at the chip rate. The early and late branch signals are the samples in the buffer 302 that occur "Tc/8 Early" and "Tc/8 Late" with respect to the on-time sample. Samples Tc/8 Early and Tc/8 Late are denoted as R n] and R^n], respectively, where n is the index of the samples in the chip rate. The integration time, which is also referred to as the code tracking dwell time, is denoted as Λ/D. If the local scrambling code sequence is denoted as
Figure imgf000009_0001
then the sample error signal e[m] is obtained as follows:
N »„»--\■ N "nn--iι [m] = RE[mND + n]Sc[mND + n] - T R mND + n]Sc[mND + n]
where m is an index for the sample error signal e[m]. It is to be appreciated that the arithmetic module 304 performs subtraction (early sample minus late sample) and so forth, as necessary to compute the sample error signal e[m]. It is to be further appreciated that while separate multipliers 380 and integrators 390 are shown in the loop 300, the arithmetic module 304 may perform these and other functions necessary for computation of the sample error signal e[m] and for proper operation of the loop 300. The on time sample, which is not needed by the arithmetic unit 304 to compute the sample error signal e[m], is provided to a demodulation block (not shown, as it is not part of the loop 300) for demodulation. For the sake of brevity, further description of the performed demodulation is not provided, as demodulation is known to those of ordinary skill in the art. Typically, the sample error signal e[m] is noisy and its magnitude and phase may have large variations due to the fading effect in the wireless channel. This is generally the case even though the timing between the received code sequence and local scrambling code sequence is the same. Thus, instead of directly using e[m], the present invention advantageously extracts the sign value (step 202) from the sample error signal e[m], for use in maintaining code synchronization between the received scrambling code sequence and the local scrambling code sequence. The sign value of the sample error signal e[m], which is either equal to -1 or +1 , is accumulated in the accumulator and decimator 306 (step 204). That is, the current sign value of the sample error signal e[m] is added to the previous content (previous signal values of the sample error signal e[m]) in the accumulator and decimator 306. The accumulator value Acc[m] that is output from the accumulator and decimator 306 is compared against two thresholds (+a and -b) (step 206). If one of the thresholds is satisfied, then a loop error signal is generated and the accumulator value ACC is reset to zero (step 208). If the accumulator value ACC is greater than the threshold +a, then a positive constant loop error signal +X is generated. If the accumulator value ACC is less than the threshold -b, then a negative constant loop error signal -y is generated. The comparison step and the generation of the error signal are both performed by the accumulator and decimator 306. However, it is to be appreciated that in some embodiments of the present invention, a separate comparator may be disposed in between the accumulator and decimator 306 and the LPF 308 to perform the comparing and generating steps. In the case that the thresholds are not satisfied, then the accumulator and decimator 306 continues to accumulate values without resetting. It is to be noted that the values +x and -y act as gains in the loop 300. According to another embodiment of the present invention, the accumulator and decimator 306, in addition to performing accumulation, also performs decimation. In this case, for every f (threshold) input samples, the decimator is reset to zero, and at the same interval, the output of the buffer 302 is passed as a loop error signal to the LPF 308. In this case, as opposed to the previously described one, there are no fixed gains +x and -y that need to be additionally determined. Moreover, in this case, there are no thresholds +a and -b that need to be applied. As is known, a decimator having a certain input rate will correspondingly have a reduced output rate, with each input symbol or bit being "stretched" or repeated at the output to form a continuous output at the reduced rate. Thus, in this embodiment, the accumulator and decimator 306 performs both accumulation and decimation, in contrast to other embodiments wherein the accumulator and decimator 306 is simply an accumulator that performs accumulation but not decimation. The threshold values +a, -b and the constant loop error signals +x, -y can be adjusted to change the code-tracking loop characteristics. These adjustments can take place during the calibration of the receiver, or can be adaptively changed based on the values of the channel Doppler and other parameters. The threshold values +a, -b and the constant loop error signals +x, -y are most often chosen experimentally such that the bandwidth and response of the control loop can properly track the behavior of the channel and the receiver components. The loop error signal (either +x or -y when decimation is not employed or the output of the buffer 302 when decimation is employed) is further passed into the LPF 308 to limit the noise in the signal (step 210). The output of the LPF 308, as scaled by the gain module 310, is used by the timing controller 312 to adjust the position in the high-speed buffer 302 from which the early, late and on time branch samples are retrieved. The adjustment of the position is computed by properly scaling the output of the LPF 308 via the gain module 310 such that the obtained value represents the sample index n pointing to the right location in the sample buffer 302 for early and late samples. The scaling is done by setting the gains in the loop. The LPF 308 is usually a low pass filter. By way of example, the commonly used loop filter is a second order low pass filter, as follows:
i[n]= i[n-1] + β*e[n] out[n]=α*e[n]+i[n],
where α and β are the filter coefficients, l[n] is the integral part of the filter, α*e[n] is the proportional, and out[n] is the loop filter output . Those of ordinary skill in the art will recognize that other loop filters may be utilized without departing from the spirit of the present invention. The positions in the buffer 302 from which the samples are retrieved are adjusted by the timing controller 312 based on an output of the LPF 308 (step 212). The output of the LPF 308 is scaled such that the obtained value represents the offset from the sample index pointing to the right location in the sample buffer for early and late samples. Scaling is performed by setting the gains in the gain module
310. Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one of ordinary skill in the related art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.

Claims

1. A method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system, comprising the steps of: accumulating sign information relating to phase differences between samples of a received code sequence; comparing the accumulated sign information against adaptable threshold levels; and generating the loop error signal when at least one of the adaptable threshold levels is satisfied.
2. The method according to claim 1 , further comprising the steps of: calculating a first integral corresponding to a product of one of the samples and a scrambling code sequence; calculating a second integral corresponding to a product of a later received one of the samples and the scrambling code; and subtracting the second integral from the first integral to obtain the sign information.
3. The method according to claim 2, wherein each of the first integral and the second integral are calculated over a code tracking dwell time.
4. The method according to claim 1 , wherein said accumulating step accumulates the sign information from a sample error signal e[m], wherein e[m] is equal to
JVπ-l N„-l 2^ R£ [mND + n]Sc[mND + n] - RL [mND + n]Sc[mND + n] n=0 «=0
wherein RE and RL respectively represent an earlier occurring sample and a later occurring sample with respect to an on-time occurring sample, n is an index of the samples in a chip rate, No is a code tracking dwell time, Sc is a local scrambling code sequence, and m is an index of the sample error signal e[m].
5. The method according to claim 1 , wherein the predetermined threshold levels include a positive threshold and a negative threshold.
6. The method according to claim 5, wherein said generating step comprises the step of generating a positive constant loop error signal when the positive threshold is satisfied, and generating a negative constant loop error signal when the negative threshold level is satisfied.
7. The method according to claim 6, wherein the positive constant loop error signal and the negative constant loop error signal are used to control a gain of the delay-lock code tracking loop.
8. The method according to claim 1 , further comprising the step of utilizing values of the loop error signal to control a gain in the delay-lock code tracking loop.
9. The method according to claim 8, wherein the values of the loop error signal are constant values capable of being adjusted to control the gain in the delay- lock code tracking loop.
10. The method according to claim 1 , further comprising the step of utilizing the adaptable threshold levels to affect a bandwidth of the delay-lock code tracking loop.
11. The method according to claim 1 , wherein the delay-lock code tracking loop includes a receiver sample buffer from which the samples of the received code sequence may be retrieved with different delays, and the method further comprises the step of adjusting a position of the samples in the receiver sample buffer based on the loop error signal.
12. The method according to claim 11 , further comprising the step of filtering the loop error signal prior to said adjusting step.
13. An apparatus for generating an error signal for a delay-lock code tracking loop in a CDMA system, comprising: an accumulator for accumulating sign information relating to phase differences between samples of a received code sequence; a comparator for comparing the accumulated sign information against adaptable threshold levels; and an error signal generator for generating the error signal when at least one of the adaptable threshold levels is satisfied.
14. The apparatus according to claim 13, further comprising an arithmetic module for calculating a first integral corresponding to a product of one of the samples and a scrambling code sequence, calculating a second integral corresponding to a product of a later received one of the samples and the scrambling code, and subtracting the second integral from the first integral.
15. The apparatus according to claim 14, wherein each of the first integral and the second integral are calculated over a code tracking dwell time.
16. The apparatus according to claim 13, wherein said accumulator accumulates the sign information from a sample error signal e[m], wherein e[m] is equal to
+ n]Sc[mND + n]
Figure imgf000017_0001
wherein RE and RL respectively represent an earlier occurring sample and a later occurring sample with respect to an on-time occurring sample, n is an index of the samples in a chip rate, ND is a code tracking dwell time, Sc is a local scrambling code sequence, and m is an index for the sample error signal e[m].
17. The apparatus according to claim 13, wherein said error signal generator generates a positive constant error signal when the positive threshold is satisfied, and generates a negative constant error signal when the negative threshold level is satisfied.
18. The apparatus according to claim 17, wherein the positive constant error signal and the negative constant error signal are used to control a gain of the delay-lock code tracking loop.
19. The apparatus according to claim 13, further comprising a receiver sample buffer from which the samples of the received code sequence may be retrieved with different delays, and wherein positions of the samples in the buffer are adjusted based on the error signal.
20. The apparatus according to claim 19, further comprising a filter for filtering the error signal prior to adjusting the positions of the samples in the receiver sample buffer.
21. A method for generating a loop error signal for a delay-lock code tracking loop in a CDMA system, comprising the steps of: accumulating sign information relating to phase differences between samples of a received code sequence; decimating the accumulated sign information; and utilizing an output of said decimating step as the loop error signal for the delay- lock code tracking loop.
22. The method according to claim 21 , wherein the output of said decimating step is utilized as the loop error signal upon a decimation of a threshold number of the samples.
23. The method according to claim 22, further comprising the step of resetting the output of said decimating step at a same interval as when the output of said decimating step is utilized as the loop error signal.
24. The method according to claim 21 , further comprising the steps of: calculating a first integral corresponding to a product of one of the samples and a scrambling code sequence; calculating a second integral corresponding to a product of a later received one of the samples and the scrambling code; and subtracting the second integral from the first integral to obtain the sign information.
25. The method according to claim 24, wherein each of the first integral and the second integral are calculated over a code tracking dwell time.
26. The method according to claim 21 , wherein said accumulating step accumulates the sign information from a sample error signal e[m], wherein e[m] is equal to
Nn-\ Nn-l 2_JRE[mND + n]Sc[mND + ] - RL[mND + n]Sc[mND + n]
wherein RE and RL respectively represent an earlier occurring sample and a later occurring sample with respect to an on-time occurring sample, n is an index of the samples in a chip rate, ND is a code tracking dwell time, Sc is a local scrambling code sequence, and m is an index for the sample error signal e[m].
27. The method according to claim 21 , wherein the delay-lock code tracking loop includes a receiver sample buffer from which the samples of the received code sequence may be retrieved with different delays, and the method further comprises the step of adjusting a position of the samples in the receiver sample buffer based on the loop error signal.
28. The method according to claim 11 , further comprising the step of filtering the loop error signal prior to said adjusting step.
29. An apparatus for generating a loop error signal for a delay-lock code tracking loop in a CDMA system, comprising: an accumulator for accumulating sign information relating to phase differences between samples of a received code sequence; and a decimator for decimating the accumulated sign information, wherein an output of said decimator is utilized as the loop error signal for the delay-lock code tracking loop.
30. The apparatus according to claim 29, wherein the output of said decimator is utilized as the loop error signal upon a decimation of a threshold number of the samples.
31. The apparatus according to claim 30, wherein the output of said decimator is reset at a same interval as when the output of said decimator is utilized as the loop error signal.
32. The apparatus according to claim 29, further comprising an arithmetic module for calculating a first integral corresponding to a product of one of the samples and a scrambling code sequence, calculating a second integral corresponding to a product of a later received one of the samples and the scrambling code, and subtracting the second integral from the first integral.
33. The apparatus according to claim 32, wherein each of the first integral and the second integral are calculated over a code tracking dwell time.
34. The apparatus according to claim 29, wherein said accumulator accumulates the sign information from a sample error signal e[m], wherein e[m] is equal to
+ n]Sc[mN D + n]
Figure imgf000022_0001
wherein RE and RL respectively represent an earlier occurring sample and a later occurring sample with respect to an on-time occurring sample, n is an index of the samples in a chip rate, ND is a code tracking dwell time, Sc is a local scrambling code sequence, and m is an index for the sample error signal e[m].
35. The apparatus according to claim 29, further comprising a receiver sample buffer from which the samples of the received code sequence may be retrieved with different delays, and wherein positions of the samples in the buffer are adjusted based on the error signal.
36. The apparatus according to claim 35, further comprising a filter for filtering the error signal prior to adjusting the positions of the samples in the receiver sample buffer.
PCT/US2004/005628 2004-02-25 2004-02-25 Method and apparatus for code tracking in code division multipe access (cdma) systems WO2005086370A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063657A1 (en) * 2001-10-01 2003-04-03 Interdigital Technology Corporation Code tracking loop with automatic power normalization
WO2003093929A2 (en) * 2002-04-29 2003-11-13 Interdigital Technology Corporation Simple and robust digital code tracking loop for wireless communication systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030063657A1 (en) * 2001-10-01 2003-04-03 Interdigital Technology Corporation Code tracking loop with automatic power normalization
WO2003093929A2 (en) * 2002-04-29 2003-11-13 Interdigital Technology Corporation Simple and robust digital code tracking loop for wireless communication systems

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