WO2005057663A2

WO2005057663A2 - Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices

Info

Publication number: WO2005057663A2
Application number: PCT/IB2004/003992
Authority: WO
Inventors: Frédéric Salvetti; Etienne Robilliart; Alexandre Dray; François Wacquant; Damien Lenoble; Ramiro Palla
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-12-10
Filing date: 2004-12-03
Publication date: 2005-06-23
Anticipated expiration: 2006-06-10
Also published as: WO2005057663A3; TW200535923A

Abstract

A method of forming a semiconductor device, the method comprising sequentially forming on a semiconductor substrate (10), a gate structure (14) including a gate electrode layer (15) forming an upper surface of said gate structure, performing heavy impurity doping in portions (126) of said semiconductor substrate (10) not covered by said gate structure (14) to partially form source and drain regions of said semiconductor device, removing in a single step a first layer of substantially uniform thickness from the upper surface and sidewalls of said gate structure (14), performing light impurity doping in portions (124) of said semiconductor substrate (10) not covered by said gate structure (14) to complete said source and drain regions of said semiconductor device, removing in a single step a second layer of substantially uniform thickness from the upper surface and sidewalls of said gate structure (14), forming a spacer layer (125) on the sidewalls of said gate structure (14) and forming a silicide contact (28) on the upper surface of said gate structure (14).

Description

Method and Apparatus for Fabrication of Metal-oxide Semiconductor Integrated Circuit Devices

FIELD OF THE INVENTION This invention relates to a method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices, and in particular to a method and apparatus for fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuit devices of the lightly doped drain (LDD) type.

BACKGROUND OF THE INVENTION As feature sizes in CMOS devices decrease to the micron and submicron range, so- called short-channel effects arise which tend to limit device performance. For the n-channel transistors in such a device, the major limitation encountered is caused by hot-electron induced instabilities. To reduce these effects, LDD n-channel transistors have been proposed. For p-channel transistors in a short-channel CMOS device, the major limitation on performance stems from effects such as punch-through. To minimise this effect, relatively shallow junctions are required in the p-channel transistors. In prior art fabrication processes, disposable spacers made of various materials have been proposed as a basis for making LDD n-channel transistors in a CMOS device. Thus, for example, spacers made of polysilicon, silicon dioxide and silicon nitride have been proposed. As stated above, one technique used in semiconductor processing for reducing so- called hot-carrier effects in metal oxide semiconductor field effect transistors is the formation of lightly-doped drain (LDD) structures. In traditional LDD structures, the source/drain is formed by two implantation steps. The first of these implantations is a light-doping step that is self-aligned to the gate electrode. The second step is a heavy-doping step that is self- aligned to two oxide sidewall spacers previously formed adjacent the gate electrode. After the first light-dopant implantation step, sidewall spacers are formed to protect a portion of the lightly-doped substrate adjacent to the gate electrode during the subsequent heavy-doping implantation step. Although LDD structures are advantageous for reducing hot-carrier effects, traditional methods of forming these types of structures results in increased fabrication complexity and associated costs. In particular, formation of the traditional sidewall spacers requires several processing steps, for example, oxide deposition, etching and cleaning, that increase fabrication complexity and the time and costs associated with these steps.

SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a method and apparatus for fabricating a metal-oxide semiconductor integrated circuit device using a reduced number of process steps relative to prior art arrangements, and to provide a metal-oxide semiconductor integrated circuit device using such method and apparatus. Thus, in accordance with the present invention, there is provided a method of forming a semiconductor device, the method comprising the steps of forming a gate structure on a semiconductor substrate, performing heavy impurity doping in portions of said semiconductor substrate not covered by said gate structure so as to partially form source and drain regions of said semiconductor device, removing a first layer from an upper surface and sidewalls of said gate structure, performing light impurity doping in portions of said semiconductor substrate not covered by said gate structure to complete said source and drain regions of said semiconductor device, removing a second layer from the upper surface and sidewalls of said gate structure, forming a spacer layer on the sidewalls of said gate structure and forming a suicide contact on the upper surface of said gate structure. The present invention also extends to an apparatus for forming a semiconductor device according to the above-defined method, the apparatus comprising means for forming a gate structure on a semiconductor substrate, means for performing heavy impurity doping in portions of said semiconductor substrate not covered by said gate structure so as to partially form source and drain regions of said semiconductor device, means for removing a first layer from an upper surface and sidewalls of said gate structure, means for performing light impurity doping in portions of said semiconductor substrate not covered by said gate structure to complete said source and drain regions of said semiconductor device, means for removing a second layer from the upper surface and sidewalls of said gate structure, means for forming a spacer layer on the sidewalls of said gate structure and means for forming a suicide contact on the upper surface of said gate structure. The present invention extends still further to a semiconductor device manufactured in accordance with the method defined above. In one exemplary embodiment of the present invention, the step(s) of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure comprises an etching process, for example, an anisotropic reactive-ion-etching process. In another exemplary embodiment of the present invention, the step of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure comprises an oxidation process, beneficially coupled with gas implantation, preferably Argon and/or Nitrogen implantation. Beneficially, the step of removing a second layer from the upper surface and the sidewalls of the gate structure is followed by an annealing process. These and other aspects of the invention will be apparent from and will be elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in more detail, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a schematic illustration of the process flow of a fabrication process according to the prior art; - Figure 2 is a schematic illustration of the process flow of a fabrication process according to a first exemplary embodiment of the present invention; and Figure 3 is a schematic illustration of the process flow of a fabrication process according to a second exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION Referring to Figure la, a conventional integrated circuit device defined in a semiconductor wafer 10 made of silicon includes a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm). Overlying the dielectric layer 12 is a conventional heavily doped polysilicon gate 14. The exposed surface of the polysilicon gate 14 is provided with a silicon dioxide layer SiO 16 by, for example, a standard low-pressure chemical-vapour- deposition (LPCVD) process. Subsequently in, for example, a LPCVD step, a layer 18 of silicon nitride is deposited on the top surface of the structure. Next, in, for example, an anisotropic reactive-ion-etching (RIE) step, all of the nitride layer 18 is removed, except for the relatively thick, sloped wall portions 20. In addition, exposed portions of the underlying layer 16 are also thereby etched away, as shown in Figure lb. By way of example, this RIE step may be carried out by utilising a known plasma derived from a standard mixture of CO₂, CHF₃ and He. Such an etchant does not significantly affect the surface of the gate 14. Advantageously, the structure may then be subjected to a standard O₂ plasma, so as to remove from the surface of the gate 14 any polymer formed thereon during the etching step. At that point in the process flow, the structure appears as shown in Figure lb of the drawings. It will be appreciated that together each adjoining pair of nitride and oxide portions constitute an offset spacer 21. Next, a blanket implant step is performed to form the LDD portion 24 of the n- channel transistor. By way of example, this step may comprise implanting phosphorous ions at an energy of around, say, 50,000 to 70,000 electron volts, and the resultant structure is illustrated in Figure lc of the drawings. As shown in Figure Id, a spacer 25 is formed on the sidewall of each offset spacer 21, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14. Next, an ion implanting step is performed to form a doped region 26, and the doped region 26 and the LDD region 24 together form a source/drain region, as shown in Figure le of the drawings. Finally, self-aligned suicide contacts 28 are formed for the drain, source and gate of the device, as shown in Figure If. Thus, it will be appreciated that although the use of offset spacers in the fabrication of metal-oxide semiconductor integrated circuit devices has been shown to improve device performance, the main process steps involved in the fabrication of such offset spacers involves two material deposition steps (oxide and nitride) and two etching steps. In addition to the fact that the deposition temperature used during the fabrication process leads to undesired dopant diffusion, there are other disadvantages to the above-described process. For example, the fabrication of the offset spacers leads to four possible dispersion sources, whereas in order to ensure good process control, it is highly desirable to reduce dispersion. Moreover, with new technologies, it is crucial to achieve the shallowest possible junctions, to which over-diffusion of the dopant is not conducive. Finally, for throughput reasons, it is highly desirable to minimise the number of process steps, especially deposition steps, which are very time-consuming.

We have now devised an improved arrangement, which enables the use of a single etching step, as opposed to the two deposition steps and two etching steps of the above- described prior art process, without reduction in device performance.

Referring to Figure 2 of the drawings, a method of fabricating a semiconductor device according to a first exemplary embodiment of the invention is proposed. Said fabrication method is particularly advantageous for high dielectric permittivity gate oxide or metal gates comprising, for example, SiGe or TiN. Referring to Figure 2a of the drawings, once again, the process starts with a semiconductor wafer 10 made of silicon and including a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm). Said dielectric layer preferably includes a high dielectric permittivity layer (for example HfO₂). Overlying the dielectric layer 12 is a gate structure 14_including poly-silicon. In this case, however, the next step is an ion implanting step which is performed through the dielectric layer 12 to form a heavily doped region 126 and a gate electrode layer 15 on the top of the gate structure. The heavily doped region 126 partially forms a source/drain region. The ion implanting step is a conventional one comprising, for example, implanting Arsenic As ions at an energy of around 10 keV or Bore B ions at an energy of around 3 keV. The heavily doped region corresponds to a concentration of doping elements higher than a predetermined threshold which equals, in general, 10 atomes/cm . Referring to Figure 2b, next, the gate structure 14 including the gate electrode layer

15 is etched, by means of, for example, an anisotropic reactive-ion-etching (RIE) step, as referred to above, to expose a small peripheral portion of the gate structure 14. It is to be noted that the high dielectric permittivity layer is not etched by this RIE step. Said first etching step is thus adapted to remove in a single step a first layer, preferably of substantially uniform thickness, from the upper surface and sidewalls of the gate structure 14. As illustrated in Figure 2c, a blanket implant step is then performed through the dielectric layer 12 to form the LDD portion 124 of the n-channel transistor, which completes the source/drain region of the device. By way of example, once again, this step may comprise implanting phosphorous ions at an energy of around 50 to 70 keV. The lightly doped portion 124 corresponds to a concentration of doping elements much lower than a predetermined threshold which equals, in general, 10¹⁸ atomes/cm³. Next, the dielectric layer 12, except for the portion thereof covered by the gate structure 14, is removed by a second etching step, as is a further small peripheral portion, preferably of substantially uniform thickness, of the gate structure 14 including the gate electrode layer 15, and the resultant structure is illustrated in Figure 2d. As illustrated by Figure 2e, a relatively short annealing step at elevated temperatures is then carried out to fit the new atoms introduced by implantation into the substrate crystal lattice. The annealing step duration is, for example, lower than one second and is applied, for example, at a temperature equal to or higher than 1000°C. Said annealing step causes diffusion of the doping elements into the substrate (and into the gate) as illustrated by the arrows in Figure 2e. Finally, a spacer 125 is formed on the sidewalls of the polysilicon gate 14, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14, as illustrated in Figure 2f. Then self-aligned suicide contacts 28 are formed for the drain, source and gate of the device, as shown in Figure 2g, as before. Said suicides are, for example, of the CoSi₂ or NiSi₂ type. This spacer formation step is necessary to ensure good silicidation (i.e. no bridging). Another advantage of this approach is the resultant capability for implantation of further pockets after the second gate etching step, so the spacer can be accurately located relative to the LDD portions.

Referring to Figure 3 of the drawings, and more particularly to Figure 3a, in a second exemplary embodiment of the present invention, once again, the process starts with a semiconductor wafer 10 made of silicon and including a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm). Said dielectric layer includes, for example, an oxide (for example SiO₂), an oxy-nitride (for example SiO +Si3N₄) or a high dielectric permittivity material (for example HfO₂). Overlying the dielectric layer 12 is a gate structure 14 including poly-silicon. In this case, once again, the first step is an ion implanting step which is performed to form a heavily doped region 126 and a gate electrode layer 15 on the top of the gate structure. Said doped region 126 partially forms a source/drain region. In this case, however, the next step comprises the oxidation of the gate 14, together with Argon (Ar) and Nitrogen (N₂) implantation to create an oxide layer 17 around the outer walls of the gate 14, as illustrated in Figure 3b of the drawings. Said Ar and N₂ implantation favours oxidation of the sidewalls of the gate. Said oxidation step is thus adapted to oxidise in a single step a first layer, preferably of substantially uniform thickness, from the upper surface and sidewalls of the gate structure 14. This oxide layer acts as a good barrier material for the subsequent LDD implantation step (as before) which completes the source/drain region of the device, and the resultant structure is illustrated in Figure 3c of the drawings. Said oxide layer is then removed thanks to a hydrofluoric acid HF cleaning. In a next step, as illustrated in Figure 3d of the drawings, the gate 14 is once again oxidised, together with Argon and nitrogen implantation to form another oxide layer 19 around the outer walls of the gate structure 14, preferably of substantially uniform thickness. The oxide layer acts as a good insulator during the subsequent annealing step, as illustrated in Figure 3e. Said oxide layer is then removed thanks to a HF cleaning together with the dielectric layer 12, except for the portion thereof covered by the gate structure 14. Finally, a spacer 125 is formed on the sidewalls of the polysilicon gate 14, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14, as illustrated in Figure 3f. Self-aligned suicide contacts 28 are then formed for the drain, source and gate of the device, as shown in Figure 3g, as before. The use of oxidation in the second exemplary embodiment of the present invention instead of the etching steps used in the first exemplary embodiment of the present invention, permits the use of the above-described method in integration processes without the need for high dielectric permittivity or metal gates, such that this process can be used within current technologies.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of forming a semiconductor device, the method comprising the steps of: forming a gate structure (14) on a semiconductor substrate (10), - performing heavy impurity doping in portions (126) of said semiconductor substrate (10) not covered by said gate structure (14) to partially form source and drain regions of said semiconductor device, removing a first layer from an upper surface and sidewalls of said gate structure (14), performing light impurity doping in portions (124) of said semiconductor substrate (10) not covered by said gate structure (14) to complete said source and drain regions of said semiconductor device, removing a second layer from the upper surface and sidewalls of said gate structure (14), forming a spacer layer (125) on the sidewalls of said gate structure (14), and - forming a suicide contact (28) on the upper surface of said gate structure (14).

2. A method according to claim 1, wherein the step or steps of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure (14) comprises an etching process.

3. A method according to claim 2, wherein said etching process comprises an anisotropic reactive-ion-etching process.

4. A method according to claim 1, wherein the step of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure (14) comprises an oxidation process.

5. A method according to claim 4, wherein said oxidation process is coupled with gas implantation.

6. A method according to claim 5, wherein said oxidation process is coupled with Argon and/or Nitrogen implantation.

7. A method according to any one of the preceding claims, wherein the step of removing a second layer from the upper surface and the sidewalls of the gate structure (14) is followed by an annealing process.

8. Apparatus for forming a semiconductor device by the method of any one of claims 1 to 7, the apparatus comprising: means for forming a gate structure (14) on a semiconductor substrate (10), means for performing heavy impurity doping in portions (126) of said semiconductor substrate (10) not covered by said gate structure (14) so as to partially form source and drain regions of said semiconductor device, means for removing a first layer from an upper surface and sidewalls of said gate structure (14), means for performing light impurity doping in portions (124) of said semiconductor substrate not covered by said gate structure (14) to complete said source and drain regions of said semiconductor device, means for removing a second layer from the upper surface and sidewalls of said gate structure (14), means for forming a spacer layer (125) on the sidewalls of said gate structure (14), and means for forming a suicide contact (28) on the upper surface of said gate structure (14).

9. A semiconductor device fabricated by the method according to any one of claims 1 to

7.