WO2004055985A1

WO2004055985A1 - Method and device for charge recovery in an integrated circuit

Info

Publication number: WO2004055985A1
Application number: PCT/CH2003/000827
Authority: WO
Inventors: François SALCHLI; Pierre-Alain Conus; Alessandro Rega; Christian Pillonel
Original assignee: Ecole D'ingenieurs Du Canton De Vaud
Priority date: 2002-12-17
Filing date: 2003-12-17
Publication date: 2004-07-01
Also published as: AU2003303000A1

Abstract

The invention concerns a method and a device for charge recovery in an integrated circuit, in particular a digital integrated circuit, said circuit being electrically powered by a power source consisting for example of a battery rechargeable or not and comprising at least one node causing a stray capacitance which is alternately charged and discharged during the operation of the circuit. An inverter (20), equipped with the device, comprises a recovery capacitor (Cre) which is arranged between a node (B) linked to the transistor (T1) and the node (S). The stray capacitance (Cpa) is charged when the output node (A) shifts from the voltage (VSS) to the voltage (VDD). On the other hand, when the output of the inverter (20) shifts from the voltage (VDD) to the voltage (VSS) the charges of the stray capacitance are recovered for the major part by the recovery capacitor (Cre). A fictitious voltage (F_VSS) is then produced for the inverter (20) instead of the voltage (VSS) between the node (B) and the node (S). The logic states are thus contained between (VDD) and (F_VSS).

Description

METHOD AND DEVICE FOR RECOVERING LOADS IN AN INTEGRATED CIRCUIT

Technical area

The present invention relates to a method for recovering charges in an integrated circuit, in particular a digital integrated circuit, this circuit being electrically supplied by an energy source constituted in particular by a rechargeable or non-rechargeable battery and comprising at least one node causing a parasitic capacitance which charges and discharges alternately during the operation of this circuit.

It also relates to a device for recovering charges in an integrated circuit, in particular a digital integrated circuit, this circuit being electrically supplied by an energy source constituted in particular by a rechargeable or non-rechargeable battery and comprising at least one node causing a capacity parasite which loads and discharges alternately at. during the operation of this circuit.

Prior art

The geometries of the integrated circuits become more and more fine and the density of integration more and more important. The consumption requirements of the circuits are increasing and the supply voltages tend to decrease. For 0.18μm technology, for example, the supply voltage is 1.8 volts. A significant part of the consumption in a circuit is

25 caused by the charging and discharging of the stray capacitances of the nodes of the circuit. With the evolution of the circuits, these parasitic capacities increase in number, which increases the consumption of current used to charge and decarge-these parasitic capacities ^ and consequently decreases the life of the batteries or supply batteries of the circuit .

30

The increase in the lifespan of batteries and power supplies for electronic circuits is a major concern of all industries using this type of circuits. This is particularly the case for the watch industry, the computer industry and, more generally, all portable systems, in particular telephones or the like.

Statement of the invention

The object of the present invention is to reduce the drawbacks attributable to the overconsumption of electrical energy of integrated circuits due to the existence of parasitic capacitances, by proposing a method as well as a device making it possible to recover at least partially the energy consumed. .

This object is achieved by the method as defined in the preamble and characterized in that the quantities of charges generated during discharges of said parasitic capacity are recovered and stored for later use.

According to a preferred embodiment, said quantities of charge are recovered by means of at least one recovery capacity and these quantities of charge are transferred into at least one storage capacity when the voltage across said terminals of recovery reaches a predetermined threshold.

According to an advantageous embodiment, the said quantities of charges are transferred from said recovery capacity to said storage capacity by means of a series of switches controlled by a logic circuit.

In a particularly advantageous manner, said quantities of charges are recovered by means of at least two recovery capacities and these quantities of charges are alternately transferred into at least one storage capacity when the voltage across the terminals of the one of said recovery capacities reaches a predetermined threshold. According to a particular embodiment, a part of the circuit or the complete circuit is supplied when the voltage across the storage capacity is sufficient, until the voltage supplied by said storage capacity is equal to the voltage the lowest that still allows the circuit to operate.

This object is also achieved by the device as defined in the preamble and characterized in that it includes means for retrieving and storing, for later use, the quantities of charges generated during discharges of said parasitic capacities.

According to a preferred embodiment, said device comprises at least one recovery capacity for recovering said quantities of charge and at least one storage capacity into which these quantities of charge are transferred when the voltage across said recovery capacity reaches a threshold predetermined.

According to an advantageous embodiment, said device comprises a series of switches controlled by a logic circuit for effecting the transfer of said quantities of charges from said recovery capacity to said storage capacity.

In a particularly advantageous manner, the device comprises at least two recovery capacities for recovering said quantities of charges and means for alternately transferring these quantities of charges into at least one storage capacity when the voltage across one of said capacities recovery reaches a predetermined threshold.

According to a particular embodiment, two switches of the series of switches controlled by the logic circuit are controlled so that, when the voltage across the storage capacity is sufficient to supply part of the circuit, or the complete circuit , one of the switches opens and the other switch closes until the voltage supplied by the storage capacity is equal to the lowest voltage which still allows the circuit to operate.

Brief description of the drawings

The present invention and its advantages will appear better in the description of different embodiments of the invention, described by way of nonlimiting examples and with reference to the appended drawings, in which:

FIG. 1 represents an electronic circuit corresponding to a conventional inverter and illustrating the prior art,

FIG. 2 represents an electronic circuit corresponding to an inverter and illustrating the method according to the invention, and

- Figure 3 shows an embodiment of the device according to the invention.

Best way to realize the invention

The circuit represented by FIG. 1 illustrates a conventional inverter 10 supplied by a battery 11 and comprising two transistors Ti and T _2] an input terminal 12 and an output node A. The battery delivers a voltage VDD to a terminal D of the inverter 10 and a voltage Vss at another node S of this inverter. The input voltage V | _N of the inverter 10 is measured between the input terminal 12 and the node S. The output voltage V ₀ uτ of the inverter 10 is measured between the output node A and the node S. A parasitic capacitance C _pa is inevitably generated at node A by the transistors, the connection lines and the rest of the circuit. At each transition from node A from voltage Vss to voltage VDD the -battery-1-1 must provide a quantity of charges Q equal to: -

Q = Cpa. VDD to charge the stray capacitance C _pa at the voltage V _D D- This quantity of charges is then eliminated in node A when the output of the inverter changes from voltage V _DD to voltage Vss-

FIG. 2 schematically illustrates the method according to the invention which proposes to recover this quantity of charges which is lost in conventional circuits such as that of FIG. 1. The circuit represented by this figure represents an inverter 20 substantially identical to that of Figure 1, but which differs from the latter in that it further comprises a recovery capacity C _re which is arranged between a node B linked to the transistor Ti and the node S.

The parasitic capacitance C _pa is charged as before when the node A passes from the voltage V _S s to the voltage VD On the other hand _, when the output of the inverter 20, namely the node A, passes from the voltage V _DD to the voltage Vss the loads of the parasitic capacity are largely recovered in the recovery capacity C _re (according to the ratio of the two capacities C _pa and C _re ). A fictitious voltage F_V _S s is then created for the inverter 20 in place of the voltage V _S s between node B and node S. The logic states are therefore contained between V _D D and F_V _S s-

Depending on the switching frequency of the inverter, the recovery capacity C _re fills with charges and the voltage across its terminals increases. For the inverter to continue to function correctly, it is necessary that this voltage across the terminals of the recovery capacity does not exceed a certain value in order to respect a robustness to noise and to ensure appropriate protection against the transmission of parasitic states through the inverter. When a predetermined threshold is reached, the

_^ charges stored_by capacity. of "recovery _re " to a storage capacity C _V DD (not shown in this figure - see Figure 3). The switching technique for transferring the recovered charges is advantageously similar to the capacity technique used in the integrated voltage multipliers. FIG. 3 illustrates an embodiment of the device 30 according to the invention, the function of which consists in recovering the charges of the parasitic capacity C _pa by means of at least one recovery capacity C _re and in storing them in a storage capacity CVDD- This device is delimited in the figure by a broken line.

In this embodiment the device which cooperates with a conventional electronic circuit 32 comprises two recovery capacities, respectively C _re ι and C _re2 arranged to recover the charges arriving in the node B. These charges are stored alternately in these two recovery capacities . When the voltage across the recovery capacity C _re ι reaches a predetermined threshold, the charges are directed to the recovery capacity C _re2 - As a result, the system can continue to operate while the recovery capacity C _re ι is emptied into the CVDD storage capacity - After the transmission of the quantities of charges Q contained in the recovery capacity C _re ι to the storage capacity CVD _D , the quantities of charges Q contained in the recovery capacity C _re2 may in turn be transferred to CVDD storage capacity

The switching ensuring the control of these functions is carried out by means of elements in the form of a series of switches Si to Sι ₂ whose functions are defined below.

The switches Si and S ₃ on the one hand and S ₂ and S ₄ on the other hand, have the function of connecting to node B which corresponds to node S in a conventional circuit not comprising the device 30. The switches Si and S ₂ are active for alternation. and the switches S ₃ and S are active for the other half-wave,

The switches S5 and S _{7 as} well as the switches Ss and Sa allow respectively to connect the recovery capacities C _τe2 and C _re ι to the storage capacity CVDD- The switches Sg ensure the direct connection of the circuit 32 to the battery 11 and the switch S ₁₀ provides the connection for recover the charges and deliver a voltage V _D Dca _P a to replace the user electronic circuit 32. The switches Su and S ₂ provide the connection for controlling the voltages across the recovery capacitors C _re ι and C _r e2 by means of a logic circuit 33. This circuit makes it possible to control the opening and closing of the switches so that the device can fulfill its role of recovery of the loads of the stray capacitances and it ensures the control of the values of voltage thresholds.

Finally, when the voltage across the storage capacity CVDD is sufficient to supply either part of the user circuit 32 or the complete circuit, the switch Sg is open and the switch S- is closed until the voltage V _D Dcapa supplied by the CVDD storage capacity is equal to the lowest voltage which still allows the circuit 32 to operate. When this lower value is reached, the supply of the circuit 32 is again switched to the battery 11 by the closing of the switch S ₉ .

The example described above is not limiting and the inverter could be replaced by any digital circuit as well as certain analog circuits.

Claims

1. Method for recovering charges in an integrated circuit, in particular a digital integrated circuit, this circuit being electrically supplied by an energy source constituted in particular by a rechargeable or non-rechargeable battery and comprising at least one node causing parasitic capacitance (C _pa ) which is charged and discharged alternately during the operation of this circuit, characterized in that one recovers and stores, for later use, at least partially the quantities of charges (Q) generated during discharges of said parasitic capacity.

2. Method according to claim 1, characterized in that said quantities of charges are recovered (Q) by means of at least one recovery capacity (C _re ) and in that these quantities of charges are transferred ( Q) in at least one storage capacity (CVDD) when the voltage across said recovery capacity (C _re ) reaches a predetermined threshold.

3. Method according to claim 2, characterized in that one carries out the transfer of said quantities of charges (Q) from said recovery capacity (C _re ) to said storage capacity (CVDD) by means of a series of switches controlled by a logic circuit.

4. Method according to claim 2, characterized in that said quantities of charges are recovered (Q) by means of two recovery capacities (C _re ι, C _re2 ) and in that these quantities are transferred alternately from charges (Q) in at least one storage capacity (CVDD) when the voltage across one of said recovery capacities (C _re ι, C _re2 ) reaches a predetermined threshold. . ._.

5. Method according to claim 4, characterized in that one supplies a part of the circuit or the complete circuit when the voltage across the storage capacity (CVD _D ) is sufficient, until the voltage (V _D Dca _P a) provided by the storage capacity is equal to the lowest voltage which still allows said circuit to operate.

6. Device for recovering charges in an integrated circuit, in particular a digital integrated circuit, this circuit (32) being electrically supplied by an energy source (11) constituted in particular by a rechargeable battery or not and comprising at least one node (B) causing a parasitic capacitance (C _pa ) which is charged and discharged alternately during the operation of this circuit, for the implementation of the method according to claim 1, characterized in that it comprises means for recovering and to store, for later use, the quantities of charges generated during discharges of said parasitic capacity (C _pa ).

7. Device according to claim 6, characterized in that it comprises at least one recovery capacity (C _re ) for recovering said quantities of charges (Q) and at least one storage capacity (CV _D D) into which are transferred these quantities of charges (Q) when the voltage at the nodes (B, S) of said recovery capacity (C _re ) reaches a predetermined threshold.

8. Device according to claim 7, characterized in that it comprises a series of switches (Si to Sι ₂ ) controlled by a logic circuit (33) for effecting the transfer of said quantities of charges (Q) from said recovery capacity (C _re ) to said storage capacity (CV _D D) -

9. Device according to claim 6, characterized in that it comprises two recovery capacities (C _re ι, C _re 2) for recovering said quantities of charges and means for alternately transferring these quantities of charges into at least one capacity of storage (CVDD) when the voltage across one of said recovery capacities (C _re ι, C _re2 ) reaches a predetermined threshold.

10. Device according to claim 8, characterized in that two switches (S _g , S- | ₀ ) of the series of switches controlled by the logic circuit (33) are controlled in such a way that, when the voltage at the terminals of storage (CVDD) is sufficient to power a ^'part of the circuit or the entire circuit (32), one of the switches (S) g is opened and the other switch (S-io) closes up that the voltage (V _DD ca _P a) supplied by the storage capacity is equal to the lowest voltage which still allows said circuit (32) to operate.