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WO2004008509A1 - Reduction des defauts dans des materiaux semi-conducteurs - Google Patents

Reduction des defauts dans des materiaux semi-conducteurs Download PDF

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Publication number
WO2004008509A1
WO2004008509A1 PCT/EP2003/007604 EP0307604W WO2004008509A1 WO 2004008509 A1 WO2004008509 A1 WO 2004008509A1 EP 0307604 W EP0307604 W EP 0307604W WO 2004008509 A1 WO2004008509 A1 WO 2004008509A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching
epitaxial
substrate
growth
layer
Prior art date
Application number
PCT/EP2003/007604
Other languages
English (en)
Inventor
Brendan John Roycroft
Pleun Pieter Maaskant
Original Assignee
University College Cork - National University Of Ireland, Cork
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University College Cork - National University Of Ireland, Cork filed Critical University College Cork - National University Of Ireland, Cork
Priority to AU2003254349A priority Critical patent/AU2003254349A1/en
Priority to EP03763842A priority patent/EP1540713A1/fr
Priority to JP2004520620A priority patent/JP2005532692A/ja
Publication of WO2004008509A1 publication Critical patent/WO2004008509A1/fr
Priority to US11/030,986 priority patent/US7399684B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching

Definitions

  • the invention relates to the production of epitaxial materials with a reduced defect density.
  • Epitaxial wafer materials are widely used as starting materials in semiconductor device fabrication.
  • the presence of defects in such wafer materials can seriously affect the subsequent device performance.
  • GaN and its related compounds InGaN and AlGaN are widely used in the fabrication of short- wavelength semiconductor laser diodes.
  • the performance of such laser diodes is seriously degraded by the presence of threading dislocations, which thread vertically through the epitaxial layers. Similar defects are found in other material systems, for example, when GaAs is grown on SiGe/Si. A reduced dislocation density on the epitaxial wafer materials is therefore desired.
  • GaN shall also refer to its compounds (In)(Al)(Ga)N, and may be p-type, n-type or undoped.
  • ELOG Epitaxial Layer Over-Growth
  • Defect density in good ELOG growth is reduced from 10 l ⁇ cm “2 in standard GaN/Sapphire growth, to 10 8 cm “2 in 1 step ELOG, or to 5.10 5 cm “2 after multiple steps of ELOG.
  • a defect density of 5.10 5 cm “2 corresponds to 1 defect per 14 ⁇ mxl4 ⁇ m square area. Therefore, the size of a defect-free area is still small in comparison to the 50mm diameter wafer area available for device fabrication.
  • a second approach, described in US patent application US2002/0005593 is to grow standard GaN epitaxial layers at high temperature (1000 °C), then deposit a thin layer of GaN at a lower temperature (700 - 900 °C), then resume growth at the high temperature (1000 °C). It is claimed that this prevents defects from propagating vertically, and reduces the defect density from >10 10 cm 2 to 4.10 7 cm 2 . This approach suffers from insufficient removal of defects.
  • a third approach is the direct production of GaN substrates from liquid gallium, and nitrogen at very high pressure (45,000 bar) (by Unipress in Poland). This approach suffers from the use of very highly specialised and expensive equipment, and the production of rather small ( ⁇ 1 cm 2 ) GaN crystals.
  • the invention is therefore directed towards providing a method and system to produce large areas of epitaxial material with low defect density in a simple and effective manner, using relatively common and inexpensive equipment and materials.
  • a method of producing a low-defect semiconductor wafer in which an epitaxial layer is grown on a substrate comprising the steps of:- (a) growing a layer of epitaxial material on the substrate,
  • the step (b) is performed by exposing the surface to dry etching by RIE, or ICP (Inductively Coupled Plasma etching), or chemically assisted ion beam etching, or other suitable dry etching process.
  • RIE reactive ion etching
  • ICP Inductively Coupled Plasma etching
  • chemically assisted ion beam etching or other suitable dry etching process.
  • the step (b) is performed by immersion in aqua regia, or a mixture of KOH/NaOH, or other suitable wet etching solution.
  • an additional compound is added for the growth step (c) to improve surface smoothness.
  • the additional compound is In(Ga)N, or Al(Ga)N, or magnesium doped (Al)(In)(Ga)N.
  • the epitaxial material is GaN.
  • the substrate is of sapphire material.
  • the substrate is of Si, SiC, or diamond material.
  • the epitaxial material is InP.
  • the epitaxial material is GaAs.
  • the method comprises the further steps of repeating steps (b) and (c) one or more additional times until a target defect density is achieved.
  • the etching is performed in-situ within a growth chamber.
  • the etching is performed under vacuum.
  • the invention provides a semiconductor wafer whenever produced by a method as defined above.
  • Figs. 1(a) to 1(d) are a series of diagrams showing a semiconductor growth method of the invention.
  • Fig. 2 is a photograph illustrating the surface of etched GaN after RIE.
  • a sapphire substrate 1 acts as the substrate for the epitaxial growth of device quality wafer material.
  • an initial epitaxial layer 2 of GaN is grown on the substrate 1 in a conventional manner. However, there are many defects 3 which thread through the epitaxial layer 2.
  • the epitaxial layer 2 is etched by wet or dry etching within the growth chamber.
  • the etching acts preferentially on the epitaxial layer 2 at the defects 3, causing them to become enlarged cavities 5, which may or may not extend down to the substrate 1.
  • These cavities 5 appear as black dots in the photograph of an etched surface shown in Fig. 2.
  • the cavities 5 are too large in proportion to the crystal lattice to act as defects in the usual sense.
  • Indium or magnesium may be added to the GaN to aid planarisation. Steps (c) and (d) may be repeated if removal of defects was not sufficient in step (c).
  • Further epitaxial growth allows wafer materials for devices such as high power transistors, light emitting diodes, and laser diodes to be produced.
  • GaN growth is initiated in the standard way by MOVPE or MBE. It has been found by other groups that after an initial three dimensional growth, a two dimensional growth mode takes over. Incorporated unintentionally in this two dimensional growth are many threading dislocations which propagate upwards through any subsequent growth.
  • the wafer is removed from the growth chamber and placed in a reactive ion etch (RIE) chamber. Etching proceeds with a mixture of SiCl 4 /H 2 as the etchant. This has been found to preferentially etch macroscopic defects and threading dislocations.
  • RIE reactive ion etch
  • etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate.
  • the surface is heat treated at 300-1000°C in a N 2 or NH 3 ambient. GaN growth is then resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for the subsequent growth of device epitaxial layers, as required.
  • Example 2
  • GaN growth is initiated in the standard way by MOVPE or MBE.
  • MOVPE commonly sapphire, but may be SiC or other
  • GaN growth is initiated in the standard way by MOVPE or MBE.
  • MOVPE commonly sapphire, but may be SiC or other
  • the wafer is removed from the growth chamber and placed in a beaker of boiling aqua regia solution (HC1:HN0 3 at 3:1).
  • Etching has been found to leave the good quality GaN areas almost unaffected, but macroscopic defects and threading dislocations are substantially etched.
  • the time of etching is left to the discretion of the operator, but should be long enough to cause substantial etching of the defects, which may or may not be etched all the way back to the substrate.
  • the wafer is then removed from the solution, placed in boiling ammonia polysulfide solution for ten minutes, removed, rinsed in de-ionised water, then dried. Finally, GaN growth is resumed in the growth reactor until a planar surface is achieved. The wafer is now ready for subsequent device epitaxial layers, as required.
  • the invention achieves a more effective reduction of defects with simpler processing than the prior art.
  • the etching step is applied to the whole wafer surface there is no need for definition/ masking of surface areas as in the ELOG approach.
  • the invention does not require the incorporation of a foreign material (such as Si0 2 or Si x N y in ELOG) as it effectively provides an homogenous GaN epitaxy over the substrate.
  • defects are removed over the whole surface, rather than in strips as in ELOG.
  • there is little material wastage as only about 1 micron is lost due to the dry etching, and almost no material is lost due to the wet etching. Regrowth may achieve planarisation in less than 1 micron of growth, due to the small size of the defects.
  • at least 2 micron growth is required to cover the Si0 2 strips and to achieve a planarised surface, often over 100 micron growth is used.
  • the invention can be applied to the growth of other epitaxial layers for a wide variety of semiconductor devices, such as InP, GaAs, and Si. Further any other suitable substrate may be used such as Si, SiC, or diamond. Also, any suitable wet or dry etching method which preferentially etches the defects may be used.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne une couche initiale épitaxiale (2) de GaN que l'on forme sur un substrat (2) en saphir. La couche épitaxiale (2) est ensuite attaquée dans une chambre de gravure ionique réactive (RIE). Cette gravure agit de préférence sur les défauts (3) qui deviennent alors des cavités (5) agrandies. Ces cavités (5) sont trop grandes par rapport au réseau cristallin pour normalement être considérées comme des défauts. On remplit alors les cavités d'une nouvelle couche épitaxiale GaN. On évite ainsi une propagation des défauts.
PCT/EP2003/007604 2002-07-11 2003-07-11 Reduction des defauts dans des materiaux semi-conducteurs WO2004008509A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2003254349A AU2003254349A1 (en) 2002-07-11 2003-07-11 Defect reduction in semiconductor materials
EP03763842A EP1540713A1 (fr) 2002-07-11 2003-07-11 Reduction des defauts dans des materiaux semi-conducteurs
JP2004520620A JP2005532692A (ja) 2002-07-11 2003-07-11 半導体材料における欠陥の減少
US11/030,986 US7399684B2 (en) 2002-07-11 2005-01-10 Defect reduction in semiconductor materials

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IE2002/0574 2002-07-11
IE20020574 2002-07-11

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/030,986 Continuation US7399684B2 (en) 2002-07-11 2005-01-10 Defect reduction in semiconductor materials

Publications (1)

Publication Number Publication Date
WO2004008509A1 true WO2004008509A1 (fr) 2004-01-22

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PCT/EP2003/007604 WO2004008509A1 (fr) 2002-07-11 2003-07-11 Reduction des defauts dans des materiaux semi-conducteurs

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EP (1) EP1540713A1 (fr)
JP (1) JP2005532692A (fr)
CN (1) CN100454486C (fr)
AU (1) AU2003254349A1 (fr)
WO (1) WO2004008509A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006064081A1 (fr) 2004-12-14 2006-06-22 Optogan Oy Substrat semi-conducteur, composant a semi-conducteur et procede de fabrication d'un substrat semi-conducteur

Families Citing this family (6)

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Publication number Priority date Publication date Assignee Title
CN101587831B (zh) * 2008-05-19 2013-01-16 展晶科技(深圳)有限公司 半导体元件结构及半导体元件的制造方法
CN102005370B (zh) * 2010-10-12 2013-09-18 北京大学 一种制备同质外延衬底的方法
EP2783390A4 (fr) * 2011-11-21 2015-12-23 Saint Gobain Cristaux Et Detecteurs Substrat semi-conducteur et procédé de formation
CN102779787A (zh) * 2012-07-20 2012-11-14 江苏能华微电子科技发展有限公司 一种ⅲ族氮化物半导体器件的制备方法
CN103871849A (zh) * 2012-12-18 2014-06-18 上海华虹宏力半导体制造有限公司 外延层的形成方法
CN106486339B (zh) * 2015-08-26 2020-03-13 中芯国际集成电路制造(上海)有限公司 GaN薄膜的制备方法

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Publication number Priority date Publication date Assignee Title
US4404265A (en) * 1969-10-01 1983-09-13 Rockwell International Corporation Epitaxial composite and method of making
US6121121A (en) * 1997-11-07 2000-09-19 Toyoda Gosei Co., Ltd Method for manufacturing gallium nitride compound semiconductor
EP1111663A2 (fr) * 1999-12-20 2001-06-27 Nitride Semiconductors Co., Ltd. Dispositif semiconducteur composé à base de GaN et procédé de fabrication
US20010008299A1 (en) * 1998-11-24 2001-07-19 Linthicum Kevin J. Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on silicon carbide substrates by lateral growth from sidewalls of masked posts

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JP3958818B2 (ja) * 1997-01-08 2007-08-15 三菱電線工業株式会社 半導体発光素子及びその製造方法
JP3786544B2 (ja) * 1999-06-10 2006-06-14 パイオニア株式会社 窒化物半導体素子の製造方法及びかかる方法により製造された素子
JP2001122693A (ja) * 1999-10-22 2001-05-08 Nec Corp 結晶成長用下地基板およびこれを用いた基板の製造方法
JP4556300B2 (ja) * 2000-07-18 2010-10-06 ソニー株式会社 結晶成長方法
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US4404265A (en) * 1969-10-01 1983-09-13 Rockwell International Corporation Epitaxial composite and method of making
US6121121A (en) * 1997-11-07 2000-09-19 Toyoda Gosei Co., Ltd Method for manufacturing gallium nitride compound semiconductor
US20010008299A1 (en) * 1998-11-24 2001-07-19 Linthicum Kevin J. Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on silicon carbide substrates by lateral growth from sidewalls of masked posts
EP1111663A2 (fr) * 1999-12-20 2001-06-27 Nitride Semiconductors Co., Ltd. Dispositif semiconducteur composé à base de GaN et procédé de fabrication

Non-Patent Citations (1)

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Title
WEYHER J L ET AL: "Study of individual grown-in and indentation-induced dislocations in GaN by defect-selective etching and transmission electron microscopy", MATERIALS SCIENCE AND ENGINEERING B, ELSEVIER SEQUOIA, LAUSANNE, CH, vol. 80, no. 1-3, 22 March 2001 (2001-03-22), pages 318 - 321, XP004234721, ISSN: 0921-5107 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006064081A1 (fr) 2004-12-14 2006-06-22 Optogan Oy Substrat semi-conducteur, composant a semi-conducteur et procede de fabrication d'un substrat semi-conducteur

Also Published As

Publication number Publication date
CN100454486C (zh) 2009-01-21
EP1540713A1 (fr) 2005-06-15
JP2005532692A (ja) 2005-10-27
CN1675746A (zh) 2005-09-28
AU2003254349A1 (en) 2004-02-02

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