WO2004006329A1

WO2004006329A1 - Thin-film substrate having post via

Info

Publication number: WO2004006329A1
Application number: PCT/JP2002/006847
Authority: WO
Inventors: Masateru Koide; Naomi Fukunaga; Misao Umematsu; Satoshi Ohsawa; Tomohisa Yamamoto
Original assignee: Fujitsu Limited
Priority date: 2002-07-05
Filing date: 2002-07-05
Publication date: 2004-01-15
Also published as: JPWO2004006329A1; JP4478567B2

Abstract

An insulating layer (14) is formed between two wiring layers forming pattern wiring. A post via (15) for signal transmission electrically interconnects the wiring layers. A dummy post via (17) is disposed in a portion where the density of the post vias (15) is lower than that of the other portions in the insulating layer (14). The dummy post via (17) is an isolated post via not connected to a signal transmission circuit. As a result, the distribution density of the post vias in the insulating layer (14) is uniformed to some extent, and the whole insulating layer (14) is polished to a uniform thickness.

Description

Technical field of thin film substrate with bost via

The present invention relates to a thin film substrate, and more particularly to a thin film substrate having a post via extending into an insulating layer between wiring layers. Background art

A thin film substrate is used as a package substrate of a semiconductor device. Wiring layers are formed on the upper and lower surfaces of the thin film substrate, and the upper and lower wiring layers are electrically connected by relatively long pillar-shaped vias called post vias. Post vias are typically formed by filling elongated holes formed in resist with a conductive material such as metal. The thin film substrate is formed by embedding the thus formed post via in an insulating “green” resin layer.

For example, a copper post is formed by filling an elongated hole formed in the resist layer with copper by copper plating or the like. Then, the resist layer is removed and copper posts are embedded in the insulating layer. The insulating layer with the embedded copper posts is polished by mechanical buffing (mechanical polishing). Thereby, the thickness of the thin film substrate is reduced, and the surface of the substrate is made flat.

Here, problems in performing the above-described mechanical buffering will be described. The electrode pads formed on the surface of the package substrate are arranged based on the electrode arrangement of the semiconductor chip to be packaged. For example, in a package substrate used for a semiconductor chip having a peripheral array electrode structure, many electrode pads are formed in a peripheral portion of the substrate. Therefore, the number of post vias connecting the electrode pad and the wiring (electrode pad) formed on the opposite side of the substrate is also large in the peripheral portion of the substrate and small in the central portion. That is, the distribution density of the post vias is large in the peripheral portion of the substrate, and small in the central portion.

Figure 1 shows a package base with a portion where the distribution density of bostvia differs as described above. FIG. 4 is a cross-sectional view of an insulating layer in a state before performing mechanical buffering in a step of forming a plate. FIG. 2 is a cross-sectional view showing a state after the insulating layer shown in FIG. 1 has been subjected to mechanical buffering.

In FIG. 1, a plurality of Bostvias 2 formed by copper plating or the like are embedded in an insulating layer 4 for forming the Bostvias 2. The tip of each bost via 2 protrudes from the surface 4 a of the insulating layer 4. This is to sufficiently fill the copper holes in the holes for the post vias formed in the insulating layer 4. After the post vias 2 are formed in the insulating layer 4 as shown in FIG. 1, the surface 4a of the insulating layer 4 is polished to a predetermined thickness, and the surface 4a of the insulating layer 4 is flattened. Dagger. This polishing is performed by the mechanical backing described above.

Here, when polishing the surface 4a of the insulating layer 4, the bost via 2 is also polished. Since the insulating layer 4 is formed of an insulating resin or the like, the hardness of the insulating layer 4 is much lower than the hardness of the post via 2 formed by copper plating. Therefore, the polishing rate of the insulating layer 4 is higher than the polishing rate of the boast via 2 during mechanical buffing.

If the distribution density of the boss vias 2 in the insulating layer 4 is uniform throughout the insulating layer 4, the insulating layer 4 is polished almost uniformly to have a uniform thickness, and the polished surface 4a of the insulating layer 4 is flat. Be tan. When the distribution density of the post vias 2 in the insulating layer 4 is partially different as shown in FIG. 1, the surface 4a of the insulating layer 4 after mechanical puffing becomes as shown in FIG. It is not flat.

That is, as shown in FIG. 1, if there is a portion where the distribution density of the post via 2 is small, only that portion is polished, and the post via 2 becomes lower than other portions. For example, in the case of a thin film substrate for a semiconductor chip having a peripheral arrangement electrode structure as described above, the central portion of the insulating layer is lower than the peripheral portion, and a depression is formed. As described above, if the thickness of the insulating layer is not uniform, signal transmission characteristics may vary, and interlayer short-circuit may occur during long-term use. Disclosure of the invention

A general object of the present invention is to provide an improved and useful thin film substrate which solves the above-mentioned problems. Is to provide a structure.

A more specific object of the present invention is to uniformly polish the entire polished surface when the insulating layer in which the bostvia is embedded is subjected to mechanical buffering in the manufacturing process of the thin film substrate having the bostvia. It is to provide a structure of a thin film substrate. In order to achieve the above object, according to the present invention, there is provided a thin film substrate for a semiconductor device, comprising: at least two wiring layers for forming pattern wiring; an insulating layer located between the wiring layers; A post via extending inside and electrically connecting the wiring layer; and at least one dummy post via arranged in a portion of the insulating layer where the density of the boast via is smaller than other portions and not connected to the signal transmission circuit. A thin film substrate for a semiconductor device is provided.

In the above-described thin film substrate for a semiconductor device according to the present invention, the dummy post via is preferably formed of the same material as the post via. Also, the dummy post via is preferably an electrically isolated post via that is not connected to an external circuit. Alternatively, the dummy post via may be a part of the power supply wiring or the ground wiring. Further, the insulating layer may be exposed around a portion of the wiring layer to which the dummy post via is connected, and the exposed insulating layer may form a gas vent hole.

According to the invention described above, since the dummy post vias are present, the density distribution of the vias is substantially constant over the entire surface of the insulating layer, and the insulating layer is polished to a flat state even when mechanical puffing is performed. be able to. Therefore, the thickness of the insulating layer can be made uniform, and the long-term reliability of the semiconductor device formed using the thin film substrate according to the present invention can be improved.

Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view of a resin layer in which post vias are embedded, before performing mechanical buffering.

FIG. 2 is a cross-sectional view showing a state after the resin layer shown in FIG. FIG. 3 is a sectional view of a part of a thin film substrate according to one embodiment of the present invention.

FIG. 4 is a view for explaining a part of the process of forming a boss via.

FIG. 5 is a view for explaining a part of the step of forming the bost via. (B) FIG. 6 is a cross-sectional view of the insulating layer in which dummy bost vias are formed.

FIG. 7 is a cross-sectional view showing a state after the insulating layer shown in FIG. 6 has been mechanically buffered.

FIG. 8 is a cross-sectional view showing an example in which a gas vent hole is provided in a solid pattern wiring connected to a dummy post via.

FIG. 9 is a plan view of the solid pattern wiring shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are given to the same components.

FIG. 3 is a sectional view showing a part of a thin film substrate according to one embodiment of the present invention. The thin film substrate 10 shown in FIG. 3 includes a core layer 11 and thin film layers 12 formed on both sides thereof. The thin film layer 12 has a multilayer structure, and a plurality of pattern wirings 13 are stacked via an insulating layer 14.

In the present embodiment, the pattern wirings 13 are electrically connected to each other by the post vias 15. For example, the electrodes 15 formed on the front surface and the rear surface of the thin film substrate 10 are electrically connected. The arrangement of the boss vias 15 depends on the electrode arrangement of the semiconductor chip mounted on the thin film substrate 10, and the density of the horizontal boss vias 14 in the thin film layer 12 is not uniform.

Therefore, in the present embodiment, besides the bost via 15 necessary for the wiring in the thin film substrate 10, a dummy post via 17 which does not function as a wiring is provided. As a result, the density of the post vias in the thin film layer 12 is made uniform to some extent, thereby solving the problem of mechanical backing as described later.

Here, a manufacturing process of a portion where the post via of the thin film substrate 10 is arranged will be described with reference to FIG. 4 and FIG. 4 and 5 are views each showing a part of a manufacturing process of a thin film substrate having a post via. Bost vias 15 and dummy post vias 17 in FIG. 3 are formed.

First, a seed layer 18 is formed on the insulating layer 14 (FIG. 4 (a)) by electroless plating or the like (FIG. 4 (b)). Next, a dry film resist (DFR) 19 is pasted on the seed layer 18 (FIG. 4 (c)), and exposed and developed to remove the resist 19 while leaving a predetermined pattern (FIG. 4 (C)). d)). The seed layer 18 is exposed at the portion where the resist 19 is removed. This portion becomes the pattern wiring 13 of the thin film substrate 10.

Thereafter, a metal layer (copper layer) 20 is formed on the seed layer 18 by electrolytic plating (43 (e)), and the resist 19 is removed (FIG. 4 (f)). Then, a dry film resist 21 is attached on the metal layer 20 (FIG. 4 (g)), and the resist 21 is exposed to light and developed to remove a portion where a post via is to be formed, thereby forming an elongated hole 21a ( Figure 4 (h)). The part where the post via is formed is a predetermined position on the pattern wiring formed by the metal layer 20.

Next, the hole 21a is filled with metal (copper) by, for example, plating to form a bost via 15 (FIG. 4 (i)). At this time, plating is performed until the metal protrudes from the hole 21a so that the metal is sufficiently filled in the hole 21a.

Then, the surface 21 of the resist 21 and the tip of the post via 15 are polished by mechanical mechanical buffering until the post via reaches a predetermined height (FIG. 4 (j)).

Next, the resist 21 is removed (FIG. 4 (k)), and the exposed seed layer 18 is removed by etching (FIG. 4 (1)). When the seed layer 18 is removed, a metal layer 20 (pattern wiring 13) is formed on the insulating layer 14 and a post via 15 is formed thereon.

Here, an insulating resin sheet is pasted on the metal layer 20 and hardened to form an insulating layer 22 (FIG. 4 (m)). At this time, the post via 15 formed on the metal layer 20 is embedded in the insulating layer 22.

Next, the surface of the insulating layer 22 is polished by mechanical buffing to expose the tip 15a of the post via 15 to the surface of the insulating layer 22 (FIG. 5 (a)). Then, the insulating layer 22 is subjected to a surface treatment by etching or the like to be cleaned (FIG. 5B). Thus, the formation of the bost via 15 is completed.

When the formation of the bost via 15 is completed, a seed layer 23 is formed on the surface of the insulating layer 22 and the end surface 15a of the post via 15 (FIG. 5 (c)), and a driver is formed on the seed layer 23. Paste the resist film 24 (Fig. 5 (d)). Then, the resist 24 is removed in the shape of the wiring pattern (FIG. 5 (e)), and a metal layer (copper) 25 is formed on the seed layer 23 by electrolytic plating (FIG. 5 (f)). This metal layer 25 becomes the pattern wiring 13. Therefore, a structure in which the metal layer 25 (pattern wiring) and the metal layer 20 (pattern wiring) are electrically connected by the post via 15 is formed. Thereafter, the resist 24 is removed (FIG. 5 (g)), and the exposed seed layer 23 is removed by etching (FIG. 5 (h)). Finally, an insulating layer 26 is formed on the metal layer 25.

The above is the step of forming a part of the thin film layer 12 of the thin film substrate 10. To make the thin film substrate a multilayer package substrate, the above steps are repeated to make the thin film layer 12 multilayer. At that time, formation of post vias and mechanical buffing are also repeated.

Next, the dummy post via 17 in the above embodiment will be described in detail. If the distribution density of the post vias 15 is not uniform, as described above, in the mechanical force / rebuffing process shown in FIG. (Equivalent to the insulating layer 22 in FIG. 5 (a).) As a result, the long-term reliability of the semiconductor device using the thin film substrate is impaired.

Therefore, in this embodiment, as shown in FIG. 6, the distribution density of the post vias is kept within a certain range by arranging the dummy post vias 17 in portions (regions) where the distribution density of the bost vias 15 is low. The dummy post via 17 is an isolated via that is not connected to an external circuit, and is provided only for mechanical cavitation, not for a via required for an electric circuit of a thin film substrate.

Due to the presence of the dummy bost vias 17, the via density distribution is almost constant over the entire surface of the insulating layer 14, and the insulating layer 14 is in a flat state as shown in Fig. 7 even when the two-way buffering is performed. Can be polished. Therefore, the thickness of the insulating layer 14 In this case, the semiconductor device formed using the thin film substrate 10 according to the present embodiment can have improved long-term reliability.

Dummy Bost Via 17 can be formed simultaneously with Bost Via 15 in the process of forming normal Bost Via 15. It is not necessary to provide. Therefore, the dummy via 17 can be formed without increasing the manufacturing cost of the thin film substrate.

In many cases, a plurality of dummy boost vias 17 are provided in an area where the density of the signal vias 15 is low, but in such a case, a plurality of dummy boost vias 17 are placed on the solid pattern wiring. Can be formed. That is, a plurality of dummy vias 17 can be formed on one electrically isolated pattern wiring. This is because even if the dummy post vias 17 are electrically connected to each other, the dummy post vias 17 need only be separated from the signal pattern wiring as a whole.

However, when the solid pattern wiring on which the dummy post via 17 is provided is large, it is necessary to provide an opening in the solid pattern wiring as a gas vent hole. The gas vent hole is an opening for releasing moisture existing inside the thin film substrate to the outside, and is not a cavity but a part of the resin layer exposed from the solid pattern wiring.

FIG. 8 is a cross-sectional view of an insulating layer 14 having a solid pattern wiring provided with dummy boost vias, and FIG. 9 is a plan view of the solid pattern wiring 26 shown in FIG. Dummy bost via 17 is located at a position avoiding signal pattern wiring.So, the periphery of dummy post via 17 of solid pattern rota-line 26 Hole 27.

In the above embodiment, the dummy bost via is an electrically isolated via. However, a dummy bost via can be formed as a part of a power wiring or a ground wiring other than the signal wiring, for example. By forming the dummy bus via as a part of the power supply wiring or the ground wiring and surrounding the signal wiring with the pattern wiring to which the dummy boost via is connected, the effect of shielding the signal wiring can be obtained.

The present invention is not limited to the specifically disclosed embodiments, and various modifications and improvements may be made within the scope of the present invention.

Claims

The scope of the claims

1. A thin film substrate for a semiconductor device,

At least two wiring layers forming pattern wiring;

An insulating layer located between the wiring layers;

A post via extending into the insulating layer and electrically connecting the wiring layer; and a post via having a density smaller than that of the other portion in the insulating layer and not connected to a signal transmission circuit. With one dummy Bostvia

A thin film substrate for a semiconductor device, comprising:

2. The thin film substrate for a semiconductor device according to claim 1, wherein

The dummy bost via is a semiconductor formed of the same material as the bost via

3. The thin film substrate for a semiconductor device according to claim 1, wherein

The thin film substrate for a semiconductor device, wherein the dummy boss via is an electrically isolated boss via which is not connected to an external circuit.

4. The thin film substrate for a semiconductor device according to claim 1, wherein

The dummy boss via is a thin film for a semiconductor device which is a part of a power supply wiring or a ground wiring.

5. The thin film substrate for a semiconductor device according to claim 1, wherein

A thin film substrate for a semiconductor device, wherein the insulating layer is exposed around a portion of the wiring layer to which the dummy bost via is connected, and the exposed insulating layer forms a gas vent hole.