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WO2003021656A2 - Improved material for use with ferroelectrics - Google Patents

Improved material for use with ferroelectrics Download PDF

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Publication number
WO2003021656A2
WO2003021656A2 PCT/EP2002/009259 EP0209259W WO03021656A2 WO 2003021656 A2 WO2003021656 A2 WO 2003021656A2 EP 0209259 W EP0209259 W EP 0209259W WO 03021656 A2 WO03021656 A2 WO 03021656A2
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WO
WIPO (PCT)
Prior art keywords
layer
ferroelectric
sro
liner
enriched
Prior art date
Application number
PCT/EP2002/009259
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French (fr)
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WO2003021656A3 (en
Inventor
Rainer Bruchhaus
Original Assignee
Infineon Technologies Ag
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Publication date
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Publication of WO2003021656A2 publication Critical patent/WO2003021656A2/en
Publication of WO2003021656A3 publication Critical patent/WO2003021656A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer

Definitions

  • the present invention relates to ferroelectric integrated circuits and, more particularly, to materials that reduces fatigue in the ferroelectric material .
  • a memory cell of the ferroelectric memory device includes a capacitor which serves as the storage element.
  • Fig. 1 shows a conventional ferroelectric capacitor 101.
  • the capacitor comprises a ferroelectric metal oxide ceramic layer 150 sandwiched between first and second electrodes 110 and 120.
  • the electrodes typically are formed from a noble metal such as platinum.
  • the ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor.
  • a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes.
  • the polarization of the capacitor depends on the polarity of the voltage applied.
  • An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
  • fatigue in the ferroelectric material occurs after a certain number of switching cycles.
  • strontium- ruthenium-oxide (SrRu0 3 or SRO) as a liner material directly attached between the ferroelectric film and the electrode has been proposed.
  • SRO is typically formed by sputtering.
  • SRO as a liner material due to the instability of its forming compounds Ru0 and SrO.
  • Ru0 2 is a volatile oxide and SrO easily forms SrC0 3 if it is exposed to the atmosphere .
  • Some Ru0 2 evaporates during the crystallization anneal of the amorphous film formed during sputtering, resulting in excess SrO in the SRO layer. This is undesirable because excess SrO produces flowerlike features on the surface of the SRO layer.
  • SrO itself is an isolating material leading to a performance degradation of the ferroelectric capacitor.
  • an SRO target with excess Ru0 2 is used.
  • the excess Ru0 2 diffuses and reacts with the ferroelectric layer during high temperature crystallization of the ferroelectric material which degrades its ferroelectric properties.
  • the material comprises SRO which is enriched with Ti0 2 .
  • the SRO comprises about 1-10 atomic weight percent (unless otherwise specified, all percentages are in atomic weight percent) of Ti0 2 .
  • the Ti0 2 enriched SRO is formed on a substrate which is processed to include a first or bottom capacitor electrode.
  • a ferroelectric material such as PZT is formed on the Ti0 2 enriched SRO.
  • a second Ti0 2 enriched SRO layer is formed on the ferroelectric layer followed by formation of the upper electrode.
  • the SRO enriched layer is formed by sputtering using an SRO target doped with 1-10 percent % Ti0 2 .
  • Fig. 1 shows a conventional ferroelectric capacitor
  • Fig. 2 shows a ferroelectric capacitor in accordance with one embodiment of the invention
  • Fig. 3 shows an illustrative system for depositing the Ti0 2 enriched SRO layer in accordance with one embodiment of the invention.
  • Fig. 4 shows an SRTO layer after a crystallization anneal .
  • Fig. 2 shows a ferroelectric capacitor 201 in accordance with one embodiment of the invention.
  • a capacitor for example, is used to form a ferroelectric memory cell of a ferroelectric memory IC.
  • the capacitor comprises first and second electrodes 210 and 220.
  • the electrodes are formed from, for example, platinum or a noble metal such as Ir, Pd, Ir0 2 or other conducting oxides.
  • a ferroelectric layer 150 is located between the electrodes.
  • the ferroelectric material comprises PZT or lead-1anthanum- zirconium-titanate (PLZT) .
  • PZT lead-1anthanum- zirconium-titanate
  • Other types of ferroelectric material such as Strontium-bismuth-tantalate (SBT) may also be used.
  • Liner layers 230a-b are provided between the electrodes and the ferroelectric layer to reduce fatigue in the ferroelectric layer.
  • the liner layer comprises Ti0 2 enriched SRO (e.g., Ti0 2 doped SRO) .
  • the Ti0 2 increases the stability of the SRO layer which in turn, reduces the formation of flowerlike features.
  • the SRO is doped with 1-10 percent of Ti0 2 . Greater than 10% of Ti0 2 in the SRO film can increase the sheet resistance of the Ti0 2 enriched SRO layer beyond desirable limits, thus adversely impacting the performance of the capacitor.
  • the thickness of the Ti0 2 enhanced SRO layer is about 5-50nm
  • the ferroelectric layer is about 100-200nm
  • the electrode is about 10-lOOnm.
  • the preferred thickness of the Ti0 2 doped SRO is in the range of 5-50 nm, typical PZT thicknesses are 100-200 nm, Pt 10-100 nm.
  • the Ti0 2 enriched SRO layer is sputtered, in one embodiment, on the substrate.
  • Fig. 3 shows a sputtering system 301 used to deposit the Ti0 2 enriched SRO layer.
  • the system includes a substrate support 305 on which a substrate is mounted.
  • the substrate has been processed to include, for example, a conductive layer such as platinum to serve as the bottom electrode of the capacitor. Depending on the process, the conductive layer can be patterned or not.
  • the system also includes a sputtering target 310 comprising a SRO ceramic compound enriched with 1-10 percent of Ti0 2 .
  • atoms from the target react to form an amorphous layer 330 consisting of SrO, Ti0 2 and Ru0 2 on the substrate.
  • the parameters of the sputtering process are as follows: Pressure: 0.5 -1 Pa
  • Reactive gas Ar gas with 5 - 50 % volume weight %
  • the amorphous film is crystallized by an annealing process at, for example, a temperature of 450 - 700°C for about 30 seconds to 5 minutes.
  • excess SrO is transformed into SrTi0 3 (STO) .
  • STO is a stable material having a perovskite structure similar to that of PZT and other types of ferroelectric materials.
  • the Ti0 2 enriched SRO layer may also contain unreacted Ti0 2 grains 434, as shown in Fig. 4.
  • the STO and unreacted Ti0 2 grains serve as nucleation sites for the subsequently formed ferroelectric layer, triggering a very uniform grain structure in the ferroelectric layer and improved ferroelectric properties.
  • the process continues to form the ferroelectric capacitor and completion of the IC. This, for example, includes forming the ferroelectric layer, the second Ti0 2 enriched SRO layer, upper electrode, interconnects and interlevel dielectrics, passivation layer and packaging.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Physical Vapour Deposition (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)

Abstract

A liner layer comprising TiO2 enriched SRO is disclosed. The TiO2 enriched SRO liner improves the reliability of ferroelectric materials such as PZT without adversely impacting or degrading the ferroelectric properties of the PZT. The SRTO, in one embodiment is sputtered using an SRO target doped with 1-10% TiO2.

Description

IMPROVED MATERIAL FOR USE WITH FERROELECTRICS
FIELD OF THE INVENTION The present invention relates to ferroelectric integrated circuits and, more particularly, to materials that reduces fatigue in the ferroelectric material .
BACKGROUND OF THE INVENTION Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferrolectric semiconductor memory devices. A memory cell of the ferroelectric memory device includes a capacitor which serves as the storage element. Fig. 1 shows a conventional ferroelectric capacitor 101. As shown, the capacitor comprises a ferroelectric metal oxide ceramic layer 150 sandwiched between first and second electrodes 110 and 120. The electrodes typically are formed from a noble metal such as platinum. The ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell. However, fatigue in the ferroelectric material occurs after a certain number of switching cycles. To reduce fatigue in the erroelectric capacitor, strontium- ruthenium-oxide (SrRu03 or SRO) as a liner material directly attached between the ferroelectric film and the electrode has been proposed. SRO is typically formed by sputtering. A problem, however, exists with the use of SRO as a liner material due to the instability of its forming compounds Ru0 and SrO. Specifically Ru02 is a volatile oxide and SrO easily forms SrC03 if it is exposed to the atmosphere . Some Ru02 evaporates during the crystallization anneal of the amorphous film formed during sputtering, resulting in excess SrO in the SRO layer. This is undesirable because excess SrO produces flowerlike features on the surface of the SRO layer. Furthermore, SrO itself is an isolating material leading to a performance degradation of the ferroelectric capacitor.
To counterbalance the loss of Ru0 during crystallization, an SRO target with excess Ru02 is used. However, the excess Ru02 diffuses and reacts with the ferroelectric layer during high temperature crystallization of the ferroelectric material which degrades its ferroelectric properties.
From the foregoing discussion, it is desirable to provide an improved material which reduces fatigue without adversely impacting its ferroelectric properties .
SUMMARY OF THE INVENTION The invention relates to the use of materials which reduces fatigue in ferroelectric materials without adversely affecting its ferroelectric properties. In one embodiment of the invention, the material comprises SRO which is enriched with Ti02. The SRO comprises about 1-10 atomic weight percent (unless otherwise specified, all percentages are in atomic weight percent) of Ti02. In one embodiment, the Ti02 enriched SRO is formed on a substrate which is processed to include a first or bottom capacitor electrode. A ferroelectric material such as PZT is formed on the Ti02 enriched SRO. Subsequently, a second Ti02 enriched SRO layer is formed on the ferroelectric layer followed by formation of the upper electrode. In one embodiment, the SRO enriched layer is formed by sputtering using an SRO target doped with 1-10 percent % Ti02.
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 shows a conventional ferroelectric capacitor;
Fig. 2 shows a ferroelectric capacitor in accordance with one embodiment of the invention;
Fig. 3 shows an illustrative system for depositing the Ti02 enriched SRO layer in accordance with one embodiment of the invention; and
Fig. 4 shows an SRTO layer after a crystallization anneal .
DETAILED DESCRIPTION OF THE INVENTION Fig. 2 shows a ferroelectric capacitor 201 in accordance with one embodiment of the invention. Such a capacitor, for example, is used to form a ferroelectric memory cell of a ferroelectric memory IC. As shown, the capacitor comprises first and second electrodes 210 and 220. The electrodes are formed from, for example, platinum or a noble metal such as Ir, Pd, Ir02 or other conducting oxides. A ferroelectric layer 150 is located between the electrodes. In one embodiment, the ferroelectric material comprises PZT or lead-1anthanum- zirconium-titanate (PLZT) . Other types of ferroelectric material, such as Strontium-bismuth-tantalate (SBT) may also be used.
Liner layers 230a-b are provided between the electrodes and the ferroelectric layer to reduce fatigue in the ferroelectric layer. In accordance with the invention, the liner layer comprises Ti02 enriched SRO (e.g., Ti02 doped SRO) . The Ti02 increases the stability of the SRO layer which in turn, reduces the formation of flowerlike features. In one embodiment, the SRO is doped with 1-10 percent of Ti02. Greater than 10% of Ti02 in the SRO film can increase the sheet resistance of the Ti02 enriched SRO layer beyond desirable limits, thus adversely impacting the performance of the capacitor. In one embodiment, the thickness of the Ti02 enhanced SRO layer is about 5-50nm, the ferroelectric layer is about 100-200nm, and the electrode is about 10-lOOnm. The preferred thickness of the Ti02 doped SRO is in the range of 5-50 nm, typical PZT thicknesses are 100-200 nm, Pt 10-100 nm.
The Ti02 enriched SRO layer is sputtered, in one embodiment, on the substrate. Fig. 3 shows a sputtering system 301 used to deposit the Ti02 enriched SRO layer. The system includes a substrate support 305 on which a substrate is mounted. The substrate has been processed to include, for example, a conductive layer such as platinum to serve as the bottom electrode of the capacitor. Depending on the process, the conductive layer can be patterned or not. The system also includes a sputtering target 310 comprising a SRO ceramic compound enriched with 1-10 percent of Ti02.
During the sputtering process, atoms from the target react to form an amorphous layer 330 consisting of SrO, Ti02 and Ru02 on the substrate. The parameters of the sputtering process, for example, are as follows: Pressure: 0.5 -1 Pa
Temperature: room temperature to 650°C Power: 500-1000
Reactive gas: Ar gas with 5 - 50 % volume weight % After deposition, the amorphous film is crystallized by an annealing process at, for example, a temperature of 450 - 700°C for about 30 seconds to 5 minutes. During the anneal, excess SrO is transformed into SrTi03 (STO) . STO is a stable material having a perovskite structure similar to that of PZT and other types of ferroelectric materials. The Ti02 enriched SRO layer may also contain unreacted Ti02 grains 434, as shown in Fig. 4. The STO and unreacted Ti02 grains serve as nucleation sites for the subsequently formed ferroelectric layer, triggering a very uniform grain structure in the ferroelectric layer and improved ferroelectric properties. After the crystallization of the Ti02 enriched SRO layer, the process continues to form the ferroelectric capacitor and completion of the IC. This, for example, includes forming the ferroelectric layer, the second Ti02 enriched SRO layer, upper electrode, interconnects and interlevel dielectrics, passivation layer and packaging. While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.

Claims

What is claimed is:
1. A method for forming a ferroelectric capacitor comprising: providing a substrate having a first conductive layer formed thereon, the first conductive layer serves as a electrode of the capacitor; depositing a first amorphous liner layer on the electrode; depositing a ferroelectric layer on the first liner layer; depositing a second amorphous liner layer on the ferroelectric layer; and depositing a second conductive layer on the liner layer, the second conductive layer serves as a second electrode, wherein the liner layer comprises SRO enriched about 1-10% Ti02 weight percent, wherein the liner layers improve the properties of the ferroelectric layer.
2. The method of claim 1 wherein the ferroelectric layer comprises PZT.
3. The method of claim 2 wherein the first electrode comprises a noble metal.
4. The method of claim 3 wherein the first electrode comprises platinum.
5. The method of claim 1 wherein the electrodes comprise a noble metal .
6. The method of claim 5 wherein the electrodes comprise platinum.
7. The method of claim 1,2,3,4,5 or 6 further comprises an annealing process to crystallize the Ti02 enriched SRO layer.
8. The method of claim 7 wherein the annealing process comprise heating the Ti02 enriched SRO layer at a temperature of about 650°C for about 30 sec.
9. The method of claim 8 further comprising the steps for completing a ferroelectric memory IC.
10. The method of claim 7 further comprising the steps for completing a ferroelectric memory IC.
11. A method for forming a ferroelectric capacitor comprising: depositing a first amorphous layer on a substrate.; depositing a ferroelectric layer on the first liner layer; depositing a second amorphous liner layer on the ferroelectric layer; and depositing a second conductive layer on the liner layer, the second conductive layer serves as a second electrode, wherein the liner layer comprises SRO enriched with about 1-10% Ti02, wherein the liner layers improves the properties of the ferroelectric layer.
PCT/EP2002/009259 2001-08-31 2002-08-19 Improved material for use with ferroelectrics WO2003021656A2 (en)

Applications Claiming Priority (2)

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US94491801A 2001-08-31 2001-08-31
US09/944,918 2001-08-31

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005036612A3 (en) * 2003-09-26 2005-06-02 Toshiba Kk Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same
US7129196B2 (en) * 2003-07-21 2006-10-31 Los Alamos National Security, Llc Buffer layer for thin film structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3472087B2 (en) * 1997-06-30 2003-12-02 Ｔｄｋ株式会社 Film structure, electronic device, recording medium, and method for producing oxide conductive thin film
JPH11195768A (en) * 1997-10-22 1999-07-21 Fujitsu Ltd Electronic device including perovskite oxide film, method of manufacturing the same, and ferroelectric capacitor
JP3169866B2 (en) * 1997-11-04 2001-05-28 日本電気株式会社 Thin film capacitor and method of manufacturing the same
US6128178A (en) * 1998-07-20 2000-10-03 International Business Machines Corporation Very thin film capacitor for dynamic random access memory (DRAM)
JP2001196547A (en) * 2000-01-12 2001-07-19 Fujitsu Ltd Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7129196B2 (en) * 2003-07-21 2006-10-31 Los Alamos National Security, Llc Buffer layer for thin film structures
US7736761B2 (en) * 2003-07-21 2010-06-15 Los Alamos National Security, Llc Buffer layer for thin film structures
WO2005036612A3 (en) * 2003-09-26 2005-06-02 Toshiba Kk Ferroelectric capacitor with a complex-oxide hard-mask top electrode and method for manufacturing the same

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WO2003021656A3 (en) 2003-11-20

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