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WO2002054451A2 - Procede d'empilage de circuits integres - Google Patents

Procede d'empilage de circuits integres Download PDF

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Publication number
WO2002054451A2
WO2002054451A2 PCT/FR2001/004118 FR0104118W WO02054451A2 WO 2002054451 A2 WO2002054451 A2 WO 2002054451A2 FR 0104118 W FR0104118 W FR 0104118W WO 02054451 A2 WO02054451 A2 WO 02054451A2
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WO
WIPO (PCT)
Prior art keywords
layer
integrated circuit
integrated circuits
stacking
polymer
Prior art date
Application number
PCT/FR2001/004118
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English (en)
Other versions
WO2002054451A3 (fr
Inventor
Myriam Oudart
François Bernard
Marie-José MOLINO
Bruno Reig
Original Assignee
Thales
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales filed Critical Thales
Publication of WO2002054451A2 publication Critical patent/WO2002054451A2/fr
Publication of WO2002054451A3 publication Critical patent/WO2002054451A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/0106—Neodymium [Nd]
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    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé d'empilage d'un composant (6) (circuit intégré de petites dimensions) sur un circuit intégré de grandes dimensions (10). Selon ce procédé, la face du composant (6) opposée à la face portant ses plots de connexion est collée à la face du circuit intégré (10) qui porte des plots de connexion. Les deux types de circuits ont ainsi leurs faces portant leurs plots de connexion accessibles d'un même côté de l'empilement réalisé. Applications : Empilement de composants de types différents, par exemple MMIC sur ASIC.

Claims

REVENDICATIONS
1. Procédé d'empilage de circuits intégrés caractérisé en ce qu'il comporte les étapes suivantes :
- Dépôt d'au moins une première couche fine d'un matériau polymère (2, 2', 3) sur la surface d'un premier circuit intégré de grandes dimensions ;
- Dépôt d'une deuxième couche épaisse d'un matériau polymère (4) sur la surface de la première couche fine de matériau polymère ;
- Réalisation d'au moins une cavité (5) dans la deuxième couche épaisse de matériau polymère (4) ;
- Mise en place et collage dans la cavité (5) d'un composant de plus petites dimensions (6) avec sa face opposée à la face portant des plots de connexion en contact avec la première couche de matériau polymère (3) ; - Dépôt d'une troisième couche de matériau de matériau polymère (8) sur l'ensemble ;
- Réalisation de trous (9) traversant tout ou partie des trois couches de matériau polymère (3, 4, 8) pour atteindre les plots de connexion du premier circuit intégré et de trous traversant la troisième couche de matériau polymère pour atteindre les plots de connexion du deuxième circuit intégré ;
- Métallisation des trous et réalisation de connexion électrique.
2. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que les composants de petites dimensions (6) sont des circuits intégrés de plus petites dimensions que celles du premier circuit intégré.
3. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que les différentes étapes sont réalisées sur une plaquette (1) comportant plusieurs circuits intégrés de grandes dimensions de façon à empiler sur chacun de ces circuits, un ou plusieurs circuits intégrés de petites dimensions et en ce qu'après métallisation des trous, la plaquette est découpée en circuits individuels.
4. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que la première couche fine de matériau polymère (3) est réalisée sur la surface portant les plots de connexion d'une plaquette (1) de circuits intégrés, ensuite différents circuits de grandes dimensions (6) sont découpés dans la plaquette (1 ) puis sont placés dans une grille de positionnement (14), la deuxième couche épaisse de matériau polymère étant alors déposée sur chaque circuit intégré de grandes dimensions.
5. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que les différentes couches de matériaux polymères sont réalisées à l'aide d'un même matériau polymère.
6. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que le circuit intégré de grandes dimensions comporte différents niveaux de connexion et en ce qu'au moins une fine couche de polymère (3) est réalisée sur ces différents niveaux de connexion.
7. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que le circuit intégré de petites dimensions (6) est collé ou brasé aux circuits intégrés de grandes dimensions à l'aide d'un matériau de collage ou de brasage (7).
8. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que la somme des épaisseurs du composant et de la colle est sensiblement égale à l'épaisseur de la deuxième couche de polymère (4).
9. Procédé d'empilage de circuits intégrés selon la revendication 1 , caractérisé en ce que la deuxième couche de matériau de polymère (4) sert de cale de façon que la surface supérieure du composant (6) affleure la face supérieure de la couche de matériau polymère (4).
10. Procédé d'empilage de circuits intégrés selon la revendication
1 , caractérisé en ce que la troisième couche de polymère (8) est déposée en phase liquide et sous vide.
11. Procédé d'empilage de circuits intégrés selon la revendication 9, caractérisé en ce que l'ensemble est placé sous vide dans un sac et qu'un outil plat permet d'exercer une pression sur la couche de polymère de façon à ce que cette couche de polymère pénètre entre les parois de la cavité (5) et le circuit intégré(6).
12. Empilement de circuits intégrés, caractérisé en ce qu'il comporte : 8
- un premier circuit intégré (10) d'un premier type de technologie et de grandes dimensions portant sur ses faces (15) au moins une couche d'isolant (2, 27, 3) sur laquelle sont prévus des circuits de connexion, - au moins un deuxième circuit intégré (6) d'un deuxième type de technologie et de plus petites dimensions collé par sa face opposée à celle portant ses connexions, à la couche d'isolant (3) du premier circuit intégré, ce deuxième circuit intégré étant encastré dans une couche de matériau polymère (4) dont la face supérieure affleure la face supérieure du deuxième circuit intégré,
- au moins une couche de matériau isolant (8) réalisée sur la face supérieure de la couche de matériau polymère (4) et sur la face supérieure du deuxième circuit intégré (6), - des circuits de connexion réalisés sur la face supérieure de la couche de matériau isolant (8) et des éléments de connexion (31 , 51) traversant la couche d'isolant (8) et/ou la couche de matériau polymère (4) connectant lesdits circuits de connexion à des plages de connexions des premier et deuxième circuits intégrés.
PCT/FR2001/004118 2000-12-28 2001-12-20 Procede d'empilage de circuits integres WO2002054451A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR00/17232 2000-12-28
FR0017232A FR2819100B1 (fr) 2000-12-28 2000-12-28 Procede d'empilage de circuits integres

Publications (2)

Publication Number Publication Date
WO2002054451A2 true WO2002054451A2 (fr) 2002-07-11
WO2002054451A3 WO2002054451A3 (fr) 2002-10-10

Family

ID=8858352

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PCT/FR2001/004118 WO2002054451A2 (fr) 2000-12-28 2001-12-20 Procede d'empilage de circuits integres

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FR (1) FR2819100B1 (fr)
WO (1) WO2002054451A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447850A3 (fr) * 2003-02-13 2010-07-21 Shinko Electric Industries Co., Ltd. Structure d'empaquetage d'un élément électronique et méthode de fabrication associèe

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10214847A1 (de) * 2002-04-04 2003-10-23 Diehl Munitionssysteme Gmbh Flexibler dünner Schaltungsaufbau
WO2004112136A1 (fr) * 2003-06-12 2004-12-23 Koninklijke Philips Electronics N.V. Dispositif electronique
EP3869554A4 (fr) * 2018-11-09 2022-03-23 Huawei Technologies Co., Ltd. Puce intégrée à au moins deux dés

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2153144A (en) * 1984-01-13 1985-08-14 Standard Telephones Cables Ltd Circuit packaging
US5994739A (en) * 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device
US5422513A (en) * 1992-10-16 1995-06-06 Martin Marietta Corporation Integrated circuit chip placement in a high density interconnect structure
US6025995A (en) * 1997-11-05 2000-02-15 Ericsson Inc. Integrated circuit module and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1447850A3 (fr) * 2003-02-13 2010-07-21 Shinko Electric Industries Co., Ltd. Structure d'empaquetage d'un élément électronique et méthode de fabrication associèe
US7964950B2 (en) 2003-02-13 2011-06-21 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same

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Publication number Publication date
WO2002054451A3 (fr) 2002-10-10
FR2819100B1 (fr) 2003-08-08
FR2819100A1 (fr) 2002-07-05

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