WO2002052719A1

WO2002052719A1 - Linearized power amplifier unit

Info

Publication number: WO2002052719A1
Application number: PCT/SE2001/002846
Authority: WO
Inventors: Mark Briffa
Original assignee: Allgon Ab
Priority date: 2000-12-22
Filing date: 2001-12-20
Publication date: 2002-07-04
Also published as: SE0004791D0; SE0004791L

Abstract

Feed-forward linearized power amplifier unit comprising a signal cancellation loop (SCL) and a distortion cancellation loop (DCL), each loop comprising an amplifying branch and a time delay branch, respectively, wherein the power amplifier unit is provided with an input and an output. A measurement output is arranged at the output of the first summation point of the SCL, adapted to be used when performing a distortion cancellation loop (DCL) test step, and that a remotely controllable switch is arranged in the time delay branch of the signal cancellation loop, adapted to be opened when performing a distortion cancellation loop (DCL) test step. The invention also comprises a method in a power amplifier unit.

Description

Title

Linearized Power amplifier unit.

Field of the invention The present invention relates to a method of testing a feed-forward linearized power amplifier unit.

Background of the invention

When using frequency modulation (FM) or phase modulation (PM) for transmitting information all information is dependent of the phase of the signal and no information is dependent of the amplitude. Hence, the amplitude is constant, and the phase and frequency changes. In an FM or PM signal no linear amplification is needed and it is therefore possible to use non-linear amplifiers.

When using amplitude modulation (AM) all information lies in the amplitude of the transmitted signal and therefore an AM signal must be linearly amplified.

In order to maximize the amount of information that can be transmitted for a given bandwidth a combination of both AM and PM is typically utilized. Common examples are Quadrature Amplitude Modulation (QAM) and π/4 shift Quadrature Phase Shift Keying (QPSK). These modulation schemes are commonly referred to as linear modulation schemes and also require linear amplification.

Linear modulation schemes may be represented in Cartesian representation in the form of a phase plane trajectory diagram where each position represents a particular amplitude and phase of the RF (radio frequency) carrier, π/4 shift QPSK has 8 different positions that each represent a unique piece of information. The π/4 shift QPSK signal is both amplitude and phase modulated and it is therefore necessary to use a linear power amplifier when amplifying such a signal.

Two main problems can be identified for power amplifiers that are non-linear: 1) AM/AM distortion and AM/PM distortion in power amplifiers. AM/AM distortion is the creation of an additional undesired AM when a non-linear amplifier is excited by an input AM signal. AM/PM distortion is the creation of an additional undesired PM when a non-linear amplifier is excited by an input AM signal. Both these distortions cause the output signal to deviate from the intended position of the trajectory diagram. This results in the transmission of erroneous information from the antenna that is typically connected at the output of the power amplifier. Error vector magnitude (EVM) is commonly used to describe the degree of this error and hence the quality of the transmitter. It can thus be summarized that AM/ AM and AM/PM distortion cause a degradation of the error vector magnitude.

2) Adjacent channel interference (ACI) or inter-modulation (IM) distortion. When linearly modulated radio frequency signals are distorted new signals at other frequencies are generated. This is commonly referred to as intermodulation distortion. This IM falls on odd multiples of the signal frequencies present. In practice the result is that interference is generated on near-by channels. This interference is commonly referred to as adjacent channel interference. The two closest adjacent channels on either side of the transmitted channel are called the first adjacent channels. ACI must be suppressed since it may become impossible for users of the adjacent channels to communicate.

The main object of a linearized power amplifier is to avoid the two problems identified above.

Another object of a linearized power amplifier is that it should be sufficiently broadband to equally amplify the input signal over a wide range of frequencies.

The above discussion, which relates to single carrier transmissions, is also applicable for multicarrier signals.

When two or more modulated carriers are combined the result is typically a signal containing amplitude modulation even if the original signals were, for example, two FM or GMSK (Gaussian Minimum Shift Keying) signals with constant amplitudes but varying phases. Typically, multi-carrier signals are composed of several modulated carriers. The modulation schemes vary depending on the application. Some common examples are FM, GMSK, π/4 shift QPSK, 8-PSK (Phase Shift Keying), CDMA (Code Division Multiple Access) and WCDMA (Wideband CDMA) for mobile telephony systems; QAM (Quadrature

Amplitude Modulation) for microwave and satellite links; and VSB (Vestigal Sideband) for cable television applications.

To summarize then, MultiCarrier signals must be linearly amplified due to their inherent amplitude modulation.

One important use for linearized power amplifiers is when amplifying a signal to be applied to an antenna in a base station in a cellular mobile system. Normally one base station with one antenna communicates with many mobile stations using many channels, one for each mobile station. In many prior art systems each channel is designated a transceiver provided with a power amplifier that amplifies the signal. The amplified signals from all channels are then combined prior to being forwarded to the antenna. If the input signal is not amplitude modulated the power amplifier need not be linear. But if the input signal is amplitude modulated then the power amplifier must be linear.

One problem with this prior art technique is that when combining already high power amplified signals, .considerable power losses occur. The high power combining technique is usually tuned. This restricts the frequency locations that can be used without the need to re-tune.

Having a linearized high power amplifier offers the possibility of combining signals at much lower powers thereby avoiding both high power combining losses, and tuning. The possibility to frequency-hop and allocate channel frequencies dynamically is therefore possible and can thus be used to increase capacity. Combining at low power does however set very high linearity requirements on the linearized power amplifier.

A linearized high power amplifier also enables the power amplification of signals that are digitally combined and generated. This can be achieved through combining digital representations of several single individually modulated carriers or using modulation schemes that inherently combine many channels, e.g. CDMA and WCDMA where many users utilize the same carrier and have different unique codes assigned to identify different channels /users.

All RF amplifiers are nonlinear to some degree, and consequently generate intermodulation (IM) components if the input signal fluctuates in amplitude. In most applications of interest, there are strict limits on the level and frequency distribution of IM power. Examples include mobile and satellite links carrying either single channels with non-constant envelope or multiple channels in any modulation format. The latter is common in base station transmitters. Another example is a cable television (CATV) system, with either coax or fiber trunks.

If the signal carried by the amplifier has an envelope that fluctuates in magnitude, such as a multicarrier signal or a linear data modulation, then the non-linear operation generates intermodulation (IM) products in the amplifier output. These IM products represent unwanted interference in the operating band of the amplifier. Although it is possible to reduce the power of the IM products relative to the power of the desired signal by reducing the drive level of the amplifier, this approach also reduces the power efficiency of the amplifier. Increasing the linearity of the amplifier by means of external circuitry can be a more efficient alternative.

US-5,489,875 discloses an adaptive feedforward linearizer for RF power amplifiers with two loops: a signal cancellation loop (SCL) and a distortion cancellation loop (DCL). The main concern with this patent is how to make the system adaptive. In order to achieve this, two controllers are arranged, one for each loop. These controllers are used to control a first and a second delay, gain and phase adjusters (DGPA) in order to adapt the DGPAs to changes in the applied signals and to environmental conditions such temperature and time.

Although the power amplifier of US-5,489,785 is adaptive and therefore arranged to continuously adjust the delay, gain and phase, some initial measurements are always performed in order to be able to initially adjust the components of the two loops. Furthermore, it is advantageous to remove and trim amplitude variations with frequency and more elaborate phase variations with frequency than only delay adjustment can provide (a delay adjustment can be considered as a means of adjusting the phase slope versus frequency) . In general the removal of these amplitude and phase variations can be referred to as frequency equalization. Additionally, more complex forms of frequency equalization may be difficult to adapt with real-life signals without causing a degradation in the IM performance of the linearized power amplifier.

The US-patent does not discuss these initial measurements and the practical problems related to them in order to achieve a cost efficient and optimal production process, especially when producing large series of linearized power amplifiers.

The SCL can be tested and assessed in production by applying a signal at the input of the system and measuring the signal at the output of the summation point of the SCL. The measurement point is therefore typically inside the physical enclosure of the feed-forward system.

Testing of the DCL requires intrusively inserting a test signal into SCL and then measuring the at the output of the feed-forward system. The point of signal insertion is therefore also typically inside the physical enclosure.

In order to perform these tests of the feedforward system the enclosure must be opened in order to measure the error signal of the SCL and to insert the DCL test signal. This implies that additional time consuming assembly steps must be performed.

The mechanical construction of the enclosure must also contain additional costly details to allow RF shielding when the lid or final mechanical detail of the enclosure is removed for testing. The object of the present invention is to achieve a less time consuming and a more optimal test procedure when producing a ready to use feedforward linearized power amplifier unit.

Another object of the present invention is to allow the trimming and adjustment of frequency equalization in each of the loops in a time efficient and effective manner.

Summary of the invention The above-mentioned objects of the present invention are achieved by a method and a unit according to the independent claims.

Preferred embodiments are set forth in the dependent claims.

The solution of the above-mentioned problem is a combination of placing a detector at the output of the summation point of the SCL in order to provide externally an electrical representation of the error signal via a typically existing external computer interface, and of arranging a remotely activated RF switch in the time delay branch of the SCL. This allows a DCL test signal to be inserted at the input of the system without having to break into the active branch of the SCL.

According to the present invention intrusion into the feedforward unit during testing procedures is avoided, and the unit can therefore be fully assembled when the test is performed. This implies that no additional assembly steps need to be performed after testing, thereby saving time and hence production costs.

Another advantage is that the number of mechanical details are reduced since shielding (in order to achieve reliable test results) need to be achieved only with the enclosure sealed, which also reduces production costs and weight.

Short description of the appended drawings

Figure 1 shows a simplified block diagram of a linearized feedforward power amplifier according to prior art. Figures 2a-2e show signals at different points in the power amplifier disclosed in figure 1.

Figure 3 is an illustration of prior art feedforward linearization applied at RF.

Figure 4 shows a power amplifier unit according to the present invention.

Figure 5 shows a representation of signals obtained during the method of testing a power amplifier unit according to a preferred embodiment of the present invention.

Figure 6 shows a preferred embodiment of the power amplifier unit according to the present invention.

Detailed description of preferred embodiments of the invention

With references to figure 1 a prior art feedforward linearized power amplifier will now be described.

In simplified terms, a linearized feedforward power amplifier cascades a signal cancellation loop (SCL, first loop) and a distortion cancellation loop (DCL, second loop).

The signal cancellation loop has two branches, a first branch which comprises a first gain and phase adjuster (GPAl) and a main power amplifier (MPA) whose output is to be linearized. In particular, the amplifier's output consists of an amplified version of an input signal, plus intermodulation (IM) distortion, referenced in the figure as an addition of distortion, "d". This first branch of the SCL starts at the input 2 and ends at the output of the first summation point 10 via GPAl and MPA.

The second branch of the signal cancellation loop comprises a first time delay τi chosen to match the delay of the first branch, i.e. GPAl and MPA, and starts at the input 2 and ends at the output of the first summation point 10. The distortion cancellation loop has two branches. A first branch of the distortion cancellation loop comprises a second time delay τ₂ chosen to match the delay of the second branch of DCL, i.e. GPA2 and EPA. The first branch of the DCL starts at the output of the MPA 4 and ends at the output 14 of the second summation point 12.

The second branch of DCL comprises a second gain and phase adjuster (GPA2) and an error power amplifier (EPA) . In particular, the output of the error power amphfier consists of an amplified version of error signal. The second branch of the DCL starts at the output of the MPA 4 and ends at the output 14 of the second summation point 12 via GPA2 and EPA.

Figures 2a-2e are intended to illustrate the principle of the prior art feedforward linearized power amplifier shown in figure 1. In figures 2a-2e different frequencies are represented along the horizontal line and the height of the vertical lines represents the amplitude for a given frequency. The different figures naturally only illustrate the amplitude relationship between different frequencies. Figure 2a is non-amplified but figures 2b-2e are amplified.

By way of example, the input RF signal 2 to be amplified comprises two distinct frequencies, typically two carriers, relatively close to each other having the same amplitude and is illustrated in figure 2a as two vertical lines.

Figure 2b illustrates the signal in the point referenced as 4 in figure 1 where, in addition to the input RF signal, distortion is undesirably added to the signal seen as additional signals in adjacent channels. A suitably scaled signal sample of the MPA output 4 is taken and applied to summation point 10. The scaling is chosen such that the amplitude of this signal is reduced and made equal to the signal arriving at summation point 10 via the second branch of the SCL.

In the second branch of the SCL, the input signal 2 is delayed and applied to summation point 10. Thus, the signals arriving at the first summation point 10 should have the same amplitude but opposite phase. If they are not, the error signal 6 provided to the distortion cancellation loop DCL will not contain distortion only but an undesirable unsuppressed amount of the input RF signal.

Figure 2c illustrates the error signal at the point referenced as 6 in figure 1.

The error signal is amplified by the error power amplifier EPA such that is it at the same level as the MPA distortion arriving at summation point 12 via the DCL delay branch τ . It is then apphed out of phase at the point referenced as 8 in figure 1 and is illustrated in figure 2d.

Figure 2e illustrates the summation of the signals depicted in figure 2b and figure 2d, and is ideally an amplified direct replica of the input RF signal 2.

Again referring to figure 1, the task of the GPAl and GPA2 in series with both power amplifiers MPA and EPA is therefore to adjust the gain and phase of the signals they process such that they arrive at the respective summation points with the correct magnitude and phase.

For broadband performance the correct gain and phase must be maintained over a range of frequencies i.e. both the gain and phase frequency response must be ideally fiat. Since both the MPA and EPA have a phase characteristic that decreases with frequency, a similar phase shift is needed in each of the opposing branches. This decreasing phase shift is obtained by the first time delay τi and the second time delay τ₂, respectively.

Figure 3 is an illustration of prior art feed-forward linearization applied at RF. It is well known in the art that the summation blocks (10, 12) and tap points (2, 4, 6) can be realised at RF using couplers. The figure also illustrates that both the DCL test input connector (indicated by a circle) and SCL test output connector (also indicated by a circle) are located inside the enclosure. The enclosure must therefore be opened in order to access these connection points. Figure 4 is a block diagram illustrating the present invention. In addition to the block diagram disclosed in figure 3 showing a prior art linearized power amplifier is arranged a measurement output 16 provided with a measurement means 18 and a remotely controllable (indicated by an arrow) switch 20 arranged at the delay branch of the SCL. One obvious way to control the switch is by means of a digital control signal.

It should be noted that the measurement output 16 is already present in most prior art feed-forward power amplifiers, see e.g. US-5,489,875, where it is used for controlling purposes. However it is not discussed in US-5,489,875 whether this output is available outside a physical enclosure of the power amplifier. According to the present invention this output is preferably located outside the physical enclosure as an electrical representation of the signal level at point 6. The measurement means 18 may e.g. be a diode and an amplifier, or some kind of IC-circuit used to interpret the analogue signal. Additionally the analogue output is A/D converted and presented as a digital word using some kind of processing unit inside or outside the enclosure of the power amplifier unit. A person skilled in the art of signal processing is aware of numerous different methods applicable.

Figure 5 shows a representation of a so-called suppression diagram, showing signals obtained during the method of testing a power amplifier unit according to a preferred embodiment of the present invention.

The suppression diagram in figure 5 illustrates in particular the signal obtained in measurement point 16. The vertical line indicates the suppression in dB and the horizontal line indicates the frequency in Hertz.

When performing the test according to the present invention a typical test signal comprises a frequency sweep covering a broad range of frequencies including the center frequency representing the carrier frequency where infinite suppression should be achieved. Prior to each main test step a pre-test step for calibration purposes is performed. In the pre-test step for testing the SCL, the frequency test signal is apphed through the delay branch τi only by for example turning off the MPA. The measurement output 16 is then manipulated and stored such that it represents OdB across the band of measurement (see figure 5 reference sign 22). The so called manipulation procedure is well known in the art and is often referred to as calibration.

During the main test step of the SCL the MPA is turned on and GPAl is adjusted until good suppression is obtained (illustrated by double-arrows) in the center frequency, see reference sign 24. Suppression in the SCL is therefore measured without opening the enclosure. Typically a minimum level of suppression is required over a certain bandwidth. The required level of suppression is mainly dependent on the size of the EPA. The required bandwidth is dependent on the desired bandwidth of the application. For illustrative purposes a level of 30dB suppression over 20 MHz is shown in figure 5. In order to achieve the desired levels of suppression over a given bandwidth, the amplitude and phase characteristics versus the frequency of both branches must be similar. Deviations result in non-destructive cancellation and therefore reduced suppression. This is well known in the art. If for example the length of the delay line is not correctly adjusted smaller suppression bandwidth results.

The DCL requires a broader suppression bandwidth compared to SCL in order to suppress IM. This suppression is usually more difficult to achieve.

In the pre-test or calibration step for testing the DCL, the frequency test signal is only applied through the delay branch τ₂ by opening the RF switch 20 via an electrical stimulus outside the enclosure. The output 14 is then measured, manipulated and stored such that it represents OdB across the band of measurement.

During the main test step of the DCL switch 20 is closed and GPA2 is adjusted until good suppression is obtained in the center frequency. Suppression in the DCL is therefore measured without opening the enclosure. A preferred embodiment of the invention is illustrated in figure 6 where a first frequency equalization block (EQ1) is arranged in one or both branches of the SCL and a second frequency equalization (EQ2) block is arranged in one or both branches of the DCL (in figure 6 the equahzation blocks are arranged in the MPA and EPA branches respectively). The reason to include these blocks is to be able to remove, or at least reduce, gain and phase variations versus frequency. The intention with the EQ blocks is also to allow fine trimming of the delay (phase slope) in order to remove variations resulting from component tolerances and thus simplify production. This trimming of the delay, or more generally, to set default parameters for the EQ block, may be done in dependence of the level of suppression obtained from the measurements performed by the SCL test steps and the DCL test steps. Apart from the added blocks EQ 1 and EQ2 the embodiment disclosed in figure 6 corresponds to the embodiment shown in figure 4 and it is therefore referred to the above description of figure 3.

The present invention is not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appending claims.

Claims

1. Method of testing a feed-forward linearized power amplifier unit comprising a signal cancellation loop (SCL) including a Main Power Amplifier (MPA) branch and a time delay (τi) branch and a distortion cancellation loop (DCL) including an amphfying branch and a time delay (τ₂) branch, the SCL further comprises a first Gain and Phase Adjuster (GPAl) and the DCL further comprises a second Gain and Phase Adjuster (GPA2), the power amphfier unit is provided with an input and an output, the method comprising two main steps A and B:

A) signal cancellation loop (SCL) test step, comprising the following sub-steps: al) deactivating the signal path through the MPA branch, a2) applying a test signal at the input of the power amplifier unit (2) , a3) calibrating the measurements by measuring the level of the output signal at a measurement output of the first summation point (6) of the SCL and letting the result represent OdB with the signal path through the MPA deactivated, a4) activating the signal path through the MPA branch, a5) adjusting GPAl such that suppression is achieved, a6) measuring the suppression level of the output signal at a measurement output of the first summation point (6) of the SCL with the signal path through the MPA activated.

B) distortion cancellation loop (DCL) test step, comprising the following sub- steps: bl) opening of a remotely controllable switch (20) arranged in the time delay branch of the signal cancellation loop, b2) applying a test signal at the input (2) of the power amphfier unit, b3) calibrating the measurements by measuring the level of the output signal at the output of the power amplifier unit (14) and letting the result represent OdB with the said remotely controllable switch open, b4) closing of the said remotely controllable switch, b5) adjusting GPA2 such that suppression is achieved, b6) measuring the suppression level of the output signal at the output of the power amplifier unit (14) with the said remotely controllable switch closed.

2. Method according to claim 1, characterized in that said test steps A and B is performed when said power amphfier unit is physically encapsulated.

3. Method according to claim 2, c h ar ac te rize d in that said measurement output is available outside the encapsulation of the power amplifier unit.

4. Method according to any preceding claim, characterized in that said test signal comprises a frequency sweep.

5. Method according to claim 4, c h a r a c t e r i z e d in that the level of the output signal in substep a6) represents the level of SCL suppression as a function of the input frequency sweep.

6. Method according to claim 4, characterized in that the level of the output signal in substep b6) represents the level of DCL suppression as a function of the test signal frequency sweep.

7. Feed-forward linearized power amplifier unit comprising a signal cancellation loop (SCL) and a distortion cancellation loop (DCL), each loop comprising an amplifying branch and a time delay branch, respectively, wherein the power amplifier unit is provided with an input and an output, characterized in that a measurement output is arranged at the output of the first summation point of the SCL, adapted to be used when performing a distortion cancellation loop (DCL) test step, and that a remotely controllable switch (20) is arranged in the time delay branch of the signal cancellation loop, adapted to be opened when performing a distortion cancellation loop (DCL) test step.

8. Power amphfier unit according to claim 7, characterized in that said test steps are performed when said power amphfier unit is physically encapsulated.

9. Power amphfier unit according to claim 8, characterized in that said measurement output is available outside the encapsulation of the power amplifier unit.

10. Feed-forward linearized power amplifier unit comprising a signal cancellation loop (SCL) and a distortion cancellation loop (DCL), each loop comprising an amplifying branch with a frequency equalizer (EQ1, EQ2) and Gain- Phase Adjuster (GPAl, GPA2) and a time delay branch, respectively, wherein the power amplifier unit is provided with an input and an output, characterized in that a measurement output is arranged at the output of the first summation point of the SCL, adapted to be used when performing a distortion cancellation loop (DCL) test step, and that a remotely controllable switch is arranged in the time delay branch of the signal cancellation loop, adapted to be opened when performing a distortion cancellation loop (DCL) test step.

11. Power amphfier unit according to claim 10, characterized in that said frequency equalizers (EQ1, EQ2) are adapted to be adjusted in dependence of the level of the suppression obtained in said test steps.

12. Power amplifier unit according to claim 10 or 11, characterized in that said test steps are performed when said power amplifier unit is physically encapsulated.

13. Power amphfier unit according to claim 12, characterized in that said measurement output is available outside the encapsulation of the power amplifier unit.