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WO2002015231A2 - A method for patterning layers of semiconductor devices - Google Patents

A method for patterning layers of semiconductor devices Download PDF

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Publication number
WO2002015231A2
WO2002015231A2 PCT/EP2001/009082 EP0109082W WO0215231A2 WO 2002015231 A2 WO2002015231 A2 WO 2002015231A2 EP 0109082 W EP0109082 W EP 0109082W WO 0215231 A2 WO0215231 A2 WO 0215231A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
chemistry
etching
etch
tin
Prior art date
Application number
PCT/EP2001/009082
Other languages
French (fr)
Other versions
WO2002015231A3 (en
Inventor
Lars Paschedag
Ricky Mc Gowan
Virinder Grewal
Steffen Schneider
Original Assignee
Motorola, Inc.
Semiconductor 300 Gmbh & Co. Kg
Infineon Technologies Ag
Applied Materials Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc., Semiconductor 300 Gmbh & Co. Kg, Infineon Technologies Ag, Applied Materials Gmbh filed Critical Motorola, Inc.
Publication of WO2002015231A2 publication Critical patent/WO2002015231A2/en
Publication of WO2002015231A3 publication Critical patent/WO2002015231A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Definitions

  • the present invention generally relates to the production or fabrication of semiconductor devices and more particularly to a method for patterning layers of semiconductor devices which is performed during the production of semiconductor devices.
  • the etching of the metallic layers is performed in a single step using a special chemistry in a plasma etch chamber .
  • a Ti-layer and/or a TiN-layer might be used as an anti-reflection layer or an extra organic anti-reflection layer has to be used.
  • the wavelength can be 365 run, so that no extra organic anti-reflection layer is needed.
  • DUV deep ultraviolet light
  • an organic anti-reflection layer is needed.
  • the opening of the organic anti-reflection layer is normally performed in an oxide-etch-tool in which usually oxide etches are performed. This leads to a time-consuming method for the opening of the organic anti-reflection layer and the complete metal etch.
  • the metal etch of all metal layers in one step with the same chemistry further leads to etch results which are sometimes not uniform over the wafer.
  • much time is needed for the complete metal etch, i.e. the metal etch, the resist strip, the passivation, the polymer removal and the opening of the anti- reflection layer, because a lot of steps are used which are performed in different chambers of the processing line or production line.
  • moire oxide-etch chambers have to be used although there still exists a capacity in the metal-etch tool.
  • Fig. 1 to 4 illustrate enlarged, cross-sectional views of the production steps of the patterning of layers of semiconductors and especially of the etching of the metal-1-layer of a 64 Mbit chip in a first embodiment of the invention
  • Fig. 5 to 8 illustrate enlarged, cross-sectional views of the production steps of the patterning of layers of semiconductors and especially of the etching of the metal-1-layer of a 64-Mbit chip in a second embodiment of the invention.
  • the present invention provides a method for patterning layers of semiconductor devices, starting with providing a workpiece having a substrate, an Al-layer and a layer of TiN and a layer of TiN.
  • the method comprises the further step of etching the layer of TiN, and the layer of TiN selectively to the underlying Allayer or Al alloy with a chemistry comprising CF and Cl .
  • Al-layer and “layer of Al” also stands for layer of Al alloy
  • the term “layer of TiN" of "TiN layer” also stand for a layer of Ti only.
  • this method shows a big advantage because the selectivity of the etch step to Ti or TiN with respect to Al or Al alloys leads to a complete etching of the TiN-pattern or a pattern of the Ti/TiN-stack without the loss or without an etching of aluminum or an aluminum alloy. This reveals a good starting point for a uniform aluminum etch.
  • a step of etching an organic anti-reflection layer is performed with a chemistry comprising CF and Cl 2 .
  • This etching step is performed in the etch chamber in which the titanium-nitride or titanium stack etching step and the aluminum etching step is performed.
  • the semiconductor material or the wafer or the workpiece which is treated does not have to be transported from an oxide-etch chamber of the oxide-etch tool to a metal-etch chamber of the metal-etch tool.
  • other processes in between do not necessarily have to be performed. This leads to a shorter overall processing time and a processing time which does not need so many oxide-etch chambers.
  • the utilization of capacity of the processing line and especially the metal-etch tool is improved with this method.
  • the pattern is defined by a resist which is located on top of the workpiece.
  • the etching is preferably performed in a plasma and especially via an reactive ion etch (RIE) .
  • RIE reactive ion etch
  • the method further comprises the step of etching the Al-layer or the layer of the Al alloy with a chemistry comprising BC1 3 , Cl 2 or N 2 or a mixture of said chemistry.
  • This etch step is also preferably performed via RIE.
  • the method further comprises the step of removing sidewall polymers being produced during the etching of the Al-layer or the layer of the Al alloy and/or an underlying Ti-layer.
  • the walls of the chamber during the above mentioned aluminum etch are heated to prevent the walls from the chamber from being contaminated by polymers .
  • the walls are held at a temperature of > 60°C, preferably > 80°C.
  • a removing of the sidewall polymers is performed in situ in the metal-etch chamber by using a plasma of nitrogen (N 2 ) . If all passivation polymers are removed in this step, the following wet cleaning ,can be omitted. This saves work in the process flow and omits problems imposed by wet cleaning, e.g. electro-corrosion. If not all polymers have been removed in the previous step or no plasma etch for the removing of sidewall polymers is performed, the method preferably further comprises the steps of passivating the metal and removing the residual resist mask in a strip chamber of the metal-etch tool. Preferably, a chemistry especially a plasma chemistry of H0, N 2 or 0 2 or a mixture of said chemistry is used.
  • a plasma is used to perform the etching or the removing.
  • the etching is performed in a single chamber.
  • the single chamber is a metal-etch chamber.
  • the above mentioned problem is also solved by a method for patterning layers of semiconductor devices starting with providing a workpiece comprising at least an anti- reflection layer, wherein a following step is performed in which only the anti-reflection layer is etched with a chemistry comprising CF 4 and Cl 2 .
  • This also leads to a shorter overall processing time and a processing line which does not need so many oxide-etch chambers. This further leads to a more uniform aluminum etch or aluminum alloy etch.
  • a metal etch is further performed with a chemistry comprising BC1 3 , Cl 2 or N 2 or a mixture of said chemistry.
  • a chemistry comprising BC1 3 , Cl 2 or N 2 or a mixture of said chemistry.
  • the etch steps are performed in a single chamber.
  • the anti-reflection layer is at least partly organic.
  • the anti-reflection layer further comprises a layer of TiN or a layer of Ti and a layer of TiN.
  • the anti-reflection layer is a layer of TiN or a layer of Ti and a layer of TiN, e.g. a stack of Ti- and TiN-layers.
  • etching a layer of Al or a layer of an Al alloy and/or a Ti-layer, being located under the Al-layer or the Al-alloy layer with a chemistry comprising BC1 3 , Cl 2 or N 2 or a mixture of said chemistry in said metal-etch chamber,
  • a method for providing a metallic microstructure starting with a workpiece comprising a substrate and a stack of layers of which at least a Ti-layer or a TiN-layer is located between the substrate and an Al-layer or a layer of an Al alloy, whereas the method comprises the steps of - patterning the Al-layer or the layer of the Al alloy, and
  • the invention uses the insight that a chemistry of CF 4 and Cl 2 is selectively etching Ti or TiN and not etching Al or Al alloys.
  • the methods according to the invention are performed in a 300mm - (diameter of wafers) process technology of the production of semiconductor devices. It is, however, not restricted to 300mm - process technology.
  • Fig. 1 illustrates an enlarged, cross-sectional view of an embodiment of the present invention in a beginning stage of fabrication of the metal layer. It is shown an already structured resist 1 which is especially a developed photoresist mask.
  • the photoresist 1 is on top of a TiN-layer 4 which is on top of a Ti-layer.
  • an i-line photoresist 1 is used.
  • a wavelength of 365 n is used.
  • the TiN-layer 4 and the Ti-layer 5 deal as anti-reflection layers.
  • the Al- alloy layer is above the layer of Ti which is a so-called Ti-liner 8.
  • the Ti-layer 8 or -liner is located above the Si0 2 -layer 9.
  • a selective breakthrough is performed in a metal-etch chamber by using a plasma chemistry of a CF 4 and Cl 2 .
  • This chemistry only etches the anti-reflection layer which is in this embodiment the TiN-layer 4 and the Ti-layer 5.
  • the etching stops selectively on the aluminium-alloy layer 6.
  • the aluminum alloy is for example Al, Cu which consists for ⁇ example of 0,5 % copper.
  • the selective etching leads to a good starting point for a uniform aluminum etch in the following.
  • Fig. 2 illustrates the structure of Fig. 1 further along in processing and illustrates the selective etching of the anti-reflection layer.
  • Fig. 3 illustrates the structure of Fig. 2 further along in processing.
  • the metal-1 etch is performed in the metal-etch chamber by using a plasma chemistry of BC1 3 , Cl 2 or N 2 or a mixture thereof.
  • the sidewall polymers 10 which were produced during the metal etch are then removed in situ in the same metal- etch chamber by using a N 2 -plasma or in another chamber by using a wet chemistry. If the resist 1 is not too thick, it can also be removed in the metal-1-etch in the metal-etch chamber, i.e. during the step, which would directly lead to the structure of Fig. 4.
  • the wafer or the workpiece is transported into a strip chamber of the metal-etch and there, the resist 1 is removed and the metal layers 4 to 8 are passivated towards corrosion by using a plasma chemistry comprising H 2 0, 0 or N 2 or a mixture of this chemistry. It is preferred that the passivation of the metal takes place prior to the removal of the resist 1.
  • Fig. 4 illustrates the structure of Fig. 3 after removing the resist 1 and the passivation. In between the processing steps, it is preferred to evacuate the processing chamber if different chemistry is used.
  • the process parameters of the process steps in an applied material (AMAT) decoupled plasma source (DPS) metal-etch chamber which is typically a high-density plasma (HDP) etch-chamber in which inductive power excitation is used, the ranges of the parameters for the etching steps are the following:
  • step_He_Set- point is the backside pressure of helium, whereas helium is transported between the wafer and the lower electrode or the electrostatic chuck to receive a better heat conduction from the wafer or the workpiece;
  • the RF_Source_Power is the radio frequency power which is inductively excited over a coil in the upper area of the chamber, whereas the plasma is ignited over the RF_Source_J?ower;
  • RF_Bias_Power means the power which is coupled capacitively by use of the lower electrode on which the wafer is supported, to the wafer. This leads to a negative charging of the wafer and to the aligned acceleration of positive charged ions to the wafer, which is necessary for anisotropic etching.
  • mT means milliTorr and Gas_Ar means the amount of Ar which is used and Gas_BCl 3 means the amount of BC1 3 which is used etc. for the other gases.
  • Pressure_Setpoint means the pressure during processing in mTorr.
  • the parameters are the following:
  • Typical parameters for the etching of the anti-reflection layer and/or the TiN-layer and/or the Ti-layer are the following:
  • the parameters for the main metal-etch step to etch the aluminum layer 6 and the Ti-layer 8 are as the following:
  • the parameters are the following:
  • FIG. 5 illustrates an enlarged cross-sectional view of a further embodiment of the present invention in a beginning stage of fabrication of the chip or device. It is shown an already structured or patterned resist 1 which is especially a developed photoresist mask for deep-ultraviolet lithography.
  • the lithography is for example performed with light of 248 nm wavelength.
  • an extra anti-reflection layer has to be used which is in this example an organic anti- reflection layer.
  • the plasma chemistry which is used to open the organic anti-reflection layer in the metal- etch chamber in situ is CF and Cl 2 , especially with N . This etch also removes the anti-reflection layer which is non-organic, namely the Ti-layer 5 and the TiN-layer 4. The etch stops on the layer of AlCu 6.
  • the metal-1 etch is performed in the metal-etch chamber by using a plasma chemistry of BC1 3 , Cl 2 and N .
  • a plasma chemistry of BC1 3 , Cl 2 and N is used to etch the metal-1 etch.
  • the metal-1 etch in which the layers of AlCu 6 and the layer of Ti 8 are etched, polymers build up on the side of the remaining stacks, which are

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Abstract

In a method for patterning layers of semiconductor devices, starting with a substrate with an Al-layer (6) (or Al alloy) and a layer of TiN (4) (or Ti (5)), the layer of TiN (4) is selectively etched with a chemistry comprising CF4 and Cl2.

Description

A METHOD FOR PATTERNING LAYERS OF SEMICONDUCTOR DEVICES
Field of the Invention
The present invention generally relates to the production or fabrication of semiconductor devices and more particularly to a method for patterning layers of semiconductor devices which is performed during the production of semiconductor devices.
Background of the Invention
In the mass production of semiconductor devices like, e.g. memory chips, it is known to use photomasks or masks and etching processes to pattern layers of the chip, e.g. the metal-1-layer of the chip.
To etch metal layers and especially aluminum stacks normally patterns of photoresist or patterns of hard mask are used.
In known methods for patterning layers of semiconductor devices the etching of the metallic layers is performed in a single step using a special chemistry in a plasma etch chamber .
Depending on the laser wavelength which is used to pattern the resist, a Ti-layer and/or a TiN-layer might be used as an anti-reflection layer or an extra organic anti-reflection layer has to be used. E.g. by using an i-line photoresist the wavelength can be 365 run, so that no extra organic anti-reflection layer is needed. By using deep ultraviolet light (DUV) of 248 run, an organic anti-reflection layer is needed. The opening of the organic anti-reflection layer is normally performed in an oxide-etch-tool in which usually oxide etches are performed. This leads to a time-consuming method for the opening of the organic anti-reflection layer and the complete metal etch. The metal etch of all metal layers in one step with the same chemistry further leads to etch results which are sometimes not uniform over the wafer. Thus, much time is needed for the complete metal etch, i.e. the metal etch, the resist strip, the passivation, the polymer removal and the opening of the anti- reflection layer, because a lot of steps are used which are performed in different chambers of the processing line or production line. Moreover, if in the processing line the oxide-edge tool is overloaded, moire oxide-etch chambers have to be used although there still exists a capacity in the metal-etch tool.
Thus, it is an object of the present invention to overcome these deficiencies and to provide a method for patterning layers of semiconductor devices and especially metal layers and also a method for providing a metallic microstructure, which is a part of a method for the production of semiconductor devices, which needs few processing time and which saves etch chambers in the processing line. It is a further object of the present invention to provide a metal etch which leads to uniform etch results.
Brief Description of the Drawings
Fig. 1 to 4 illustrate enlarged, cross-sectional views of the production steps of the patterning of layers of semiconductors and especially of the etching of the metal-1-layer of a 64 Mbit chip in a first embodiment of the invention; and
Fig. 5 to 8 illustrate enlarged, cross-sectional views of the production steps of the patterning of layers of semiconductors and especially of the etching of the metal-1-layer of a 64-Mbit chip in a second embodiment of the invention.
Detailed Description of the Preferred Embodiment
The present invention provides a method for patterning layers of semiconductor devices, starting with providing a workpiece having a substrate, an Al-layer and a layer of TiN and a layer of TiN. The method comprises the further step of etching the layer of TiN, and the layer of TiN selectively to the underlying Allayer or Al alloy with a chemistry comprising CF and Cl . It is intended that the terms "Al-layer" and "layer of Al" also stands for layer of Al alloy; and that the term "layer of TiN" of "TiN layer" also stand for a layer of Ti only.
Compared to the state of the art methods, this method shows a big advantage because the selectivity of the etch step to Ti or TiN with respect to Al or Al alloys leads to a complete etching of the TiN-pattern or a pattern of the Ti/TiN-stack without the loss or without an etching of aluminum or an aluminum alloy. This reveals a good starting point for a uniform aluminum etch.
Preferably, prior to the selective-etching step, a step of etching an organic anti-reflection layer is performed with a chemistry comprising CF and Cl2. This etching step is performed in the etch chamber in which the titanium-nitride or titanium stack etching step and the aluminum etching step is performed. Thus, the semiconductor material or the wafer or the workpiece which is treated does not have to be transported from an oxide-etch chamber of the oxide-etch tool to a metal-etch chamber of the metal-etch tool. Further, other processes in between do not necessarily have to be performed. This leads to a shorter overall processing time and a processing time which does not need so many oxide-etch chambers. Moreover, the utilization of capacity of the processing line and especially the metal-etch tool is improved with this method.
Preferably, the pattern is defined by a resist which is located on top of the workpiece. The etching is preferably performed in a plasma and especially via an reactive ion etch (RIE) .
Preferably, the method further comprises the step of etching the Al-layer or the layer of the Al alloy with a chemistry comprising BC13, Cl2 or N2 or a mixture of said chemistry. This etch step is also preferably performed via RIE. Preferably, the method further comprises the step of removing sidewall polymers being produced during the etching of the Al-layer or the layer of the Al alloy and/or an underlying Ti-layer. Preferably, the walls of the chamber during the above mentioned aluminum etch are heated to prevent the walls from the chamber from being contaminated by polymers . Preferably, the walls are held at a temperature of > 60°C, preferably > 80°C.
Preferably, a removing of the sidewall polymers is performed in situ in the metal-etch chamber by using a plasma of nitrogen (N2) . If all passivation polymers are removed in this step, the following wet cleaning ,can be omitted. This saves work in the process flow and omits problems imposed by wet cleaning, e.g. electro-corrosion. If not all polymers have been removed in the previous step or no plasma etch for the removing of sidewall polymers is performed, the method preferably further comprises the steps of passivating the metal and removing the residual resist mask in a strip chamber of the metal-etch tool. Preferably, a chemistry especially a plasma chemistry of H0, N2 or 02 or a mixture of said chemistry is used.
Preferably, a plasma is used to perform the etching or the removing. Preferably, the etching is performed in a single chamber. Preferably, the single chamber is a metal-etch chamber.
The above mentioned problem is also solved by a method for patterning layers of semiconductor devices starting with providing a workpiece comprising at least an anti- reflection layer, wherein a following step is performed in which only the anti-reflection layer is etched with a chemistry comprising CF4 and Cl2. This also leads to a shorter overall processing time and a processing line which does not need so many oxide-etch chambers. This further leads to a more uniform aluminum etch or aluminum alloy etch.
Preferably, a metal etch is further performed with a chemistry comprising BC13, Cl2 or N2 or a mixture of said chemistry. After at least one anti-reflection layer has been patterned by the above mentioned etching step down to the interface to the Al-layer or Al-alloy layer, e.g. AlCu, a good starting point for a uniform etch of the underlying metals is achieved.
Preferably, the etch steps are performed in a single chamber. Preferably, the anti-reflection layer is at least partly organic. Preferably, the anti-reflection layer further comprises a layer of TiN or a layer of Ti and a layer of TiN. Preferably, the anti-reflection layer is a layer of TiN or a layer of Ti and a layer of TiN, e.g. a stack of Ti- and TiN-layers. The above mentioned problem is further solved by a method for patterning layers of semiconductor devices starting with a workpiece comprising a substrate, a layer of Al or a layer of an Al alloy and a layer of TiN or a layer of Ti and a layer of TiN, the method comprising the steps of
- forming a pattern by a resist being located on top of the workpiece,
- etching an anti-reflection layer and/or the layer of TiN, or the layer of Ti and the layer of TiN with a chemistry comprising CF4 and Cl2, whereas the etching is performed in a metal- etch chamber in a metal-etch tool,
- etching a layer of Al or a layer of an Al alloy and/or a Ti-layer, being located under the Al-layer or the Al-alloy layer with a chemistry comprising BC13, Cl2 or N2 or a mixture of said chemistry in said metal-etch chamber,
- removing sidewall polymers, and
- passivating the metal and removing the resist.
The above mentioned problem is also solved by a method for providing a metallic microstructure, starting with a workpiece comprising a substrate and a stack of layers of which at least a Ti-layer or a TiN-layer is located between the substrate and an Al-layer or a layer of an Al alloy, whereas the method comprises the steps of - patterning the Al-layer or the layer of the Al alloy, and
- etching at least parts of the Ti-layer or the TiN-layer with a chemistry comprising CF4 and Cl .
With this method, it is easily possible to provide metallic microstructures especially for micromechanical purposes . The invention uses the insight that a chemistry of CF4 and Cl2 is selectively etching Ti or TiN and not etching Al or Al alloys.
Preferably, the methods according to the invention are performed in a 300mm - (diameter of wafers) process technology of the production of semiconductor devices. It is, however, not restricted to 300mm - process technology.
In the following, similar reference numerals are used ' which denote similar elements in the drawings: 1 photoresist 1, organic anti-reflection layer (OARC) 2, TiN-layer 4, Ti-layer 5, layer of Al alloy 6, Ti-layer 8, Si02-layer 9, and sidewall polymers 10.
Fig. 1 illustrates an enlarged, cross-sectional view of an embodiment of the present invention in a beginning stage of fabrication of the metal layer. It is shown an already structured resist 1 which is especially a developed photoresist mask. The photoresist 1 is on top of a TiN-layer 4 which is on top of a Ti-layer. In this embodiment, an i-line photoresist 1 is used. For the patterning of this photoresist 1, a wavelength of 365 n is used. For this wavelength, the TiN-layer 4 and the Ti-layer 5 deal as anti-reflection layers. Under the Ti-layer 5, a layer of an Al-alloy 6 is located. The Al- alloy layer is above the layer of Ti which is a so-called Ti-liner 8. The Ti-layer 8 or -liner is located above the Si02-layer 9.
In a first step of the method, a selective breakthrough is performed in a metal-etch chamber by using a plasma chemistry of a CF4 and Cl2. This chemistry only etches the anti-reflection layer which is in this embodiment the TiN-layer 4 and the Ti-layer 5. The etching stops selectively on the aluminium-alloy layer 6. The aluminum alloy is for example Al, Cu which consists for ■ example of 0,5 % copper. The selective etching leads to a good starting point for a uniform aluminum etch in the following. Fig. 2 illustrates the structure of Fig. 1 further along in processing and illustrates the selective etching of the anti-reflection layer.
Fig. 3 illustrates the structure of Fig. 2 further along in processing. The metal-1 etch is performed in the metal-etch chamber by using a plasma chemistry of BC13, Cl2 or N2 or a mixture thereof.
The sidewall polymers 10 which were produced during the metal etch are then removed in situ in the same metal- etch chamber by using a N2-plasma or in another chamber by using a wet chemistry. If the resist 1 is not too thick, it can also be removed in the metal-1-etch in the metal-etch chamber, i.e. during the step, which would directly lead to the structure of Fig. 4.
If the resist 1 is too thick for an effective removal in the previous mentioned step, the wafer or the workpiece is transported into a strip chamber of the metal-etch and there, the resist 1 is removed and the metal layers 4 to 8 are passivated towards corrosion by using a plasma chemistry comprising H20, 0 or N2 or a mixture of this chemistry. It is preferred that the passivation of the metal takes place prior to the removal of the resist 1.
Fig. 4 illustrates the structure of Fig. 3 after removing the resist 1 and the passivation. In between the processing steps, it is preferred to evacuate the processing chamber if different chemistry is used.
In a preferred embodiment of the invention, the process parameters of the process steps in an applied material (AMAT) decoupled plasma source (DPS) metal-etch chamber, which is typically a high-density plasma (HDP) etch-chamber in which inductive power excitation is used, the ranges of the parameters for the etching steps are the following:
- step_He_Setpoint 7000-13000mT
- RF_Source_Power 1500-2500W
- RF_Bias_Power 200-400W
- Pressure_Setpoint 5-2OmT
- Gas_Ar 50-150sccm
- Gas_BCl3 10-15Osccm
- Gas_CF4 10-lOOsccm
- Gas_Cl2 30-150sccm
- Gas_N2 10-lOOsccm
- Cathod_temp 0-60°C
- Wall_temp 10-120°C
Whereas seem are standard cubic cm/min and step_He_Set- point is the backside pressure of helium, whereas helium is transported between the wafer and the lower electrode or the electrostatic chuck to receive a better heat conduction from the wafer or the workpiece; the RF_Source_Power is the radio frequency power which is inductively excited over a coil in the upper area of the chamber, whereas the plasma is ignited over the RF_Source_J?ower; RF_Bias_Power means the power which is coupled capacitively by use of the lower electrode on which the wafer is supported, to the wafer. This leads to a negative charging of the wafer and to the aligned acceleration of positive charged ions to the wafer, which is necessary for anisotropic etching. Further, mT means milliTorr and Gas_Ar means the amount of Ar which is used and Gas_BCl3 means the amount of BC13 which is used etc. for the other gases. Pressure_Setpoint means the pressure during processing in mTorr.
In a preferred embodiment, the parameters are the following:
- Step_He_Setpoint lOOOOmT
- RF_Source_Power 2000W
- Cathod_temp 35°C
- Wall_temp 80°C
Typical parameters for the etching of the anti-reflection layer and/or the TiN-layer and/or the Ti-layer are the following:
- RF_Bias_Power 120W
- Pressure_Setpoint 15mT
- Gas_CF 40seem
- Gas_Cl2 llOsccm
- Gas_N2 50seem
In a preferred embodiment of the invention, the parameters for the main metal-etch step to etch the aluminum layer 6 and the Ti-layer 8 the parameters are as the following:
- RF_Bias_Power 350W
- Pressure_Setpoint 8mT
- Gas_BCl3 70 seem
- Gas_Cl2 lOOsccm - Gas_N 25 seem
For the overetch step which is performed to etch the rest of the metals, which could be still left in the pattern to be etched, the parameters are the following:
RF_Bias_Power 350W
Pressure_Setpoint 8mT
Gas_Ar 70sccm
Gas_BCl3 20sccm
Gas_Cl2 50sccm
In another preferred embodiment of the invention, which is described in greater detail in Fig. 5 to 8, an organic anti-reflection layer is used. Fig. 5 illustrates an enlarged cross-sectional view of a further embodiment of the present invention in a beginning stage of fabrication of the chip or device. It is shown an already structured or patterned resist 1 which is especially a developed photoresist mask for deep-ultraviolet lithography. The lithography is for example performed with light of 248 nm wavelength. For this wavelength, an extra anti-reflection layer has to be used which is in this example an organic anti- reflection layer. The plasma chemistry which is used to open the organic anti-reflection layer in the metal- etch chamber in situ is CF and Cl2, especially with N . This etch also removes the anti-reflection layer which is non-organic, namely the Ti-layer 5 and the TiN-layer 4. The etch stops on the layer of AlCu 6.
In a next step, the metal-1 etch is performed in the metal-etch chamber by using a plasma chemistry of BC13, Cl2 and N . During the metal-1 etch, in which the layers of AlCu 6 and the layer of Ti 8 are etched, polymers build up on the side of the remaining stacks, which are
Figure imgf000013_0001
example. Accordingly, it is intended by the appended claims to cover all such modifications of the invention which fall within the true spirit and scope of the invention.

Claims

Claims
1. A method for patterning layers of semiconductor devices, said method comprising the following steps: providing a workpiece having a substrate, an Allayer and a layer of TiN; and etching the layer of TiN selectively with a chemistry comprising CF4 and Cl2.
2. The method of claim 1, wherein prior to the selective-etching step a step of etching an organic anti- reflection layer is performed with a chemistry comprising CF4 and Cl2.
3. The method of claim 1, wherein the pattern is defined by a resist, which is located on top of the workpiece.
4. The method of claim 1, wherein the method further comprises the step of etching the Al-layer with a chemistry comprising BC13, Cl2 or N or a mixture of said chemistry.
5. The method of claim 4, wherein the method further comprises the step of removing sidewall polymers being produced during the etching of the Al layer.
6. The method of claim 5, wherein a chemistry comprising H20, N2 or 02 or a mixture of said chemistry is used.
7. The method of claim 1, wherein a plasma is used to perform the etching or the removing.
8. The method of claim 1, wherein the etching is performed in a single chamber .
9. The method of claim 8, wherein the single chamber is a metal-etch chamber.
10. A method for patterning layers of semiconductor devices, said method comprising: providing a workpiece having at least a substrate, a metal layer and an anti-reflection layer; and etching with a chemistry comprising CF and Cl2 the anti-reflection layer only.
11. The method of claim 10, characterized in that further a metal etch is performed with a chemistry comprising BC13, Cl or N2 or a mixture of said chemistry.
12. The method of claim 11 characterized in that the etch steps are performed in a single chamber.
13. The method of claim 10, characterized in that the anti-reflection layer is at least partly organic.
14. The method of claim 10, characterized in that the anti-reflection layer is a layer of TiN.
15. The method of claim 14, characterized in that the anti-reflection layer also comprises a layer of Ti .
16. The method of claim 13, characterized in that the anti-reflection layer further comprises a layer of TiN or a layer of Ti and a layer of TiN.
17.' A method for patterning layers of semiconductor devices starting with a workpiece comprising a substrate, a layer of Al and a layer of TiN, the method comprising the steps of
- forming a pattern by a resist being located on top of the workpiece,
- etching an anti-reflection layer and/or the layer of TiN with a chemistry comprising CF4 and Cl , whereas the etching is performed in a metal-etch chamber in a metal-etch tool,
- etching a layer of Al with a chemistry comprising BC13, Cl2 or N or a mixture of said chemistry in said metal-etch chamber,
- removing sidewall polymers, and
- passivating the metal and removing the resist .
18. A method for providing a metallic microstructure starting with a workpiece comprising a substrate and a stack of layers of which at least a Ti-layer or a TiN-layer is located between the substrate and an Al-layer or a layer of an Al alloy, the method comprising the steps of
- patterning the Al-layer or the layer of the Al alloy, and
- etching at least parts of the Ti-layer or the TiN-layer with a chemistry comprising CF and Cl2.
PCT/EP2001/009082 2000-08-14 2001-08-06 A method for patterning layers of semiconductor devices WO2002015231A2 (en)

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US7758763B2 (en) 2006-10-31 2010-07-20 Applied Materials, Inc. Plasma for resist removal and facet control of underlying features

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US5326427A (en) * 1992-09-11 1994-07-05 Lsi Logic Corporation Method of selectively etching titanium-containing materials on a semiconductor wafer using remote plasma generation
US6004884A (en) * 1996-02-15 1999-12-21 Lam Research Corporation Methods and apparatus for etching semiconductor wafers
JP2000124191A (en) * 1998-10-13 2000-04-28 Hitachi Ltd Surface processing method
TW448503B (en) * 1999-03-11 2001-08-01 Toshiba Corp Method for dry etching

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7758763B2 (en) 2006-10-31 2010-07-20 Applied Materials, Inc. Plasma for resist removal and facet control of underlying features

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