WO2000079405A1

WO2000079405A1 - Data processor

Info

Publication number: WO2000079405A1
Application number: PCT/JP1999/003279
Authority: WO
Inventors: Kohichi Suga; Hirotsugu Kojima; Naoki Mitsuishi
Original assignee: Hitachi, Ltd.
Priority date: 1999-06-21
Filing date: 1999-06-21
Publication date: 2000-12-28
Also published as: TW476883B

Abstract

A control resister (41) holds control data according to an instruction given externally. A parallelism control unit (40) determines the parallelism of the parallel operation of data processing sections (20-1 to 20-n) according to the control data held by the control resister (41). Another control resister (32) controls the frequency of the operating clock signal (CLK) for the data processing sections according to the preset control data. Since the parallelism and operating speed of the data processing sections are thus controlled according to external conditions, the processing capacity and power consumption of the data processing sections are also readily controlled according to external state. Changing the parallelism of the data processing sections is suitable for the control prior to a series of processings. It is possible to change the clock frequency even during a series of processings.

Description

Description Data processing equipment Technical field

The present invention relates to a data processing device capable of processing data in parallel, and for example, relates to a technology effective when applied to a SIMD (Single Instruction Stream Multiple Data Stream) type data processing device for performing error correction. Background art

Hard disks, CD-ROMs (Compact Disc-Read Only Memory), DVDs (Digital Video Discs),

—Code words that can correct recording z read errors that occur on the medium are used in evening recording devices. A codeword is defined, for example, by a special set of numbers called the Galois field and special operations defined with it. Code error correction is performed by data processing using the number of Galois fields and arithmetic. A set of numbers in a Galois field can be defined in multiple types by a primitive polynomial called a primitive polynomial, which defines the set of numbers. At the same time, the operation differs depending on the primitive polynomial. The most frequently used codeword is the Reed Solomon code, which is particularly used for error correction codes in data storage systems and communication systems in which errors tend to concentrate on the part.

The error correction process consists of the steps of calculating a syndrome from an input codeword, calculating an error locator polynomial and an error numerical polynomial from the syndrome, finding an error location from the error locator polynomial, and locating the error locator polynomial and error. Steps for finding error values from numerical polynomials and correcting errors Including the step of:

Since codewords are continuously received and processed from a storage or recording medium or a transmission line of a communication system, the time allowed for processing of data including such error correction is limited by the data. It is determined from the reading speed and receiving speed. Therefore, a circuit for performing error correction requires some data processing capability. From such a viewpoint, error correction can be performed using a SIMD type processor or the like.

By the way, in recent years, it is well known that low power consumption is desired not only for notebook personal computers (also referred to as personal computers) but also for desktop personal computers using an AC power supply. There is no guarantee that low power consumption will not be required in the future for circuits that perform error correction in the SIMD format.

Due to the nature of arithmetic processing, the present inventor may not be able to fully utilize all of the data processing power possessed by certain aspects of data processing, even though the processing capacity must be improved by parallel arithmetic processing. I realized that there may be cases where it is acceptable. For example, the above error correction processing capability must be able to cope with frequent errors, and conversely, if the number of errors is small, the above error correction step can be hardly performed.

As a technique for reducing power consumption from this viewpoint, there is a technique described in Japanese Patent Application Laid-Open No. Hei 9-185585. This involves assigning tasks in a data processing device that has a multiple instruction stream, multiple data stream (MIMD) parallel processor and a power supply controller, while maintaining the required processing capacity, It is described that the power supply is stopped to realize power saving. However, the power supply control assumed by this involves 0 S (Operating System), which makes the control extremely complicated. Japanese Patent Publication No. 9 _ 7 3 7 09 states that the data block in which no error symbol is detected in the error correction circuit is processed so that subsequent calculation processing is not performed. It is described that a control signal and a clock for are not supplied. In this control, the clock supply is partially stopped by the judgment of the error correction circuit itself, and the circuit part that processes error-free data does not require substantial operation at that time. Therefore, if the supply of clock signals etc. is inevitably stopped, the power consumption will be reduced accordingly. This technique does not variably control the correction processing capability of the error correction circuit. It merely controls the supply of clock signals dynamically according to the processing content. Even if no error symbol is detected, the error correction processing capacity does not change. Japanese Patent Application Laid-Open No. Hei 9-147478 also similarly describes suppressing unnecessary operations in processing and reducing power consumption. The ability itself is kept constant. Neither control on arithmetic processing capacity nor control on power consumption is considered.

Further, International Publication WO99 / 14685 describes an example in which a SIMD type processor is used for error correction. The technology described in this document is based on the SIMD type processor that provides control information for arithmetic operation from a control unit to a plurality of data processing units and operates them in parallel. There is provided standby control means for setting the processing unit to a standby state, and the control unit performs control for returning each data processing unit from the standby state to the active state. In the standby state, the clock supply to the arithmetic circuit of the data processing unit is stopped. Therefore, a data processing unit that processes error-free data can be in a standby state when another data processing unit is performing the error correction step. On the other hand, if all the data processing units can be placed in the standby state, the control unit cancels the standby state. Then, the next step can be executed by each data processing unit first, and it is easy to minimize unnecessary cycles due to the standby state of the data processing unit, and the parallel processing performance by SIMD format is improved. Can be improved.

From the viewpoint of low power consumption, this technique does not variably control the correction processing capability of the error correction circuit, but controls the supply of the clock signal dynamically according to the processing content, as in the above-described conventional technique. It is just doing. Even if no error is detected, the processing capacity for error correction does not change.

An object of the present invention is to provide a data processing device capable of controlling the data processing capability and power consumption of parallel data processing units according to external conditions.

Another object of the present invention is to provide a data processing device capable of easily controlling the data processing capability and power consumption of parallel data processing units.

The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings. Disclosure of the invention

[1] A first aspect of the data processing apparatus according to the present invention is to provide a control register having a control data according to an external instruction, and a plurality of data registers according to the control data held by the control register. The parallelism of the parallel operation by the processing unit is determined by the parallelism control unit. By controlling the degree of parallelism of the data processing unit in accordance with external conditions in this way, the processing capability and power consumption of the data processing device can be easily controlled according to external conditions.

The control of the degree of parallelism can be realized by controlling the supply / stop of the clock signal to the data processing unit. That is, the plurality of data processing units Operating in synchronization with a clock signal output from a clock generation circuit, wherein the parallelism control unit has a selection gate for separately supplying the clock signal to the data processing unit; It is determined whether or not to output a clock signal based on.

[2] A second aspect of the data processing apparatus according to the present invention is that control data is transmitted to a data processing apparatus having a plurality of data processing units operable in synchronization with a clock signal in accordance with an external instruction. A control register is provided, and a speed control unit that determines a frequency of the clock signal according to control data held by the control register is provided. For example, the speed control unit determines the frequency of the clock signal at the frequency division ratio specified by the control data. In this way, by controlling the operation speed of the data processing unit in accordance with external conditions, the processing capacity and power consumption of the data processing unit can be easily controlled according to external conditions.

[3] A third aspect of the data processing device according to the present invention enables external control of both the parallelism and the operation speed of the data processing unit. That is, a plurality of data processing units capable of operating in parallel in synchronization with the clock signal, a first control register holding the first control data according to an external instruction, and a second control register storing the first control data according to an external instruction. A second control register storing control data; and a parallelism control for determining a parallelism of the parallel operation by the plurality of data processing units according to the first control data stored in the first control registry. And a speed control unit that determines the frequency of the click signal in accordance with the second control data held by the second control register. The change in the degree of parallelism of the data processing unit is suitable for controlling before a series of processing. If the degree of parallelism is changed in the middle of the parallel operation processing, it is easy to cause a situation in which the data to be initially processed is not processed. On the other hand, the clock frequency can be changed even during a series of processes because it is not necessary to change the program. Therefore, the data By controlling both the degree of parallelism and the operation speed of the processing unit in accordance with external conditions, it becomes possible to more finely control the processing capacity and power consumption of the data processing device from the outside.

[4] The following more specific configurations can be adopted in the data processing device from the above viewpoints.

In the case of specializing in processing a large number of data blocks that are expected to go through the same data processing step, a SIMD form may be adopted for the data processing device. That is, the apparatus further includes an instruction control unit that decodes an instruction and outputs control information, and the instruction control unit is configured to be able to supply control information for an arithmetic operation to the plurality of data processing units in parallel. . If different processes are to be parallelized, the MIMD format may be used for the data processing unit.

When the SIME format is adopted, the data processing device is provided with a program memory storing an error correction program for performing error correction, the control unit fetches an instruction from the program memory, and uses the data processing unit to execute an error. It can be configured to perform correction processing. For example, the data processing unit includes a Galois field arithmetic circuit capable of performing Galois field multiplication and addition, and the control unit controls the Galois field arithmetic circuit to cause the data processing unit to perform error correction processing. .

Further, in the SIMD-type data processing device, the control unit controls transfer of unprocessed data stored in a data memory to the data processing unit, and processes the processed data processed by the data processing unit. A monitoring circuit may be employed for monitoring the status of the arithmetic processing by the data processing unit when the transfer of the data to the data memory can be controlled. The monitoring circuit outputs a signal for notifying a state in which the amount of unprocessed data remaining in the data memory exceeds a certain amount to the outside based on an access address to the data memory. The external status notification function enables external setting The validity of the processing capability, such as the degree of parallelism, can be easily determined from outside the SIMD type data processing device. In other words, it is possible to control the degree of parallelism and the operation speed of the data processing unit in consideration of the external state of the data processing device as well as the internal state of the data processing device.

[5] A data processing device based on each of the above aspects can be further integrated into a semiconductor integrated circuit by adding the following configuration.

For example, an input circuit for inputting data from the outside, data stored from the input circuit are stored, and the stored data is provided to the data processing unit, and the data calculated by the data processing unit is again processed. Further adding a data memory for storing the data and an output circuit for outputting the data stored in the data memory to the outside;

For example, the input circuit may include demodulation means for demodulating an input signal and data transfer control means for transferring demodulated data to the data memory.

Further, a system interface means may be added. The system interface means can be used to set transfer control conditions in the data transfer control means and to set control data in the control register. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an example of a data processing apparatus according to the present invention.

FIG. 2 is a block diagram showing an example of a clock frequency dividing circuit.

FIG. 3 is an explanatory diagram schematically showing the processing capability according to the setting state of the parallelism and the operation speed.

FIG. 4 is an explanatory diagram of the operation of the memory pointer in the monitoring circuit.

FIG. 5 is a flowchart showing a typical processing procedure of the error correction processing of the RS code. It is a chart.

FIG. 6 is a timing chart showing a first operation example of autonomous standby control of a data processing unit in error correction processing.

FIG. 7 is a timing chart showing a second operation example of the autonomous standby control of the data processing unit in the error correction processing.

FIG. 8 is a timing chart showing an operation example when the degree of parallelism of the data processing unit in the error correction processing is changed.

FIG. 9 is a block diagram showing a detailed example of a data processing unit suitable for error correction processing.

FIG. 10 is a block diagram of a DVD drive system having a DVD controller, which is a more detailed example of a data processing device.

Fig. 11 is a block diagram showing the entire DVD drive system.

FIG. 12 is a system operation flow chart of the DV drive system of FIG.

FIG. 13 is a block diagram showing an example of a MIMD type data processing device.

FIG. 14 is a block diagram illustrating still another data processing device. BEST MODE FOR CARRYING OUT THE INVENTION

《Overview of data processing device》

FIG. 1 shows an example of a data processing device according to the present invention. Although not particularly limited, the data processing device 1A shown in the figure is a semiconductor integrated circuit positioned as a peripheral controller, and is formed on one semiconductor chip such as single crystal silicon. Although the data processing device 1A is not particularly limited, the error correction circuit 2, the system interface circuit 3, Includes memory interface circuit 4, input circuit 5, and output circuit 6. These circuits share the local data path LDB, local address bus LAB and local control bus LCB.

The system interface circuit 3 is connected to a system controller such as a microcomputer (not shown), and the memory interface circuit 4 is connected to a data memory 7 used as a data buffer or the like. The input circuit 5 demodulates the received data or the data read from the disk, for example, and stores the data in the data memory 7. The error correction circuit 2 reads the data stored in the memory 7 for error checking, performs error correction on the erroneous data, and writes the corrected data back to the data memory. The output circuit 6 reads the data after error check and error correction from the data memory 7, performs necessary processing, and outputs the processed data to the outside. A terminal (not shown) is provided between the outside and the semiconductor integrated circuit, and the data processing device 1A transmits and receives data (signal) to and from the outside via the external terminal.

Although not particularly limited, the error correction circuit 2 performs the decoding process in the SIMD form. That is, a plurality of data processing units 20-1 through 20-n having the same circuit configuration as each other, and an instruction control unit 2 common to the data processing units 20-1 to 20-n. With one. Each data processing unit 20— :! 20 to n have an arithmetic circuit 22, a buffer memory 23, and a standby control circuit 26. The instruction control unit 21 controls the data transfer between the data memory Ί and each buffer memory 23 according to the operation program stored in the program memory 24, and controls each data processing unit 20-1 to Performs arithmetic control of 2 0—n. For example, when the input circuit 5 stores a predetermined amount of data in the data memory 7, it requests the instruction control unit 21 to perform an error correction process. Upon receiving this, the instruction control unit 21 decodes the instruction fetched from the program memory 24, and The operation of load processing, calculation processing, and store processing is repeated for data storage. In the data loading process, data is transferred from the data memory 7 to the buffer memory 23 in accordance with the transfer control conditions initially set by the system controller in advance. In the arithmetic processing, an error check is performed on the data in the buffer memory 23 using the arithmetic circuit 22, and an error correction arithmetic processing is performed on the erroneous data. In the data store process, a process of writing back the error-corrected data from the buffer memory 23 to the data memory 7 is performed. The arithmetic processing can be executed in parallel based on an arithmetic control signal 25 commonly provided from the instruction control unit 21 to each of the data processing units 20-1 to 20-n. The arithmetic processing capability is improved by this parallel arithmetic processing.

《Variable operation speed control of data processing unit》

The variable control of the operation speed in the error correction circuit 2 will be described.

'S o

The error correction circuit 2 is operated in synchronization with the clock signal CLK. The frequency of the clock signal CLK is determined by the frequency division ratio selected by the clock frequency divider (speed controller) 30. That is, the clock divider circuit 30 divides the frequency of the basic clock signal ø generated by the clock pulse generator (CPG) 31 and changes the frequency of the clock signal CLK to the operating speed register (second control register) 3. Control according to the value of 2. In the operating speed register 32, a speed control data (second control data) is externally set via the system interface circuit 3 and an external terminal (not shown). For example, as shown in FIG. 2, the frequency divider 30 A divides the basic clock signal ø to generate frequency-divided signals 0 2, φc, and divides one of these signals into an operating speed register. In the evening, the selector 30B selects the frequency-divided signal according to the set value of 32 and outputs the selected frequency-divided signal as the clock signal CLK. The clock signal CLK is And gate 4 3— :! Are supplied to the respective data processing units 20-1 to 20-n via .about.43-n.

<< Standby control for each data processing unit >>

The standby control circuit 26 individually separates the data processing units 210-1 to 20-n according to the operation result of the operation unit 22 according to the control signal 25 supplied from the instruction control unit 21. It is determined whether or not to control in a standby state, and when the state is set to the standby state, the corresponding standby control signal 27-i (i = l ~! 1) is set to the logical value "0". The standby control signal 27-i is input to the AND gate 42-i, and the output of the AND gate 42-i is input to the AND gate 43-i to determine the output of the clock signal CLK. Signal. Therefore, when the standby control signal 27-i is set to the logical value "0", the supply of the clock signal CLK to the data processing unit 20-i corresponding to the standby control signal 27-i is stopped. The operation is stopped, the operation of the data processing unit 20-i is stopped, and the data processing unit 20-i is put into a standby state. The release of the standby state for the data processing unit 20-i in the standby state is performed by the instruction control unit 21 resetting the standby control circuit 26 with the control signal 25. When the standby control circuit 26 is reset, the standby control signal 27-i is set to the logical value "1", and the supply of the clock signal CLK to the data processing unit 20-i is restarted.

For example, as a result of the data processing unit 200-i starting the error correction process and checking for the presence or absence of an error, the data processing unit 200-1i that processes the error-free data sequence has a standby control circuit 2 6 can determine the state and transition to the standby state by itself. Thereby, useless power consumption can be reduced. Further, when all the data processing units 20-1 to 20_n enter the standby state at once, the instruction control unit 21 detects this state, so that the instruction control unit 21 Data processing unit 20 0-1 to 20 0-n cancels the standby state, eliminates unnecessary standby cycles, and improves arithmetic processing efficiency. Can be

<< Parallelism control of data processing unit >>

The set value of the parallel degree register is supplied to the AND gates 4 2-1 to 4 2-n, whereby the AND gates 4 2-1 to 4 2-n and the AND gates 4 3-1 to 4-4 are supplied. 3—n constitutes a parallelism control unit 40 of the data processing units 20—1 to 20—n. In the parallel degree register 41, parallel degree control data (first control data) is set from the outside through the system interface circuit 3 and an external terminal (not shown). The parallel degree control data has a plurality of bits corresponding one-to-one to the data processing units 20-1 to 20-n, and each bit is a 2-input AND gate 42- :! ~ 4 2—This is one input of n. This parallelism control data indicates an operation with a logical value "1". Therefore, the data processing section 20-i is enabled to operate on the condition that the corresponding bit of the parallelism control data is a logical value "1". From the above, the clock signal CLK is supplied to the data processing unit in which the corresponding bit of the control data set in the parallelism register 41 is set to the logical value "1", and the supplied clock signal CLK is supplied. The CLK frequency is determined according to the control data set in the operating speed register 32. As a result, the degree of parallelism of the parallel operation in the data processing unit 20-1-20-n and the frequency of the clock signal CLK can be externally determined.

The change in the degree of parallelism must take into account the operation processing timing in the error correction circuit 2. The change in the degree of parallelism of the data processing units 20-1 to 20-n is suitable for control in advance prior to a series of processes. If the degree of parallelism is changed in the middle of the parallel processing, it is often easy for data to be initially processed to be lost. For example, after storing the operation data in the buffer memories 23 of all the data processing units 20-1 to 20-n, the error correction step is executed after determining whether there is an error. If the degree of parallelism is changed during the execution, there is a possibility that some data to be subjected to the error correction step may be excluded from the calculation. The system controller should not change the degree of parallelism on the way according to the progress of the parallel processing. In this case, even if the degree of parallelism is changed, there is no need to change the operation control program of the data processing units 20-1 to 20-n.

On the other hand, the clock frequency can be changed even during a series of processing independently of the change in the degree of parallelism.

By controlling both the degree of parallelism and the operation speed of the data processing unit in accordance with external conditions, as shown in FIG. 3, the data processing unit 1A can reduce the data processing capacity and power consumption to the degree of parallelism and operation. Based on the two aspects of speed, it becomes possible to control the outside more finely.

《Monitoring of processing capacity》

In FIG. 1, reference numeral 50 denotes a monitoring circuit. Based on the access address to the data memory 7, the monitoring circuit 50 provides a signal (external standby signal) for notifying the outside that the unprocessed data amount remaining in the data memory # exceeds a certain amount. ) 5 5 is output. According to Figure 1, the monitoring circuit 5 0, the input data Boyne evening (Boyne evening value P i) 5 1, processing the data Boyne evening (Boyne evening value p _e) 5 2, output data Poin evening (pointer value P o) 53, and a comparée 54. The input bus 51 stores the memory addresses when the input circuit 5 sequentially stores the data in the data memory 7 via the local address path LAB. The in-process data pointer 52 sequentially stores the memory address when the instruction control unit 21 sequentially stores data from the temporary memory to the buffer memory 23 by the load processing via the single-address-address bus LAB. Go. The output data pointer 53 is a local address for the memory address when the output circuit 5 sequentially outputs data from the data memory 7. It is stored sequentially via Subas LAB. The access of the data memory 7 in the above is performed sequentially for successive memory addresses. Following access to the last address of data memory 7, access is made back to the first address. In other words, the memory 7 is used as a ring buffer. The comparator 54 detects a state in which the output data bottle evening value Po has caught up to just before the input data bottle evening value Pi. In other words, it is detected whether P i = P o + h. Is a predetermined constant. When P i = P o + h is detected, the external standby signal 55 is asserted to the logical value “1”. In this state, if the amount of unprocessed data remaining in the data memory 有限 with finite storage capacity exceeds a certain amount, and if the data is further input, the newly input unprocessed data will be lost due to the nature of the ring buffer. In this state, the processed data is overwritten. In other words, it means that the data processing capacity of the data processing units 20-1 to 20-n is too low.

FIG. 4 shows the state of the boyne evening separately. When the data memory 7 is used as a ring buffer, the data processing unit 20— :! If the data processing capability at ~ 20-n is appropriate, as shown in (1), (2), and (3) in Fig. 4, while maintaining P 0 <P i, P o, P e, and P i change. However, if the data processing capacity is insufficient, P o = P i as shown in (4), and P o exceeds P o and P o> P i as shown in (5). This means that the data to be read after processing is destroyed by the read data.

The external standby signal 55 is asserted to the S value "1" immediately before the state of (5) in FIG. 4 is reached. The external standby signal 55 is given to the system controller. When detecting the assert state of the external standby signal 55, the system controller changes the value of the parallelism register 41 at a predetermined timing. To increase the parallelism of the data processing unit and improve the processing capability of the error correction circuit 2. Further, immediately change the value of the operating speed register 32 to increase the operating speed of the error correction circuit 2. Alternatively, an external circuit (not shown) that performs an input operation to the input circuit 5 is set in a standby state. As a result, errors in the entire system can be avoided.

Such an external status notification function makes it possible to easily determine the validity of the processing capability such as the degree of parallelism set from the outside from the outside of the SIMD type data processing device 1A. In other words, the degree of parallelism and operation speed of the data processing units 20-1 to 20-n can be controlled in consideration of the external state of the data processing device 1A as well as the internal state of the data processing device 1A. become.

In the configuration shown in FIG. 1, the pointers 51, 52, and 53 can be directly read from the outside via the system interface circuit 3. Therefore, the system controller directly refers to the values of the pointers 51, 52, and 53 using the empty cycles of the local paths LDB, LAB, and LCB, and accordingly, the data processing unit. It is possible to control the increase / decrease of the degree of parallelism of 20-0-1 to 20-0-n and the level of the clock frequency. For example, if there are many processed data that have not been output, the parallelism can be reduced to reduce power consumption. In this way, if the pointers 51, 52, and 53 can be referred to from outside, the processing capacity can be determined from a desired viewpoint separately from the external standby signal 55, and the degree of parallelism and clock frequency can be determined accordingly. Control becomes possible.

In actual error correction, the number of generated errors is almost always smaller than the maximum error assumed in the error correction code, so that the error correction processing capability does not need to be always maximum. In the data processing device 1A shown in FIG. 1, the processing capacity of the error correction circuit 2 is usually reduced, and the unprocessed data is processed according to the contents of the pointers 51, 52, 53 or the value of the external standby signal 55. Night At that point, the processing capacity should be increased. In addition, when the number of processed data increases, the processing capacity can be reduced. As a result, the average power consumption can be reduced according to the contents of the night, in other words, the required processing capacity.

《Example of error correction processing》

An example of the error correction processing of the RS code in the error correction circuit 2 will be described. The instruction control unit supports a RISC instruction (ReducedInsntRuction on SetCommuter). Each of the data processing units 20-1 to 20-n in the S I MD type error correction circuit 2 includes a Galois field multiplier and an adder in the arithmetic circuit 22.

At the time of error correction, first, a syndrome operation to check for errors is performed, and only when there is an error, a series of error corrections such as Euclidean algorithm, chain search, and numerical error calculation are performed. Here, assuming that the time to check for an error is T 1 and the time to perform error correction is T 2, the processing time without error is Tn = T 1 and the processing time with error is T y = Tl + T2. Therefore, when there is no error, the processing capability may be reduced by reducing the degree of parallelism or reducing the operation speed so that Tn = Ty. Since the power consumption can be reduced by lowering the processing capacity, the smaller the error, the lower the power consumption.

FIG. 5 illustrates a typical processing flow of the error correction of the RS code. In the figure, the description enclosed in an oval indicates the processing content, and the description enclosed in a rectangle indicates the output data. The error correction processing flow consists of data transfer 1001, syndrome calculation 1002, presence / absence judgment 1003, Euclidean algorithm 1004, Chien search 1005, error numerical calculation 1006, and correction 1007.

Data transfer 1001 is suitable for SIMD type parallel processing. In this format, in other words, the data is arranged from the memory 7 to the buffer memory 23 in accordance with the specified degree of parallelism. The syndrome calculation 1002 receives a series of received codes (r0 to r255) 2001 as input, and calculates a syndrome polynomial coefficient 2002. Here, it can be seen that if the coefficient 200 2 of the syndrome polynomial is all zero, there is no error in the received code. If it is found that there is no error, omit the following processing and terminate. If it is found that there is an error, start the correction processing. First, an error locator polynomial 2003 and an error numerical polynomial 2004 are calculated from the syndrome polynomial 2002 by the algorithm of algorithmic algorithm 104. The root of the error locator polynomial 2003 is found by Chien search 1005, so that the error location 205 is found. At this time, if the error position 20005 is obtained with a value that cannot actually exist, it can be understood that an error that exceeds the code correction capability has occurred. In this case, it outputs that it cannot be corrected, and skips the following processing and ends. If the position of the error is found appropriately, the numerical value of the error 206 is calculated based on the error, the correction 1007 is performed, and the process is terminated.

For example, in an error correction process for data read from a recording medium, it is efficient to process data of a plurality of sectors as a processing unit as a group of code sequences. Therefore, it is also advisable to correct the error of the received code for each data processing unit provided with the Galois field arithmetic unit, for each group of code sequences. For example, n data processing units 20— :! In the case of using all of ~ 20-n, n received code sequences can be processed simultaneously and in parallel. By changing the number of data processing units, the processing performance can be changed without changing the basic processing flow.

FIG. 6 shows a first operation example of the autonomous standby control of the data processing unit in the error correction processing. Fig. 6 shows four data processing units 20_1 and 2 A processing flow when four received code sequences 2001 are processed simultaneously and in parallel using 0-2, 20-3, and 20-4 is shown schematically. In FIG. 6, GP E 0 (20-1) to GP E 3 (20-4) indicate four parallel data processing units, and each of the data processing units in the vertical direction elapses with time. Evening The processing executed by the processing units 20-1 to 20-4 is shown.

In FIG. 6, if an error is detected in at least one of the four received code sequences 200 1, the data processing unit in which no error is detected is set to the standby state 10099, and the processing up to the correction is performed. 4 shows a flow to be executed. The received code sequence 200 1 input to the data processing unit GP E 0 (20-1) contains an error within the range that can be corrected, and is input to the data processing unit GP E 1 (20-2). An error beyond the correctable range occurs in the received received code sequence 2001, and the received code sequence 2001 input to the data processing units GPE 2 (20-3) and GPE 3 (20-4) Is the processing flow when no error occurs. Until data transfer 1001, syndrome calculation 1002, error existence judgment 1003, all data processing units 20-0-1, 20-2, 20-3, and 20-4 execute processing unconditionally. You. In this example, the data processing unit GP E 0 (20-1) and the data processing unit GP E 1 (20-2), which are found to have errors, perform subsequent error correction processing, while data processing The GPE 2 (20-3) and the data processing unit GPE3 (20-4) detect no error, so the data processing unit GPE2 (20-3) and the data processing unit GPE2 (20-3) —Evening processing section GPE 3 (20-4) enters the standby state 1 0 99 during that time. As a result of the Euclidean algorithm 1004 and the numerical error calculation process 1006, it was found that an error exceeding the code correction capability occurred. The GPE 1 (20-2) During numerical calculation 1006 and correction 1007, it enters the standby state 10999 and waits for the processing of the data processing unit GPE0 (20-1) to end. In this case, if no error is detected in all the data processing units 20-1, 20, 2, 20, 3 and 20-4, no error correction processing is performed and the next series of received codewords is executed. Since processing can be shifted to 2001, unnecessary processing steps can be avoided. However, if at least one of the four received code sequences 2001, which are simultaneously processed by the four data processing units 20-1, 20-2, 20-3, 20-14, has an error, However, the three data processing units other than the one data processing unit that actually performs error correction put all processing after the Euclidean algorithm 1004 into a standby state 10099, and complete the error correction processing. Will wait. In this case, it cannot be said that the data processing units 20-1, 20-2, 20-3, and 20-4 provided in parallel are being used effectively. As the number of data processing units increases, the probability that no error is detected in all data processing units decreases, and processing efficiency decreases.

To avoid this, the method illustrated in the processing flow of FIG. 7 is effective. In this case, too, first, the processing 1001 for reading the four received code sequences 200 1 into the four data processing units 20-1 to 20-4 is performed, and the syndrome calculation 1002 and the determination of the presence or absence of an error 1 003 are performed. Up to this point, the processing flow is the same as that shown in FIG. The data processing unit GP E 0 (20-1) and the data processing unit GP E 1 (20-2), which have been found to have errors, store the calculated syndrome 2002 in the data memory 7. The data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4), which are found to be error-free, enter the standby state 10999 and process them. Wait for the end. The processing flow returns to the first data transfer, and performs the processing 1001 for reading the next four reception code sequences 2001 into the four data processing units 20-1 to 20-4. A syndrome calculation 1 002 and an error determination 1 003 are performed, and similarly, a process 1008 for storing only the syndrome 2 002 of the received code sequence 200 1 in which an error is detected in the memory 2 is performed. After this is performed on a certain number of received code sequences 2001, a process of reading the stored syndrome 20002 only for the erroneously detected received code sequence 2001 is performed. 1 0 9 is performed to perform the subsequent error correction processing. In this case as well, if the number of errors exceeds the correction capability of the code, it is impossible to correct the error. In the example shown in FIG. 7, the process of temporarily storing the syndrome 200 2 of the received code sequence 20 ◦ 1 in which an error is detected in the memory 7 is performed, and the process of reading out again is performed. 9 is required more than the example shown in Fig. 6. In general, the processing flow shown in FIG. 6 is efficient when the frequency of occurrence of errors is high, and the processing flow shown in FIG. 7 is efficient when the frequency of occurrence of errors is low. From the relationship between the frequency of occurrence of errors, the number of processing steps required for error correction, and the number of processing steps required to temporarily store the syndrome in memory, it is possible to quantitatively determine which processing flow is more efficient.

In particular, in the case of practical error correction, the average value of the frequency of occurrence of errors is extremely lower than the frequency of occurrence of the most supposed errors. If the received code is 256 bytes and eight or less errors are corrected, 16 syndromes are required. Since the probability of an error occurring is typically 1 in 1000, an average of about four codewords will have one word error. In the case of correcting 100 received codewords = 25,600 bytes, assuming that the correction process is completed in 100,000 steps, the process flow shown in Fig. 6 is assumed. According to this, there are 1 0, 0 0 0 x 1 0 0 + 4 = 2 50, 0 0 0 steps. On the other hand, when error correction is performed according to the processing flow in FIG. 7, the total is 90,640 steps. Processing will be completed in less than half of the processing flow shown in FIG. If the error rate is lower, increase the number of data processing units and increase the parallelism. When the number of processing steps is increased, the effect of reducing the processing steps when the processing method shown in FIG. 7 is adopted becomes more remarkable.

Syndrome calculations must be performed for all input sequences, and always require a fixed amount of data processing. On the other hand, subsequent error correction requires less processing as long as there are few errors. For this reason, the flow in FIG. 7 can be further changed to FIG. 8, and the degree of parallelism can be increased for syndrome calculation and the degree of parallelism can be reduced for error processing.

These processing flows may be determined in consideration of the actual error frequency, data input speed, syndrome calculation speed, and the like.

<< Example of data processing unit >>

FIG. 9 shows a detailed example of a data processing unit suitable for error correction processing. The data processing unit 20-i shown in the figure is composed of two Galois field multipliers 110, one Galois field adder 112, a 64-bit Galois buffer 150, and a 4-word Galois register 160, 3. Data registers (PS1, PS2, PD) 12 1, 122, 123, 8-word integer register 170, one integer adder / subtractor 180, and other data processing unit It consists of a circuit that puts it in a standby state.

Galois Buffer 150 and Galois Regis 160, and two Galois Field Multipliers 1 1 and 1 Galois Field Adder 1 12 are connected by six internal buses, and Galois Puffer 150 and Galois Regis 160 Calculates the data stored in the memory and stores the result in the Galois buffer 150 and the Galois storage 160. A selector 114 is provided at the input of each of the arithmetic units 111, 112 so that an internal path from which data used for the operation is output can be selected. The outputs of the arithmetic units 11 1 and 1 12 are stored in the Galois buffer 150 or Galois register 160 via the internal path.

Galois buffer 150 has pointers (PS 1) 12 1 and (PS 2) 1 Outputs 2 words of the address specified in 22 to the internal path at the same time, and simultaneously loads data from the internal path to the address specified in Boyne (PD) 123. The values of pointers 121, 122, and 123 can be increased or decreased (+ 1 / -1) in the same cycle as Galois field arithmetic. The value of the boyfriend is written and read from the integer register 170. The integer register 170 stores data necessary for calculating values required for controlling the pointers 121, 122, and 123, and the calculation is performed using the connected integer adder / subtractor 180.

In a process in which the Galois field operation is repeated while increasing and decreasing the values of the pointers 121, 122, and 123, it may be desired to end the repetition when the values of the pointers 121, 122, and 123 reach a predetermined value. A predetermined value is stored in the register evening (P END) 131 in advance, a boyne evening to be monitored is designated by the control signal SELPEND, and the monitored evening evening value is stored in the register evening (PEND) 131. The comparator (CMP) 133 determines whether or not the value matches a preset value. When the determination results match, the RPTEND flag of the flag register 140 is set by the signal RPTEND, and the standby register 141 is set. When not monitoring the pointers 121, 122, and 123, set the control signal SELPEND so that the values of the pointers 121, 122, and 123 are not compared with the value of the register (PEND) 131. I do.

In addition to the RP TEND flag described above, a GZ flag indicating that the result of the Galois field adder 121 has become zero, an integer arithmetic unit An I ZERO flag is provided to indicate that the result of 180 is zero, and an I NEG flag is provided to indicate that the result is negative.

The contents of the flag register 140 are compared with the signal CN by the masked comparator 141. Using DXMASK as a mask, the signal is compared with the signal NOPCNDX. If they match, the wait register 144 is set. The standby register 142 is, for example, a 1-bit register, which can be set by the above two methods according to the operation result in the data processing unit 201-i, or can be set directly by an external signal PE NOP IN. Can be written and reset, or read directly to the outside as signal PEN 0 PEA. When the value of the standby register 142 is set, the control signal input to the data processing unit 20—i is not a circuit that controls access to the standby register 142 from the circuit 144. Are all controlled to be invalid. From the viewpoint of power consumption reduction, it is desirable to perform control to stop the clock when in the standby state. Further, if a gate that invalidates the control signal is inserted into all the control signals, the number of control signals is not rarely several hundred, so the increase in circuit scale due to the inserted gate cannot be ignored. When the clock is stopped, the gate needs to be inserted only for the clock, which is preferable from the viewpoint of the circuit scale.

《DVD drive system》

FIG. 10 is a block diagram of a DVD drive system having a DVD controller, which is a more detailed example of the data processing apparatus. The DVD controller 1B shown in the figure has a binarization circuit (Data-Strobe) 200 for binarizing analog data, a demodulation circuit (DVD-Demod) 201, and a modulation circuit (DVD). — Mod) 202, error correction circuit (DVD—ECC) 203, memory interface circuit (DRAM-CONT) 204, audio interface circuit (Audio Processor) 205, personal ATAP I interface circuit 206, interfaced with a host computer such as a computer, system interface circuit (MI CON IF) 206, Servo It is composed of modules such as a circuit (SERVO) 208 and a clock oscillator (CPG) 209, and is formed on one semiconductor substrate by a known semiconductor manufacturing technique. In addition, the DVD controller 1B can play a CD-ROM and a music CD-DA together with a DVD. Demodulation circuit for CD (CD-DA) 210, descrambler for reading information from CD-ROM 215, and ROM decoder (ROMDEC) 21 for decoding data in CD-ROM format Have one.

The CPG 209 generates a reference clock by performing frequency division based on a crystal oscillator or an external clock connected through an external terminal indicated by a symbol に, and outputs the reference clock to each functional block. Supply. The DVD controller 1B operates in synchronization with this reference clock.

The error correction circuit 203 has the same configuration as the error correction circuit 2 having a variable processing capability. The memory interface circuit (DRAM-CONT) 204 performs arbitration of input / output requests for the data memory 211 such as a DRAM and performs path control of the memory bus 218. . The memory interface circuit 204 and the data memory 212 correspond to the memory interface circuit 4 and the data memory 7 in FIG.

The A TAP I interface circuit 206 is an example of the output circuit 6 in FIG. The system interface circuit 207 is connected to a microcomputer 220 as a system controller. The micro computer 220 initializes each circuit such as the demodulation circuit 201 and the error correction circuit 203 via the internal bus (LAB, LDB, LCB) 221 and the error correction circuit 203 and the like. Lead the internal registry of the system to control the system. The system interface circuit 207 corresponds to the system interface circuit 3 in FIG. The binarization circuit 200, the modulation circuit 202, the servo circuit 208, and the like are connected to the preprocessing LS1224. The preprocessing LSI 224 amplifies the record information read from the DVD disk by the optical pickup 225, and supplies an information signal for reproducing the record information to the binarization circuit 200. In addition, it generates focus error and tracking error signals from the information signal envelope and the like, and supplies them to the servo circuit 208. The servo circuit 208 controls the focusing and tracking of the optical pickup 225 based on the information. In addition, the low frequency component of the tracking control is extracted, and the D / A conversion output controls the thread motor 227 of the optical pickup 225. In addition, the disk rotation speed is detected by pulse detection, servo processing is performed, and spindle motor control is performed by DZA conversion output. The focusing and tracking of the above-mentioned big-up, and the driving of the thread motor and the Svindormo are performed by the motor driver IC226.

The operation of the DVD drive system shown in FIG. 10 when reproducing recorded information will be described.

The microcomputer 220 monitors the command input from the input / output circuit and the key input of the input / output port, and when there is an input, decodes the contents of the input command ゃ key. The operation starts according to this.

The microcomputer 220 initializes the operation setting register of the servo circuit 208 via the microcomputer interface 207, and operates the focus and tracking servo control. When the focus is locked, the disk is rotated by the spindle motor 228, and the optical pickup 225 is moved to a predetermined position.

During playback, the data read by the optical pickup 2 25 The signal is converted into a digital signal by the preprocessing LSI 224, and is input to the DVD controller 1B. The input data is first input to the demodulation circuit 201, and in the case of DVD, demodulation of 8-16 system, dinterleaving, detection of sink, and the like are sequentially performed. When a predetermined amount of data is demodulated, an input request is output to the memory interface circuit 204. The memory interface circuit 204 receives the input request at a predetermined timing, and transfers the demodulated data from the demodulation circuit 201 to the data memory (DRAM) 212.

When a predetermined amount of data (in the case of DVD, one block: 182 × 208 bytes) is accumulated in the data memory 212, an interrupt request is generated from the memory interface circuit 204 and the error correction circuit 203 The interrupt is recognized and error correction processing (decoding) starts.

When the error correction processing of the predetermined data is performed, the error correction circuit 203 sets a predetermined register and the like, and instructs the data output. In accordance with this, the A TAP I interface circuit 206 issues an output request to the memory interface circuit 204. The memory interface 204 receives the output request at a predetermined timing, and outputs the data from the data memory 212 to the ATA PI interface circuit 206. The ATAP I interface circuit 206 operates like a personal computer. Outputs data to the interface circuit of the host device.

Also, depending on the contents of the command key, the error correction circuit 203 sets a predetermined register of the general-purpose interface circuit (general-purpose IF) 230 and instructs the output of the data. In the case of video data, data from the general-purpose IF 230 is supplied to a not-shown MPEG circuit, decompressed, and displayed on a display device such as an LCD.

Completion of the command key or completion of the next command key Until the above operation is continued.

The information recording operation in the DVD drive system shown in FIG. 10 will be described. In the same manner as described above, the microcomputer 220 monitors command input from the input / output circuit and key input of the input / output port, and when there is an input, the content of the input command or key is monitored. Decrypt and start operation accordingly.

The microcomputer 222 initializes the servo circuit 208 via the microcomputer interface circuit 207 to operate the focus and tracking servo control. When the focus servo is locked, the microcomputer 220 operates as a spindle motor. In the evening, the disk is rotated at 228, and the optical pickup 225 is moved to a predetermined position.

The ATAPI interface circuit 206 issues a data request to the host device and inputs data. When a predetermined amount of data is input, the ATAPI interface circuit 206 issues an input request to the memory interface circuit 204. The memory interface circuit 204 receives an input request at a predetermined time, and transfers data input from the ATAPI interface circuit 206 to the data memory 212.

When a predetermined amount of data (one block in the case of a DVD) is stored in the memory 212, an interrupt request is given from the memory interface circuit 204 to the error correction circuit 203, and Therefore, the error correction circuit 203 performs a parity addition process (encoding) on the data stored in the data memory 212.

When the error correction circuit 203 completes the noise addition processing for the predetermined data in the data memory 212, the completion of the noise addition processing is given to the modulation circuit 202. In response to this, the modulation circuit 202 transfers the data subjected to the parity addition processing from the memory to the modulation circuit 202. The data transfer control is started, and the data is internally transferred from the data memory 212 to the modulation circuit 202 via the memory interface 204. In the case of DVD data, the modulation circuit 202 sequentially performs in-leave, insert sync, 8-16 modulation, and outputs the data. The output data is amplified by the preprocessing LSI 224 and written to the optical disk via the optical pickup 225.

FIG. 11 shows the entire DVD drive system. The optical pickup 225 shown in FIG. 10 comprises a pickup 225B for focusing and tracking, and a pick amplifier 225A comprising a laser diode and the like. The module I / C 226 of FIG. 10 includes a driver 226A of Akche 225B, a driver 226B of a thread 228, and a driver 226C of a spindle 227. Here, the pre-processing L S I 224 is generically referred to by the read channel. The read channel includes a preamplifier for reading information.

The DVD controller 1B is used for recording / reproducing information on / from a real disk 230 such as a CD and a DVD, and servo control for the disk 230. That is, the DVD controller 1B obtains the tracking error signal TE, the focus error signal FE, and the like from the read channel 224, and controls the servo control signal so as to achieve tracking and focusing of the big 225A. Apply SVD AO, SV DA 1 to driver 226 A, apply servo control signal SVD A 2 to driver 226 B, and apply servo control signal SVD A3 to driver 226 C. Further, the DVD controller 1B inputs and demodulates the signal DIN read from the disk 230 and amplified by the read channel 224, and modulates data to be written to the disk 230. The A TAP I interface circuit as a host interface is based on the Enhanced I It is connected to a host device such as a personal computer via a path such as the DE path, and inputs commands, etc., and displays status, etc., and outputs data.

Information recorded on the optical disk 230 is read by the pickup 225A. The big-up 225 A outputs laser light by a light emitting element (laser diode) and detects reflected light from the optical disk 230 by a light receiving element (photo diode). The position of the pickup 230 is controlled by the actuator 225B and the thread motor 228.

The signal output from the pickup 225 A is amplified by the read channel 224 and digitized. The microcomputer 220 controls the read channel 224 using the SCI and IZO ports. For the tray whose illustration of the disk 230 is omitted, a control signal of an open switch and a close switch is input from the I / O port of the micro-computer 220, and an output switch signal is input as an interrupt request signal. The microcomputer is driven by the output of the PWM of the microcomputer 220.

The DVD drive system shown in FIG. 11 can perform recording / reproducing on CD-ROM and reproducing on CD-DA in addition to DVD. Basic playback processing is almost the same as that of DVD. That is, like a DVD, a signal read out from a disk 230 such as a CD-ROM or a CD-DA with a pickup of 255 A is amplified by a preamplifier of a lead channel 224, and then digitally processed by a waveform shaping circuit. Shaped into a waveform. The CD-ROM data is digitally demodulated by the demodulation circuit 201 of the DVD controller 1B, error-corrected by the error correction circuit 203 in the same manner as described above, and then decoded by the desk lamp 215. Rampled. The data after the descrambling process is read from CD-ROM by ROM decoder 211. The data is decoded into a data format from the format to the host device, and is provided to the host device via the host interface circuit 206. The CD-DA data is decoded by the decoding circuit 210, stored in the data memory 212, subjected to error correction and the like, and then output to the host device via the host interface circuit 206.

When the disk 230 is loaded, the microcomputer 220 reads out TOC (Table Of Contents) information and the like on the disk and stores it in the buffer memory. In the case of CDs, the TOC information in the lead-in section is a maximum of 100 songs, each of which is a short burst of 9 bytes, etc., and is stored in a high-density buffer memory for physical use. Efficiency is improved, and reading is possible at any time by the microcomputer 220, so that the amount of movement can be calculated at the time of seeking, and can be used immediately in response to commands from the host interface. . For DVD-ROM discs, Microcomputer 220 will always read ID ICoby Protection Data from Read Data.

Further, the micro-computer 220 reads out the defect information from the DVD-RAM disk and stores it in a non-volatile memory, and the microcomputer 220 sends the logical address specified by the host interface 206 to the physical address. Refer to when converting to an address.

FIG. 12 shows a system operation flowchart of the DVD drive system of FIG. In FIG. 12, the parallelism of the data processing units 20-1 to 20-n is P, the initial value of the parallelism is Pi, the operation speed is S, and the operation speed initial value is Si.

After the power-on reset, when the tray is opened and closed and the loading of the disk 230 is confirmed (31, 32, 33),? = 1, 3 = 1 Prescanning of the disc is started (S4). From the information read by the pre-scan, the disc type and error rate are checked (S5 to S8). According to the result, the parallelism P i is set to 1 to 4 (S 9 to S 12). This is a capability setting based on the disk status.

Next, a command is input (S13). When the input command is "P LAY" (S14), S = S i and P = P i are set (S 15). When the input command is "JUMP ,,," "ST0P", (S17, S18), P = 1 and S = 1 are set, and the processing capacity is reduced (S19, S20 o This is a capability setting by command.

Here, as the above command, it is recommended to use a command secured as a vendor-unique in the host interface standard.

Next, the operation in the PLAY mode (mode = 1) will be described. In FIG. 12, in the PLAY mode, the parallelism of the data processing unit is not changed. In order to change the degree of parallelism of the data processing unit during operation, it is necessary to have a configuration or control for grasping the processing state of the data processing unit, and if such a configuration or control is not adopted, it can be easily changed. Therefore, in the example of Fig. 12, the change of the processing capacity in the PLAY mode is limited to only the change of the operation speed.

In the play mode, normally, the operation is performed with the capability of S = S i and P = P i according to the setting contents of step S 16. When the number of errors increases and the processing cannot be performed in time, the error correction circuit 203 asserts the external standby signal 55. When the micro-combination 220 detects an external standby signal 55 assertion (wait instruction) (S21), it determines whether S = 4 or not (S22), and S = 4. If so, the micro computer 220 instructs the demodulation circuit 201 and the like to temporarily stop the operation (S23). If S = 4, the operation speed of the error correction circuit 203 is set as S = S + 1. Raise (S24). This is an example of changing the processing capability of the error correction circuit 203 by speed control.

If the current consumption increases and exceeds an arbitrary set value (S25), the microcomputer 220 changes the setting to S = S-1 with S = l as the lower limit, and the operating speed. To reduce power consumption (S26, S27). This is an example of processing capacity change due to external conditions.

If the current consumption has not increased in the determination in step S25, the wait instruction and the power consumption may be monitored for a certain period of time (S28), and if there is no change, S == Si may be returned ( S29).

In this way, by adjusting the processing capacity according to the external situation and the situation of the disk, power consumption can be reduced.

In addition, although not shown in FIG. 12, the system configuration of the host device is determined, and if the host device is a personal computer, whether the host device is a notebook type or a desktop type is determined. May be set. For example, in the case of a notebook type, the degree of parallelism is reduced compared to a desktop type. Also, systems such as DVD-RAM require error correction (data decoding) and data encoding. Data encoding requires less processing than data decoding. Also, the writing speed of the disk is slower than the reading speed. In consideration of this, at the time of writing, the data processing unit in the error correction circuit 203 may be used with a reduced degree of parallelism.

<< Other forms of data processing device >>

Although the data processing devices 1A and 1B are in the SIMD form, the data processing devices may be configured in the MIMD form.

FIG. 13 shows an example of a MIMD type data processing device. The difference from FIG. 1 is that the data processing units 20 C-1 to 20 C-n each execute an arithmetic processing by fetching an instruction. Therefore, individual data processing The units 20 C-1 to 20 C-n have an instruction control unit and an operation unit. Data processing section 20 C— :! 220C-n is a circuit such as a CPU unit, a floating-point arithmetic unit, and a digital signal processing unit. Also in such a MIMD type data processing device, the operation speed can be controlled in accordance with the externally set value for the operation speed register 32 as in FIG. Further, the degree of parallelism of the data processing units 20C-1 to 20C-n can be controlled in accordance with an externally set value for the parallel degree register 41.

FIG. 14 shows still another example of the data processing apparatus. The data processing device 1D shown in the figure has an input circuit 5D, an output circuit 6D, a data memory 7D for storing data, a memory interface circuit 4D, and n parallel operation. A data processing circuit 20 D— 1 to 20 D—n, a demultiplexer 40 2 that supplies data to the data processing circuit in parallel, a multiplexer 40 1 that outputs data according to the result of the parallel processing, It is composed of a parallel degree register 41 and a parallel degree control circuit 400.

The parallelism control data is externally set in the parallelism register 41 via, for example, an external terminal (not shown). According to the parallelism control data set in the parallelism register 41, the parallelism control circuit 400, the demultiplexer 402, the data processing circuit 20D-1 to 20Dn, And the multiplexer 401.

The input circuit 5D performs preprocessing such as demodulation as needed on data read from a recording medium such as a DVD, and transfers the data to the data memory D. At this time, since the order of input data is often not suitable for the order of processing, the data is temporarily stored in the data memory 7D, converted to an order suitable for processing, and processed in parallel through the demultiplexer 402. Circuit 20 D—1 to 20 D—n. Processing results are not always output However, it is described as an output in Fig. 14. Although not necessarily simultaneous, the processing results obtained in parallel are stored in the data memory 7D through the multiplexer 401. The output circuit 6D outputs the processing results stored in the memory 7D in an appropriate order and transfer rate. The memory interface circuit 4D arbitrates a contention state for a memory access request from the input circuit 5D, the output circuit 6D, and the data processing circuit 20D-1 to 20D-n. .

The parallelization of the data processing circuits 20 D-1 to 20 D-n is frequently used because it is effective for easily improving the overall processing capacity. In a data processing system to which the data processing device 1D is to be applied, the maximum processing capacity required from the usage environment is high, so the use of parallel processing can effectively satisfy the maximum processing performance specifications. Although n data processing circuits 20 D- 1 to 20 D-n are provided in parallel to satisfy the specification of the maximum processing performance, if only m m circuits are needed in normal use, external Degree of parallelism Set the degree of parallelism m (m <n) to the register 41 and demultiplexer 402, multiplexer 401, and data processing circuit 20D— :! 2 to 0 11 are controlled so as to operate at the parallel degree m. At this time, the power consumption of the entire data processing circuit can be reduced to mZn by controlling the non-operating processing circuit so that the clock signal is not supplied by the parallelism control circuit 400. As a whole, the power consumption of the other circuits is added as a fixed value. However, in many cases, the ratio of the data processing circuit to the total power consumption is high, so that the effect of reducing the power consumption as a whole is great.

《Effects of speed control and parallelism control》

Since the degree of parallelism of the data processing unit represented by the codes 20-1 to 20-0-n can be variably controlled externally, the processing capacity and power of the data processing device (1A, IB) can be adjusted at least according to external conditions. Consumption can be controlled. Ma In addition, since the operating speed can be variably controlled from outside, the processing capability and power consumption of the data processing device can be similarly controlled according to the external situation. In particular, speed control can be performed without affecting the processing procedure at all, irrespective of the progress of the data processing step, so that speed control can be performed freely even during a series of processing.

Therefore, by enabling both the variable degree of parallelism and the variable operation speed, it is possible to finely control the processing capacity and power consumption.

By monitoring the data processing status according to the accumulation status of the data in the data memory 7 overnight, and notifying the status to the outside with the external standby signal 55, it becomes easy to control the processing capability by the outside. Furthermore, if the boys 51 to 53 provided for monitoring can be directly referred to from outside, it will be easier to control the processing capacity from outside.

SIMD-type data processing devices are often used for processing such as image or audio processing, and are originally intended to improve the data processing capacity.However, depending on the contents of the calculation processing and the data to be calculated, the original calculation processing There may be situations where 100% of the ability is not used. In such a case, if the speed control and the parallelism control can be performed flexibly from the outside as described above, it is possible to maximize the effects of improving data processing efficiency and reducing unnecessary power consumption. Can be. For example, when decompressing compressed data, the required processing changes depending on the data. Unnecessary power consumption can be reduced by changing the processing capacity according to the data.

In addition, when applied to the error correction circuit 203, the error correction processing step does not need to be executed if there is no error. Therefore, if the degree of parallelism is changed according to the processing status, the improvement in data processing efficiency and wastefulness The effect of reducing power consumption can be maximized. Normally, the processing capacity is reduced, and the unprocessed data is processed according to the contents of pointers 51 to 53 and the state of external standby signal 55. When the number of nights increases, the processing capacity may be increased. In addition, when the number of processed data increases, the processing capacity can be reduced. As a result, the average power consumption can be reduced according to the content of the data, in other words, according to the required processing capacity.

When applied to a disk drive device such as a DVD drive, the power consumption can be reduced by adjusting the processing capacity according to the external situation and the situation of the disk. ... Systems such as DVD-RAM require error correction (de- night decoding) and data encoding. Data encoding requires less processing than data decoding. Also, since the writing speed of the disk is slower than the reading speed, it is possible to reduce the power consumption by lowering the degree of parallelism during writing.

The power consumption can be switched according to the system to which the data processing device is applied, for example, a notebook-type personal computer / desktop-type personal computer, which can contribute to improvement in system development efficiency and productivity.

Error correction circuits with variable processing capability are commonly used for encoding and Z-decoding, and when encoding requires only syndrome operation, the degree of parallelism can be reduced or the clock division ratio can be reduced. Or lower the power consumption according to the required processing capacity.

Even if the processing speed and the degree of parallelism are variable, there is no need to change the basic program, so that the program development efficiency is not hindered. Since the division ratio of the clock signal can be easily changed during operation, optimal control can be performed at any time.

Built-in host interface circuit allows power consumption to be changed based on a command from the host computer, for example. Such commands include the use of user-defined commands provided in the host interface circuit to add new hardware to the drive system. No need.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, the data processing device may be configured by employing only one of the speed control and the parallel degree control. Also, the standby control in each data processing unit need not be adopted. Further, the data memory may be built in the data processing device. Conversely, the program memory for the instruction control unit may be external.

Various circuits on-chip in the data processing device are not limited to the circuits described in FIG. 1 and the like, and can be appropriately changed. Further, the arithmetic processing by the data processing unit is not limited to error correction, but may be processing such as decompression / compression, modulation / demodulation, and the like. Therefore, the data processing device is not limited to being applied to an LSI for a disk controller, but can be widely applied to an LSI for communication and the like.

Although the control registers 32, 41 and the pointers 51, 52, 53 for changing the processing capacity described in FIG. 1 are provided in the data processing device, the microcomputer 220, etc. It may be placed in the system controller. Industrial applicability

The present invention relates to an optical disk drive device such as a DVD or a CD-ROM, an interface controller for communication, and a signal processing device such as a digital video camera and a digital still camera for compressing and expanding image data. It can be widely applied.

Claims

A plurality of data processing units capable of operating in parallel, a control register storing control data in accordance with an external instruction, and the plurality of data processing units according to control data stored in the control register. A data processing device comprising: a parallelism control unit for determining a parallelism of the parallel operation. The plurality of data processing units operate in synchronization with a clock signal output from a clock generation circuit, and the parallelism control unit includes a selection gate that separately supplies the clock signal to the data processing unit. 2. The data processing apparatus according to claim 1, wherein the selection gate determines whether or not to output a clock signal based on the control data. 3. The data according to claim 2, wherein the clock generation circuit is configured to be capable of selecting a frequency of a clock signal in accordance with another control data of the control register. Processing equipment. A command control unit that decodes the fetched command and outputs control information, wherein the command control unit is capable of supplying control information for arithmetic operation to the plurality of data processing units in parallel; 2. The data processing device according to claim 1, wherein the data processing is performed in a SIMD format. The control unit further includes a program memory storing an error correction program for performing error correction. 5. The data processing apparatus according to claim 4, wherein the data processing unit fetches an instruction from the program memory and performs an error correction process using the data processing unit. The data processing unit includes a Galois field arithmetic circuit capable of performing Galois field multiplication and addition, and the control unit controls the Galois field arithmetic circuit to cause the data processing unit to perform an error correction process. 6. The data processing device according to claim 5, wherein the data processing device is formed on a single semiconductor substrate. 7. The control unit is capable of controlling transfer of unprocessed data stored in a data memory to the data processing unit, and controlling transfer of processed data processed by the data processing unit to the data memory. A monitoring circuit that monitors a status of the arithmetic processing performed by the data processing unit, wherein the monitoring circuit is configured to determine whether an unprocessed data amount remaining in the data memory exceeds a predetermined amount based on an access address to the data memory. 5. The data processing apparatus according to claim 4, wherein the data processing apparatus outputs a signal for notifying a state to the outside to the outside. A plurality of data processing units capable of operating in parallel in synchronization with a clock signal; a control register storing control data according to an external instruction; and a frequency of the clock signal according to control data stored in the control register. And a speed control unit for determining the speed of the data. A command control unit that decodes the fetched command and outputs control information, wherein the command control unit is capable of supplying control information for an arithmetic operation to the plurality of data processing units in parallel; 9. The data processing device according to claim 8, wherein data processing is performed in a SIMD format. 0. The apparatus further comprises a program memory storing an error correction program for performing error correction, wherein the control unit fetches an instruction from the program memory and performs an error correction process using the data processing unit. 10. The data processing device according to claim 9, wherein:

1. The data processing unit includes a Galois field arithmetic circuit capable of performing Galois field multiplication and addition, and the control unit controls the Galois field arithmetic circuit to perform error correction processing on the data processing unit. 10. The data processing device according to claim 10, wherein the data processing device is formed on one semiconductor substrate.

2. The control unit controls the transfer of the unprocessed data stored in the data memory to the data processing unit, and transfers the processed data processed by the data processing unit to the data memory. Controllable,

A monitoring circuit that monitors a status of the arithmetic processing by the data processing unit;

The monitoring circuit outputs, based on an access address to the data memory, a signal for notifying an external state that the amount of unprocessed data remaining in the data memory exceeds a certain amount. 9. The data processing device according to claim 8, wherein the data processing device is characterized in that:

3. A plurality of data processing units capable of operating in parallel in synchronization with the clock signal, a first control register holding the first control data according to an external instruction, and a second control data according to the external instruction. A second control register for storing the data and a first control data stored in the first control register for determining the degree of parallel operation of the plurality of data processing units in accordance with the first control data; Data comprising: a control unit; and a speed control unit that determines a frequency of the click signal in accordance with second control data held by the second control register. Processing equipment.

4. It further has an instruction control unit for decoding the fetched instruction and outputting control information, and the instruction control unit can supply control information for arithmetic operation to the plurality of data processing units in parallel. Data processing in SIMD format 14. The data processing apparatus according to claim 13, wherein the processing is performed.

5. It further comprises a program memory storing an error correction program for performing error correction, wherein the control unit retrieves an instruction from the program memory and performs an error correction process using the data processing unit. The data processing device according to claim 14, wherein:

6. The data processing unit includes a Galois field arithmetic circuit capable of performing Galois field multiplication and addition, and the control unit controls the Galois field arithmetic circuit to perform error correction processing on the data processing unit. 16. The data processing device according to claim 15, wherein the data processing device is formed on one semiconductor substrate.

7. The control unit can control the transfer of the unprocessed data stored in the data memory to the data processing unit, and can control the transfer of the processed data processed by the data processing unit to the data memory. And

The monitoring circuit outputs, based on an access address to the data memory, a signal for notifying an external state that the amount of unprocessed data remaining in the data memory exceeds a certain amount. The data processing device according to claim 13, wherein the data processing device is characterized in that:

8. An input circuit for inputting data from the outside, and a data input from the input circuit are stored. The stored data is provided to the data processing unit, and the data processing unit calculates the data. It is characterized by being formed on one semiconductor substrate, further including a data memory for storing data again, and an output circuit for outputting data stored in the data memory to the outside. The data as set forth in claims 1, 3, or 13. Evening treatment equipment.

19. The input circuit further comprises: demodulation means for demodulating an input signal; and data transfer control means for transferring the demodulated data to the data memory. Item 18. The data processing equipment described in Item 18.

20. The apparatus according to claim 1, further comprising a system interface means, wherein said data transfer control means is configured to enable a transfer control condition to be set via said system interface means. Item 9. The data processing device according to item 9.

21. The data processing apparatus according to claim 20, wherein said control register is directly accessible from outside via said system interface means.