[go: up one dir, main page]

WO2000076256A1 - Commutateur photonique utilisant l'echange de creneaux - Google Patents

Commutateur photonique utilisant l'echange de creneaux Download PDF

Info

Publication number
WO2000076256A1
WO2000076256A1 PCT/US2000/014484 US0014484W WO0076256A1 WO 2000076256 A1 WO2000076256 A1 WO 2000076256A1 US 0014484 W US0014484 W US 0014484W WO 0076256 A1 WO0076256 A1 WO 0076256A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
schedule
time
input
optical
Prior art date
Application number
PCT/US2000/014484
Other languages
English (en)
Inventor
Philip P. Carvey
William J. Dally
Original Assignee
Avici Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avici Systems filed Critical Avici Systems
Priority to AU52919/00A priority Critical patent/AU5291900A/en
Publication of WO2000076256A1 publication Critical patent/WO2000076256A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects

Definitions

  • High-speed telecommunications switches accept optical inputs and produce optical outputs but internally involve almost entirely electronic switching.
  • Single-mode optical fibers are the technology of choice for long-haul transmission of information because they have very wide bandwidth, low attenuation, and low dispersion, making it possible to transmit information at very high bit rates (10 10 b/s) over long distances (10 5 m) without the need of repeaters.
  • Digital electronics is the technology of choice for switching. Digital integrated circuits can switch connections in less than a nanosecond, and 10 5 to 10 6 digital gates can be incorporated on a single integrated circuit facilitating construction of the logic that controls a fast switch on a cycle by cycle basis.
  • FIG. 1 shows a block diagram of a prior art telecommunications switch.
  • Inputs arrive on single-mode optical fibers 101.
  • these fibers carry a serial bit stream at 2.5Gbits/s (OC48) and are formatted using SONET (synchronous optical network) framing.
  • the signal on each input fiber 101 is converted to electrical form by optical-to-electrical (O/E) converters 102.
  • O/E converters demultiplex the data stream, converting the 2.5Gbits/sec serial stream into a 16-bit wide stream at 156Mbits/s.
  • This electrical version of the input stream 103 is then input to an electronic switch 1-4.
  • the switching fabric of the internet routers described in published PCT patent application number PCT/US98/16762 is an example of such a switch.
  • the switch extracts individual packets or cells (depending on the protocol) from the SONET frames (or other framing) of the incoming streams on each input and forwards each packet or cell to the output to which it is addressed.
  • the packets or cells are encapsulated in a
  • This electrical output stream 105 is then output to an electrical-to-optical converter (E/O) and the optical output stream 107 drives the long-haul fiber to the next telecommunications switch.
  • E/O electrical-to-optical converter
  • the switch requires logic to examine the contents of packets and determine where they are to be routed, and the switch requires memory to buffer packets according to a quality-of-service policy.
  • a telecommunications switch comprises a plurality of optical inputs and a plurality of optical outputs.
  • An optical switch operates with a schedule that is not directly determined by the input stream.
  • the ordering units rearrange the order of data units, such as packets or cells, within data streams to correspond to the schedule of the switch. The reordering may be made in either input streams or output streams.
  • Preferred switches include a crossbar or a multi-stage interconnection network.
  • the preferred reordering unit is a time-slot interchanger which contains a plurality of FIFOs.
  • the FIFOs are implemented as circular buffers in a single dual port memory.
  • the switch schedule may be fixed and balanced, or it may be unbalanced. In the latter case, the switch schedule may be determined by the average load between inputs and outputs. More specifically, the switch schedule may be determined by the number of data units queued from each input for each output in time-slot interchangers.
  • the present invention combines the best features of electronics and optics to overcome the bandwidth bottleneck of electronic switching, while at the same time using electronics to provide logic and memory. Also, this arrangement handles the switching of short (nanosecond) packets using optical switches that can be reconfigured at microsecond to millisecond time scales.
  • the present invention does require conversion of the input signal from electrical to optical and back again. However, this conversion is required in any case for signal regeneration.
  • the present invention is also well matched to the properties of an optical switch. By grouping many packets traveling to the same output together in time, the present invention allows short (nanosecond) length packets to be switched while reconfiguring the optical switch only once every sub-frame, frame, or multi-frame time period (microseconds or milliseconds). Also, the optical switch can be controlled with a fixed pattern, without the need to examine the arriving data to configure the switch. Alternatively, the switch can be controlled with an adaptive pattern that uses only average input to output load statistics to balance load across the switch. In either case, the configuration of the optical switch does not directly depend upon the data it is switching.
  • FIG. 1 is an illustration of a conventional telecommunications switch
  • Fig. 2 is an illustration of one embodiment of the present invention
  • Fig. 3 is an illustration of an alternative embodiment of the invention
  • Fig. 4 shows an example of the schedule of input/output connections in a switch
  • Fig. 5 illustrates the connections of Fig. 4 in graphical form
  • Fig. 6 illustrates an exemplary input sequence of data packets in the reordering of the sequence
  • Fig. 7 illustrates an unbalanced schedule
  • Fig. 8 illustrates a FIFO implementation of a time-slot interchanger
  • Fig. 9 illustrates a dual port memory implementation of a time-slot interchanger.
  • each electronic input stream 103 is input to a time-slot interchanger (TSI) 111.
  • the TSI examines the packets within an input stream, using logic to make routing decisions, and reorders them in time (exchanging their time slots) so that packets traveling to a given output are grouped together in time.
  • the reordered streams 112 are then converted back to optical form.
  • These reordered optical streams 113 are then input to an all-optical switch that changes its connectivity in a fixed pattern at a relatively slow rate.
  • Each TSI schedules the packets entering the optical switch to arrive at a time when its input is connected to the packet's destination.
  • Fig. 6 shows an input stream of packets 201 on an input line 101 and a reordered stream of packets 202 on internal line 113.
  • Each packet is marked with a number denoting the output port to which it must be forwarded and a letter denoting its sequence.
  • packet 2b is the second packet that must be forwarded to output port 2.
  • the TSI 111 reorders the packets in input stream 201 so that all packets destined for the same output are consecutive and occupy a fixed time period on the reordered stream 202 on internal line 113.
  • This ordering of packets matches the connections provided by the optical switch 114 under control of sequencer 115.
  • Figs. 4 and 5 show, in tabular form, how the sequencer directs the switch to connect inputs to outputs during each of the four periods.
  • Fig. 5 shows this same information graphically.
  • the figures show that the inputs are connected straight across to the outputs.
  • the connections are rotated by 1 with input 1 connected to output 2, input 2 to output 3, and so on.
  • input i is connected to output i+x-1 (mod 4).
  • the sequencer repeats these four connections indefinitely, connecting each input to each output in turn.
  • the interchangers knowing this pattern in advance, schedule packets to appear on a switch input during the time period when that input is connected to the desired output.
  • each time period or time-slot is 10 microseconds in length.
  • the TSI 111 that reorders packets to make packets destined for the same output contiguous can be conceptually implemented using a FIFO for each output as illustrated in Fig. 8 for the case of four outputs.
  • the interchanger consists of four FIFOs 151-154, and a multiplexer, 160.
  • multiplexer 160 is switched to select the FIFO associated with the selected output of the switch.
  • Packets are then read from this selected FIFO to reordered electronic input stream 112 until the time-slot is over or the FIFO is emptied. If the FIFO is emptied before the time-slot is over, idle symbols are transmitted through the switch. If the time- slot expires before the FIFO is empty, the packets remaining in the FIFO are retained and will be transmitted during a later time-slot when the switch is connected to the same output.
  • FIFO 152 is selected and packets 2a and 2b are transmitted on stream 112 to be forwarded to output 2, and so on.
  • the four FIFOs 151-154 of the TSI 111 are implemented with a single dual port memory 221, as illustrated in Fig. 9.
  • the contents of each FIFO are stored in dedicated circular buffers in memory 221 (denoted by the dotted lines).
  • Memory 221 is a dual port memory with one read port and one write port.
  • the write port consists of data input 222 and write address 223.
  • the read port consists of data output 224 and read address 225.
  • Each circular buffer is indexed by one of the tail pointers 231-234 and one of the head pointers 251-254.
  • a write address multiplexer 241 selects one of the tail pointers to be used as the write address for memory 221.
  • a read address multiplexer 261 selects one of the head pointers to be used as the read address for memory 221.
  • the packet When a packet arrives at the TSI of Fig. 9, the packet is examined to determine its output port and multiplexer 241 selects the tail pointer associated with this output. As each word of the packet arrives, it is placed on the data input line 222 and written into the appropriate circular buffer using the selected tail pointer as the write address 223. The tail pointer is then incremented with a limit check to wrap addresses within the circular buffer. The tail pointer is also compared to the corresponding head pointer to check for a buffer- full condition. When a new time- slot begins, the output multiplexer selects the head pointer associated with the output corresponding to this time-slot to be used as the read address.
  • All of the packets associated with the output are then read out of the selected circular buffer, incrementing the head pointer (with circular buffer wrapping) after each word of a packet is read.
  • the head pointer is compared to the corresponding tail pointer after each increment to detect an empty circular buffer.
  • optical switch 114 is implemented using a LiNbO 3 non-linear optical crossbar switch.
  • the switch is implemented as a multi-stage optical switching network, as described in Chamberlain, et al., "Design of an Optically-Interconnected Multiprocessor," Proceedings of the Fifth International Conference on Massively Parallel Processing using Optical Interconnections, IEEE, July 1998.
  • the present invention allows data to be switched to the desired output of an optical switch with fixed control (the data need not be examined to control the switch). However, it can only achieve full throughput when each input carries an equal amount of traffic destined for each output. This is because the switch schedule shown in Figs. 4 and 5 is balanced, with each input connected to each output for equal amounts of time. If the input traffic is not balanced, one or more of the FIFOs in the interchanger may be overrun, resulting in loss of data.
  • FIG. 7 This figure illustrates an eight period schedule.
  • input 1 sends three units of traffic to output 2, one unit of traffic to output 3, and two units of traffic to all other outputs.
  • Input four sends three units to output 3, one unit to output 2, and two units to outputs 1 and 4.
  • the traffic from inputs 2 and 3 is balanced.
  • Unbalanced switch schedules such as the one shown in Fig. 7 can be generated automatically by examining the occupancy of each of the four FIFOs in each of the four interchangers.
  • the interchanger finds the input 1 FIFO with the least occupancy (in this case, the one containing traffic to output 3), and swaps outputs with the interchanger (in this case, the input 4 interchanger) that connects to 2 during the cycle that 1 would normally connect to 3.
  • the schedule shown in Fig. 7 is generated.
  • this schedule is dependent on the data being transported, it still has two properties that make it suitable for driving an optical switch.
  • the switch is still set to one configuration during a period that spans many packets. In this case, however, the periods may be unbalanced to match the unbalance in input traffic.
  • the position of the optical switch 114 and the TSI 111 are reversed.
  • the switch output taken by a packet on the present telecommunications switch is determined by the TSI on the output of the upstream telecommunications switch: the switch that drives the input line 101.
  • the TSI 111 on the output of that switch schedules packets so that they appear during the proper time-slot of the present switch.
  • the optical switch may be implemented using thermally actuated directional couplers, mechanically actuated optical switches, or piezoelectrically driven optical switches.
  • the configuration of the switch may also be varied.
  • a crossbar with any number of ports may be implemented, a multi-stage network may be implemented, or a direct interconnection network may be implemented.
  • the present invention can also be implemented with time slots of varying sizes. With slow acting mechanical, thermal, or piezoelectrically-driven switches, the time-slot may be increased to a millisecond or more (at the expense of larger FIFO buffers in the TSI).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Optical Communication System (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Un train de données optiques est converti en signaux électriques qui s'appliquent à un échangeur de créneaux temporels. Ce dernier reclasse les paquets ou cellules du train de données de façon à respecter optique. L'échangeur de créneaux peut contenir une pluralité de tampons circulaires opérant en listes directes dans une unique mémoire à deux ports. L'emploi du temps du commutateur, qui peut être établi en fonction d'une charge moyenne entre les entrées et les sorties, peut également être établi en fonction du nombre de paquets ou de cellules mises en file d'attente à partir de chaque entrée ou de chaque sortie dans les échangeurs de créneaux.
PCT/US2000/014484 1999-06-03 2000-05-25 Commutateur photonique utilisant l'echange de creneaux WO2000076256A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU52919/00A AU5291900A (en) 1999-06-03 2000-05-25 Photonic switch using time-slot interchange

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/325,119 US6934471B1 (en) 1999-06-03 1999-06-03 Photonic switch using time-slot interchange
US09/325,119 1999-06-03

Publications (1)

Publication Number Publication Date
WO2000076256A1 true WO2000076256A1 (fr) 2000-12-14

Family

ID=23266523

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/014484 WO2000076256A1 (fr) 1999-06-03 2000-05-25 Commutateur photonique utilisant l'echange de creneaux

Country Status (3)

Country Link
US (1) US6934471B1 (fr)
AU (1) AU5291900A (fr)
WO (1) WO2000076256A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006081128A1 (fr) * 2005-01-27 2006-08-03 Intel Corporation Systeme de commutation par paquet a etapes multiples a acheminement du trafic alterne
US7519054B2 (en) 2005-01-27 2009-04-14 Intel Corporation Replication of multicast data packets in a multi-stage switching system
US7590102B2 (en) 2005-01-27 2009-09-15 Intel Corporation Multi-stage packet switching system
US7864757B2 (en) 2002-04-17 2011-01-04 Cambridge University Technical Services Limited Packet switching
WO2014180311A1 (fr) * 2013-05-10 2014-11-13 Huawei Technologies Co., Ltd. Systeme et procede de commutation photonique

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167480B1 (en) * 2001-06-21 2007-01-23 Lighthouse Capital Partners Iv, Lp Multi-service data transport architecture
US7177314B2 (en) * 2001-08-30 2007-02-13 Pmc-Sierra, Inc. Transmit virtual concatenation processor
US7113505B2 (en) * 2001-12-17 2006-09-26 Agere Systems Inc. Mesh architecture for synchronous cross-connects
US7660731B2 (en) * 2002-04-06 2010-02-09 International Business Machines Corporation Method and apparatus for technology resource management
US7251416B1 (en) * 2002-05-08 2007-07-31 Yotta Networks, Llc Container based crossconnect
US7272309B1 (en) * 2002-05-08 2007-09-18 Yotta Networks, Llc System and method of routing data at a photonic core
US20040071171A1 (en) * 2002-08-06 2004-04-15 Ali Ghiasi Natural data ordering of a multiplexed high speed bit stream
NO320962B1 (no) * 2003-07-04 2006-02-20 Telenor Asa Anvendelse av polarisasjon for a skille ulike typer informasjon
JP4659656B2 (ja) * 2006-03-24 2011-03-30 富士通株式会社 光伝送装置、光伝送方法および光伝送制御プログラム
US9729946B2 (en) * 2009-04-03 2017-08-08 Infinera Corporation High-capacity switch
GB2474863A (en) 2009-10-28 2011-05-04 Univ Gent Optical buffer with controllable delay
CN106789753B (zh) * 2015-11-24 2020-06-26 新华三技术有限公司 一种线卡框、多框集群路由器、及报文处理方法
KR102524579B1 (ko) 2017-01-06 2023-04-24 한국전자통신연구원 파장 가변 레이저 다이오드의 파장이 변환되는 시간에 기초하여 포토닉 프레임을 전송할 시간을 결정하는 포토닉 프레임 스위칭 시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168492A (en) * 1991-04-11 1992-12-01 Northern Telecom Limited Rotating-access ATM-STM packet switch
EP0641108A2 (fr) * 1993-08-27 1995-03-01 Gpt Limited Elément de commutation de télécommunications
US5745486A (en) * 1995-10-26 1998-04-28 Northern Telecom Limited High capacity ATM switch

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485467A (en) * 1982-02-18 1984-11-27 Teknekron Infoswitch Corporation Digital information switch matrix with on-line/off-line diagnostic features
US5093920A (en) * 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
GB9104861D0 (en) * 1991-03-07 1991-04-17 Univ Strathclyde Communications switching network
DE4108213A1 (de) * 1991-03-14 1992-09-17 Standard Elektrik Lorenz Ag Optische vermittlungseinrichtung und schaltmodul dafuer
EP0533391A3 (en) * 1991-09-16 1993-08-25 American Telephone And Telegraph Company Packet switching apparatus using pipeline controller
EP0547836B1 (fr) * 1991-12-16 2001-12-19 AT&T Corp. Commutateur optique de paquets
JP2928046B2 (ja) * 1993-04-16 1999-07-28 日本電気株式会社 光ネットワ−ク及びその障害回復方式
ES2143632T3 (es) * 1994-05-23 2000-05-16 British Telecomm Red de telecomunicaciones optica.
US5475679A (en) * 1994-12-08 1995-12-12 Northern Telecom Limited Large capacity ATM switch
GB2300086B (en) * 1995-04-18 1999-08-04 Northern Telecom Ltd Switching arrangement
EP0748086A1 (fr) * 1995-06-09 1996-12-11 Siemens Aktiengesellschaft Procédé pour la planification de cellules de message sortantes d'un réseau ATM
US5978370A (en) * 1997-01-13 1999-11-02 At&Tcorp Circuit-switched switching system
US6285679B1 (en) 1997-08-22 2001-09-04 Avici Systems, Inc. Methods and apparatus for event-driven routing
US6417944B1 (en) * 1998-05-28 2002-07-09 3Com Corporation Asynchronous transfer mode switch utilizing optical wave division multiplexing
US6111673A (en) * 1998-07-17 2000-08-29 Telcordia Technologies, Inc. High-throughput, low-latency next generation internet networks using optical tag switching
US6185221B1 (en) * 1998-11-09 2001-02-06 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168492A (en) * 1991-04-11 1992-12-01 Northern Telecom Limited Rotating-access ATM-STM packet switch
EP0641108A2 (fr) * 1993-08-27 1995-03-01 Gpt Limited Elément de commutation de télécommunications
US5745486A (en) * 1995-10-26 1998-04-28 Northern Telecom Limited High capacity ATM switch

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7864757B2 (en) 2002-04-17 2011-01-04 Cambridge University Technical Services Limited Packet switching
WO2006081128A1 (fr) * 2005-01-27 2006-08-03 Intel Corporation Systeme de commutation par paquet a etapes multiples a acheminement du trafic alterne
US7489625B2 (en) 2005-01-27 2009-02-10 Intel Corporation Multi-stage packet switching system with alternate traffic routing
US7519054B2 (en) 2005-01-27 2009-04-14 Intel Corporation Replication of multicast data packets in a multi-stage switching system
US7590102B2 (en) 2005-01-27 2009-09-15 Intel Corporation Multi-stage packet switching system
WO2014180311A1 (fr) * 2013-05-10 2014-11-13 Huawei Technologies Co., Ltd. Systeme et procede de commutation photonique
US9584885B2 (en) 2013-05-10 2017-02-28 Huawei Technologies Co., Ltd. System and method for photonic switching

Also Published As

Publication number Publication date
AU5291900A (en) 2000-12-28
US6934471B1 (en) 2005-08-23

Similar Documents

Publication Publication Date Title
US6934471B1 (en) Photonic switch using time-slot interchange
Keslassy et al. Scaling internet routers using optics
Ramamirtham et al. Time sliced optical burst switching
US7042892B2 (en) Voice-over IP communication without echo cancellation
US5099475A (en) Switching system
US5734486A (en) Optical packet switching system
JP2595025B2 (ja) 空間分割形スイッチを用いた高速パケット交換装置
US7324537B2 (en) Switching device with asymmetric port speeds
AU618634B2 (en) Time division switch
EP1058195A2 (fr) Réseau logique minimal à niveaux multiples
EP0453129B1 (fr) Système de commutation temporel à grande vitesse
JPH08507428A (ja) メッセージ経路設定
JPH0392048A (ja) パケット伝送用交換器
JPH09507996A (ja) 大容量モジュールａｔｍスイッチ
US20030103501A1 (en) Message ring in a switching network
US7046660B2 (en) Switching apparatus for high speed channels using multiple parallel lower speed channels while maintaining data rate
US20060104281A1 (en) Packet routing
US6603771B1 (en) Highly scalable architecture for implementing switch fabrics with quality of services
US6157638A (en) High density packet switch with high speed interfaces and method for using same
US6956851B1 (en) Crossbar subsystem and method
US6700896B1 (en) High-capacity WDM data network
US20030048777A1 (en) Communication multistage switching techniques
JP3695853B2 (ja) 光バッファ装置
JP3434671B2 (ja) Ａｔｍセル交換装置
Keslassy et al. Scaling internet routers using optics (extended version)

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP