WO2000001075A1

WO2000001075A1 - Digital-to-analog converter using first order sigma-delta modulation

Info

Publication number: WO2000001075A1
Application number: PCT/US1999/013274
Authority: WO
Inventors: Domenico Arpaia; Alan Holden
Original assignee: Ericsson, Inc.
Priority date: 1998-06-26
Filing date: 1999-06-10
Publication date: 2000-01-06
Also published as: AU4340299A

Abstract

The present invention provides a pulse density modulation circuit for digital-to-analog conversion in telecommunication devices. The pulse density modulation circuit includes digital summing circuitry having two m-bit inputs, a m-bit output and a one-bit carry output. The m-bit output provides an n-bit data value to the input of a like number of shift registers. The output of the shift registers are fed back to the first input. The carry output provides a substantially equally spaced pulse stream to filtering circuitry effectively converting the pulse stream into a low ripple, DC value. The number of pulses for any given period appearing at the digital output corresponds to the n-bit input value provided at the second input of the summing circuitry. In other words, the value provided at the second input controls a number of substantially, equally spaced pulses appearing in a given period at the second output.

Description

DIGITAL-TO-ANALOG CONVERTER USING FIRST ORDER SIGMA-DELTA MODULATION

Background of the Invention The present invention relates to digital signal processing and, more particularly, to a system and method for generating a single bit digital signal having substantially, equally spaced pulses from a multi-bit digital signal.

A common problem faced by designers of electronic equipment is the conversion of digital signals to analog signals. Most digital-to-analog converters require special purpose circuitry that is often not available to a digital IC designer. Particularly in the cellular telecommunication industries, baseband circuits are often required to generate analog control voltages for variable gain amplifiers, DC offset compensation circuits, and contrast adjustments for LCD's, just to name a few applications. A simple solution to this problem is the generation of a periodic digital signal with a certain DC component. The signal is then filtered using a low pass filter, which in many applications is a simple RC circuit. As shown in Figure 1 , a typical circuit for performing such a conversion function includes a counter 10 and a comparator 12. In this configuration, the counter 12 is clocked by a clock signal 14 to produce an n-bit counter output value 16, which is provided to the n-bit input B to the comparator 12. An n-bit input value 20 is provided to the other comparator input A. The comparator continuously compares the binary magnitude of the n-bit input value 20 with the binary magnitude of the ever increasing counter value 16 to generate a single bit periodic digital signal 22, which, in effect, is a pulse width modulated (PWM) digital output signal. The duty cycle of this resulting single bit digital signal is proportional to the n-bit input value; hence, the term pulse width modulation is used.

In addition to the application of such a signal within a digital circuit, the single bit digital signal is also commonly used to allow digital circuitry to interface with analog circuitry. In this application, the single bit digital signal output 22 from the comparator 12 is low-pass filtered to create an analog signal 26 using a low-pass filter 24. The purpose of the low-pass filter 24 is to average the discrete levels of the single bit digital signal 22 to produce a constant analog signal output 26. The duty cycle of the single bit digital signal 22 determines the value of the resulting analog signal 26 at the output of the filter 24.

The disadvantage of the PWM single bit digital signal 22 is that, within a single cycle, all like bits arrive consecutively, meaning there is no more than one transition from logic value "1" to logic value "0" and from logic value "0" to logic value "1 " per period. The single rising and falling edge results in the limitation of applications of such a signal within a digital circuit.

If the single bit signal is converted to analog, this disadvantage also adversely affects the analog output signal 26. To keep the analog signal output from increasing during the portion of the PWM period, which is logic value "1," and then decreasing during the portion of the PWM period, which is logic value "0," the low-pass filter selected must have a low cut-off frequency. However, the low cut-off frequency also slows the reaction time of the analog signal output 26 to changes in the value of the input digital signal 20.

The function of the low-pass filter 24 is to cut higher harmonics of the digital waveform applied to its input, thereby reducing as much as possible the ripple at the analog output of the system. The response time of the system, or in other words the bandwidth of the analog output of the circuit, is ultimately determined by the bandwidth of the low-pass filter 24. In an ordinary application, where the low-pass filter 24 is a single pole RC filter, the pole position controls both ripple and maximum update rates of the system. In many of these applications, there is no pole position that satisfies both requirements. The invention disclosed in U.S. Patent No. 5,337,338 to Sutton et al provides a novel attempt at improving the counter and comparator circuitry shown in Figure 1 to overcome the referenced deficiencies in a pulse PWM signal. In an effort to avoid simply having one extended pulse for each period in the PWM output signal 22, Sutton et al. reconfigured the circuit of Figure 1 to provide a single bit output having many transitions between logic values "0" and "1" within a single period. In their improvement, Sutton et al. used the same digital counter 10 and digital comparator 12, but changes the manner in which the counter output 16 is coupled to the comparator input B. The counter output is coupled to the comparator B in a reverse, non-sequential order; wherein the most significant bit (MSB) through the least significant bit (LSB) of the counter output is not connected to the MSB through LSB inputs of the comparator input B, respectively. The advantage of this configuration is that within a single period of the resulting single bit digital output 22, all like bits do not arrive consecutively. This allows the single bit output to have many transitions between logic values "0" and "1" within a single period. Although the invention disclosed in Sutton et al. yields a far lower ripple than the circuitry in Figure 1, many applications require an even lower ripple than any achievable by the Sutton et al. invention. Optimally, within any given period, there will be a given number of pulses corresponding to the n-bit input value. Furthermore, applicants surmise that the lowest ripple values are achieved when these pulses, no matter how many there are, are equally spaced within any given period. Clearly, there is no way to force equal spacing between all pulses within a given period because an odd number of pulses would not fit within a period composed of an even number of cycles. Although the Sutton et al. invention improves ripple, the circuit falls far short from spacing pulses substantially, equally within any given period and throughout consecutive periods. For example, if the n- bit input value is actually 5 bits and the DC voltage to be derived from the n-bit input value ranges from 0 to Vcc, the 5-bit input value will have 32 positions and the output voltage generated will be one of 0, l/32Vcc, 2/32Vcc, 3/32Vcc . . . 31/32Vcc. If T_c is a duration of one clock cycle and the sequence is repeated every 32 clock cycles (2 ), the sequence could look like the one shown in Figure 2(a). Notably, the pulses may be placed anywhere in the frames and the output DC voltage would always be the same. However, the position of the two pulses within a frame influences the ripple on the output analog voltage. To minimize the RMS value of the ripple on the system analog output, the pulses should be spaced as evenly as possible throughout the period or frame. Given the number of pulses, that is the DC value to realize at the output, the overall ripple power in the system digital output is fixed, which can be easily verified applying Parseval's theorem. Spacing the pulses evenly removes power at lower frequencies where the attenuation introduced at the low-pass filter is less, yielding a lower RMS value of ripple on the system analog output. Since the frame duration for a 5-bit system is 32 clock cycles or 32 x T_c, for two pulses, exact spacing is possible if a pulse is placed every 16 clock pulses as shown in Figure 2(b). The Sutton et al. invention described in U.S. Patent No. 5,337,338 provides such a result for any power of two. The Sutton et al. system fails when an odd number of pulses is required. Figure 2(c) shows the next sequence generated by the Sutton et al. invention: the two pulses of Figure 2(b) are "left" in the same position, and a third one is placed halfway therebetween. This sequence is not ideal and provides excessive ripple as compared to an optimal spacing shown in Figure 2(d). Although the pulses in Figure 2(d) are not exactly equally spaced, since 32 is not divisible by three, this sequence is a very close approximation to an ideal spacing. The optimal spacing for three pulses in a 32-cycle period results in the space between the first pulse and the second, and the second and third to be ten clock cycles, and the spacing between the third and first pulse of the next frame to be nine clock cycles.

Thus, there is a need for an inexpensive and reliable pulse density modulation system and method to substantially, equally space pulses throughout a reoccurring period from a one-bit digital output. There is a need to provide a low ripple DC voltage corresponding to an n-bit digital input value improving upon known circuitry and methods of like digital-to-analog conversion in the telecommunications environment.

Summary of the Invention

Applicant's invention overcomes the drawbacks of the prior art disclosed using simple circuitry capable of providing optimal pulse sequencing and spacing during a given period wherein the number of pulses in the period is equal to an n-bit digital value and the pulses are substantially, equally spaced during the period and over consecutive periods as desired.

Accordingly, the present invention provides a pulse density modulation circuit for digital-to-analog conversion in telecommunication devices. The pulse density modulation circuit includes digital summing circuitry having two inputs and two outputs. The first output provides an n-bit data value to the input of a like number of shift registers. The output of the shift registers are fed to the first input. The second output provides the substantially, equally spaced pulse stream to filtering circuitry effectively converting the pulse stream into a low ripple, DC value. The number of pulses for any given period appearing at the digital output corresponds to the n-bit input value provided at the second input of the summing circuitry. In other words, the value provided at the second input controls a number of substantially, equally spaced pulses appearing in a given period at the second output.

Preferably, the summing circuitry is configured to sum the values at the two inputs and 1) if the sum is less than 2", provide the sum to the data output and a logic zero to the overflow output, or 2) if the sum is greater than 2ⁿ, provide the data output with the remainder of the sum divided by 2ⁿ and a logic one to the overflow output. As the summing circuitry and registers cycle through the summing operations, the overflow output provides a stream of pulses configured wherein the number of pulses in any one period or frame is equal to the n-bit input value. The resulting analog output at the output of the low-pass filter will directly correspond to the n-bit input value.

The various aspects of the present invention will become apparent to those skilled in the art after a reading of the following description of the preferred embodiment when considered with the drawings.

Brief Description of the Drawings

FIGURE 1 is a schematic of a pulse width modulation circuit of the prior art;

FIGURES 2A-2D are a series of pulse sequences corresponding to the prior art and the present invention;

FIGURE 3 is a schematic of a preferred embodiment of the present invention; FIGURE 4A is a chart showing the ripple obtained for the 75^th level in an 8-bit system configured according to the present invention; and

FIGURE 4B is a chart showing the ripple obtained for the 75^th level in an 8-bit system configured according to the prior art embodiment disclosed in U.S. Patent No. 5,337,338. Description of the Preferred Embodiments The features, objects, and advantages of the present invention will become more apparent from the following description and the accompanying drawings. In the following description, like reference characters designate like or corresponding parts throughout the several views.

The preferred embodiment of the present invention is shown in Figure 3, wherein an adder or summing circuit 102, a delay circuit 104 and a low-pass filter 106 cooperate to convert an n-bit input value 16 from a control system 26 to a substantially, equally spaced digital output 112. The digital output 112 is filtered by the low-pass filter 106 to provide a low ripple analog output 114 level corresponding to the n-bit input value 16. The summing circuitry 102 includes two inputs A, B, a data output C, and an overflow output D, providing the digital output 112. The data output C preferably provides either the summation of the values at inputs A, B or the remainder of the summation value divided by the period -2ⁿ. Preferably, the n-bit value provided by the data output C is fed to the input of the delay circuit 104 via an n-bit databus 108. The delay circuit 104 may, for example, comprise an n-bit shift register. The purpose of the delay circuit 104 is to delay data output C by one clock cycle. The output of the delay circuit 104 is provided to the input A of the overflow circuit 102 via an n-bit databus 110. Thus, the data output C of the summing circuitry is fed back to input A of the summing circuitry wherein the output of one summing function at data output C is used by the summing circuitry at input A for a subsequent summing operation. Preferably, a system clock signal is provided to the shift registers 104 in the summing circuitry 116 to control the summing operations, shift registers 104 and the digital output 112. The summing circuitry is preferably configured to sum integer numbers appearing at inputs A, B and provide data output C and overflow output D as follows, wherein a, b represent the n-bit values provided to inputs A, B of the summing circuitry: if {(a+b)<N} then {data output at C = a+b and overflow output D = logic low}; and if {(a+b)>N} then {data output at C = Re[(a+b)/N] and overflow output D = logic high} .

Re[(a+b)/N] is the remainder of the division of (a+b)/N.

N is the set value where overflow occurs. In other words, if the sum of the values at inputs A, B are in excess of the set value, an overflow condition occurs. Preferably, N = 2" where n is the number of bits. Where n equals the number of bits in the system, and the n- bit input value 16 is applied to input A of the summing circuitry 102, an equal number of pulses is substantially, equally spaced in a frame or period equal to 2ⁿ cycles. This digital output 112 is filtered by the low-pass filter 106 to provide a DC value at the analog output 114 proportional to the n-bit digital value 16. Preferably, the data output C is delayed by one clock period and fed back to the adder input A. Every time an overflow occurs, the overflow output D provides a logic high for one clock period.

In a 5-bit system, the overflow value N is equal to 32 (2⁵). Thus, every time the sum of values appearing at inputs A, B exceed 32, the overflow output D goes high for one clock cycle. When the summation of inputs A, B are less than 32, the data output C provides the summation value and the overflow output D provides a logic zero for the corresponding clock cycle. The following table outlines a complete frame or period when the n-bit input value 16 has a value of 3 in a 5-bit system.

Input value = 3, Adder modulus = 32

As seen from the table, the pulse sequence for the overflow output D, which provides the digital output 112, is equal to the optimal sequence depicted in Figure 2(d). The preferred embodiment of the present invention has the following properties:

1) the number of pulses in a frame or period at the digital output equals the n-bit input value 16 provided at input B of the summing circuitry 102;

2) the digital output signal 112 provided at the overflow output D is periodic with a period no greater than N clock cycles (one period or frame duration) wherein N = 2ⁿ (N being the number of bits for the input value 16); and

3) if P is equal to the n-bit input value 16 and M is the integer part of the ratio N/P, the spacing between any two pulses in the sequence is either M or M-l . In the ι rv example above, N = 32, P = 3, M = 10, such that any two pulses in the digital output sequence 112 is either 10 or 9 cycles.

The first two properties assure that the difference between one DC value and the following value is always the same for any value of the input value 16 - a constant step property, and the third property ensures that the pulses in any sequence are substantially, equally spaced.

As mentioned above, the present invention substantially reduces the amount of ripple in the resulting analog output voltages 114. Figure 4(a) and Figure 4(b) show the ripple obtained for the 75^th level in an 8-bit system for the present invention and that disclosed in U.S. Patent No. 5,337,338, respectively. To obtain these results, a clock frequency of 1 megahertz along with a single pole low-pass filter with a 3 dB corner frequency of 1.6 kilohertz was used in both cases. In both tests, the digital wave form and the digital output of the system swings between 0 and 1 volts; however, the ripple RMS for the present invention is only 2.5 millivolts while that of the prior art was 4.6 millivolts. The "update" time for both systems is basically the same. Notably, the present invention and that of Sutton et al. provide the same result for any powers of 2 but, in any other case, the ripple RMS voltage obtained by the present invention is always significantly lower than the one obtained using the prior art, wherein the differences are most significant in the middle of the analog output range.

As far as implementation of the apparatus and method are concerned, the sequential machine in Figure 3 can be, but does not have to be, a digital circuit. The system may be implemented in software as long as proper timing is maintained. Each cycle and period should be the same to provide optimal ripple rejection. In a digital circuit implementation, the delay circuit 104 labeled "Z^"1" may be standard shift registers or flip-flops, as well as other delay circuits known to those skilled in the art. There are simple variations of the method in Figure 3 that generate the same result. For instance, one can simply take the complement to N of the input value and negate the system digital output and obtain a sequence equivalent to the one generated by the circuit in Figure 3. The complement to N of the number is N minus that number. Ripple may be further reduced using higher order low-pass filters instead of the single pole low-pass filter described above. Such variations and modifications are considered within the scope of this disclosure and the following claims. The preferred embodiment is provided to enable those skilled in the art to make or use the present invention. As noted, various modifications to these embodiments will be readily apparent to those skilled in the art, and the basic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

We Claim:

1. A pulse density modulation circuit for telecommunication devices comprising: a. digital summing circuitry having an n-bit first digital input, n-bit second digital input, n-bit first digital output and second output, said summing circuitry adapted to cyclically: i. sum values at said first and second inputs, and ii. if said sum is less than 2 to the nth power, provide said sum to said first output and a first binary logic state to said second output, and iii. if said sum is greater than or equal to 2 to the nth power, provide said first output with the remainder of the sum divided by 2 to the nth power and a second binary state to said second output; and b. n registers coupled between said first digital output and said first digital input to provide n-bit values at said first digital output to said first digital input for a subsequent cycle; c. wherein when an n-bit value is provided at said second digital input, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to

2 to the nth power.

2. The pulse density modulation circuit of claim 1 further including filter circuitry coupled to said second digital output for filtering the equally spaced pulses to provide a resultant analog output signal proportional to the n-bit value provided at said second digital input.

3. The pulse density modulation circuit of claim 1 wherein said n registers and said summing circuitry includes a clock input, said clock input for said n registers effecting a shift of said n-bit values at said first digital output to said first digital input and said clock input for said summing circuitry causing said summing circuitry to sum said values at said first and second inputs and provide said first and second outputs.

4. The pulse density modulation circuit of claim 1 wherein each pulse has a width equal to one divided by 2 to the nth power.

5. A pulse density modulation circuit for telecommunication devices adapted to cyclically: a. sum an n-bit first digital value and an n-bit second digital value, b. if said sum is less than 2 to the nth power, provide a digital result having a value equal to the sum and an output signal equal to a first binary logic state at an output, or c. if the sum is greater than or equal to 2 to the nth power, provide said digital result having a value equal to the remainder of the sum divided by 2 to the nth power and a second binary logic state to said output; and d. assign said n-bit second digital value to said digital result for a subsequent cycle; e. wherein when an n-bit value is provided for said second digital value, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to 2 to the nth power.

6. The pulse density modulation circuit of claim 1 further including filter circuitry configured to receive consecutive logic states at said output for filtering the equally spaced pulses to provide a resultant analog output signal proportional to the n-bit second digital value.

7. A pulse density modulation circuit for telecommunication devices comprising: a. means for cyclically summing values at first and second n-bit inputs; b. means to provide said sum to a first n-bit output and a first binary logic state to a second output, if said sum is less than 2 to the nth power; c. means to provide said first output with the remainder of the sum divided by 2 to the nth power and a second binary state to said second output, if said sum is greater than or equal to 2 to the nth power and d. means to cyclically provide a delayed feedback between said first digital output and said first digital input to provide n-bit values at said first digital output to said first digital input for a subsequent cycle; e. wherein when an n-bit value is provided at said second digital input, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to 2 to the nth power.

8. The pulse density modulation circuit of claim 7 further including control means for providing the n-bit value to said second digital input.

9. The pulse density modulation circuit of claim 7 further including filter means coupled to said second digital output for filtering the equally spaced pulses to provide a resultant analog output signal proportional to the n-bit value provided at said second digital input.

10. A pulse density modulation circuit for telecommunication devices comprising: a. digital summing circuitry having an n-bit first digital input, n-bit second digital input, n-bit first digital output and second output, said summing circuitry adapted to cyclically: i. sum values at said first and second inputs, and ii. if said sum is less than 2 to the nth power, provide said sum to said first output and a first binary logic state to said second output, and iii. if said sum is greater than or equal to 2 to the nth power, provide said first output with the remainder of the sum divided by 2 to the nth power and a second binary state to said second output; and b. n registers coupled between said first digital output and said first digital input to provide n-bit values at said first digital output to said first digital input for a subsequent cycle; c. a control system configured to provide an n-bit control value to said n-bit second digital input; d. wherein when an n-bit control value is provided at said second digital input, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to 2 to the nth power.

11. The pulse density modulation circuit of claim 9 further including filter circuitry coupled to said second digital output for filtering the equally spaced pulses to provide a resultant analog output signal proportional to the n-bit control value provided at said second digital input.

12. A telecommunication device having improved pulse density modulation circuitry for providing analog control voltages from digital control values, said device comprising: a. a modulo-N adder adapted to sum integer numbers at first and second n-bit inputs and provide an n-bit parallel data output and a single bit overflow output, said adder further adapted to: i. provide said sum to a data output and a first binary logic state to a second output, if said sum is less than 2 to the nth power, and ii. provide said data output with the remainder of the sum divided by 2 to the nth power and a second binary state to said overflow output, if said sum is greater than or equal to 2 to the nth power; b. n parallel shift registers coupled between said first digital output and said first digital input to provide n-bit values at said data output to said first n-bit input for a subsequent cycle; c. a control system configured to provide an n-bit control value to said n-bit second digital input; and d. filter circuitry coupled to said overflow output; e. wherein when an n-bit control value is provided at said second digital input, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to 2 to the nth power and said filter circuit filters the equally spaced pulses to provide a resultant analog control output signal proportional to the n-bit control value provided at said second n-bit input.

13. A method for pulse density modulation in telecommunication devices comprising: a. cyclically summing values at first and second n-bit inputs to provide a sum; b. providing said sum to a first n-bit output and a first binary logic state to a second output, if said sum is less than 2 to the nth power; c. providing said first output with the remainder of the sum divided by 2 to the nth power and a second binary state to said second output, if said sum is greater than or equal to 2 to the nth power; and d. cyclically providing a delayed feedback between said first digital output and said first digital input to provide n-bit values at said first digital output to said first digital input for a subsequent cycle; e. wherein when an n-bit value is provided at said second digital input, a corresponding number of substantially, equally spaced pulses are provided at said second digital output within a period having a number of cycles equal to 2 to the nth power.

14. The method of claim 13 further including providing the n-bit value to said second digital input.

15. The method of claim 13 further including filtering the equally spaced pulses to provide a resultant analog output signal proportional to the n-bit value provided at said second digital input.

16. A pulse density modulation circuit for telecommunication devices comprising: a. digital summing circuitry having an n-bit first digital input, n-bit second digital input, n-bit data output and an overflow output, said summing circuitry providing a binary output signal during a cycle; b. an n-bit register coupled between said data output and said first digital input to provide n-bit values at said first digital output to said first digital input for a subsequent cycle upon receiving a clock signal; and c. said summing circuitry configured to provide a number of pulses equal to an n-bit input value provided at said second digital input during a set number of cycles wherein the pulses are spaced substantially, equally apart.

17. The pulse density modulation circuit of claim 16 wherein, for each cycle, said summing circuitry is adapted to: a. sum the n-bit values at said first and second n-bit digital inputs, and b. upon a first result, provide said sum to said data output and a first binary logic state at said overflow output, and c. upon a second result, provide said data output with the remainder of the sum divided by the set period of cycles at said overflow output.

18. The pulse density modulation circuit of claim 16 wherein, for each cycle, said summing circuitry is adapted to: a. sum the n-bit values at said first and second n-bit digital inputs, and b. if said sum is less than 2 to the nth power, provide said sum to said data output and a first binary logic state at said overflow output, and c. if said sum is greater than or equal to 2 to the nth power, provide said data output with the remainder of the sum divided by 2 to the nth power and a second binary state at said overflow output.

19. The pulse density modulation circuit of claim 16 wherein said pulses are one cycle in duration

20. The pulse density modulation circuit of claim 16 wherein the set number of cycles is equal to 2 to the nth power.

21. The pulse density modulation circuit of claim 16 wherein spacing between any two pulses is either the integer part of said set number of cycles divided by the n-bit value or one cycle less than the integer part of said set number of cycles divided by the n-bit input value.

22. The pulse density modulation circuit of claim 16 wherein said pulses are one cycle in duration, the set number of cycles is equal to 2 to the nth power, and the spacing between any two pulses is either the integer part of said set number of cycles divided by the n-bit value or one cycle less than the integer part of said set number of cycles divided by the n-bit input value.