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WO1999026289A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO1999026289A1
WO1999026289A1 PCT/JP1998/000813 JP9800813W WO9926289A1 WO 1999026289 A1 WO1999026289 A1 WO 1999026289A1 JP 9800813 W JP9800813 W JP 9800813W WO 9926289 A1 WO9926289 A1 WO 9926289A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
memory
substrate
semiconductor
chips
Prior art date
Application number
PCT/JP1998/000813
Other languages
French (fr)
Japanese (ja)
Inventor
Kouichi Ikeda
Takeshi Ikeda
Original Assignee
T.I.F. Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by T.I.F. Co., Ltd. filed Critical T.I.F. Co., Ltd.
Publication of WO1999026289A1 publication Critical patent/WO1999026289A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Definitions

  • the present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method for manufacturing the same.
  • a multi-chip module is formed by mounting a plurality of semiconductor chips on a substrate.
  • the semiconductor chip mounted on the packaged semiconductor chip module board is subjected to a pass / fail inspection in units of one or a plurality of units.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of improving the efficiency of a semiconductor chip quality test and a method of manufacturing the same.
  • a semiconductor device is provided by mounting a plurality of semiconductor chips (preferably memory chips) on a substrate, performing a quality inspection of each semiconductor chip in a resin-sealed state, and then dividing the semiconductor chip into a predetermined number of units. Is formed. Since the quality inspection of semiconductor chips is performed on a substrate basis, the efficiency of inspection can be increased as compared with the case where one or a small number of semiconductor chips are individually inspected.
  • a plurality of semiconductor chips are mounted on one surface of the substrate, and the quality of each semiconductor chip is inspected via terminals formed on the other surface.
  • the entire board is treated as one component, and multiple semiconductors mounted on it are handled. Since the quality of semiconductor chips can be inspected, the quality of the semiconductor chips can be compared with the quality of semiconductor chips individually packaged or the semiconductor substrate on which multiple semiconductor chips are mounted. The required labor can be reduced.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment
  • FIG. 2 is a view showing a partial structure of the substrate before the memory bay chip is mounted.
  • FIG. 3 is a view showing a state where the memory bay chip is mounted on the board shown in FIG. 2.
  • FIG. 4 is a view showing the results of a pass / fail inspection of the memory bay chip mounted on the board
  • FIG. 5 is a view showing a connection state between the memory bay chip and the board in the case of flip chip mounting
  • FIG. 6 is a diagram showing a cross section of a memory bare chip having a CIB structure and a substrate
  • FIG. 7 is a diagram illustrating an outline of resin molding by transfer molding
  • FIG. 8 is using an LCC type external connection terminal Figure showing the partial structure of the memory module in the case
  • FIG. 9 is a diagram for explaining a process of forming the external connection terminals when using the LCC type external connection terminals.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment.
  • the memory module 10 as a semiconductor device includes a memory bare chip (memory chip) 1 cut out from a semiconductor wafer, a substrate 2 on which the memory bare chip 1 is mounted, and a substrate. And a resin 3 for sealing the surface on which the memory chip 2 is mounted.
  • a substrate 2 is introduced, and a plurality of memory bare chips 1 are arranged on one side of the substrate 2 at predetermined intervals vertically and horizontally. (1st step).
  • COB Chip On Board
  • FIG. 2 is a diagram showing a partial structure of the substrate 2 before the memory bay chip 1 is mounted.
  • 1A shows the surface on which the memory carrier 1 is mounted
  • FIG. 2B shows the opposite surface (back surface)
  • FIG. 1C shows the structure viewed from the side.
  • the board 2 is provided with a board pad 11 necessary for making an electrical connection with the memory bare chip 1 for each predetermined area where the memory bear chip 1 is mounted.
  • the substrate pad 11 is electrically connected to a BGA (Ball Grid Array) pad 13 on the rear side through a through hole 12.
  • BGA All Grid Array
  • FIG. 3 is a view showing a state in which the memory bare chip 1 is mounted on the substrate 2 shown in FIG. 2 in the first step.
  • FIG. 3 (a) shows the mounting surface of the memory bear chip 1
  • FIG. 3 (b) shows the structure viewed from the side.
  • Each memory tape 1 is a DRAM having a capacity of, for example, 16 M ⁇ 4 bits, and a chip pad 14 is formed on the surface thereof in a line in the center along the long side. Have been.
  • the chip pads 14 are connected to the substrate pads 11 formed on the substrate 2 by using bonding wires 15. COB mounting using such bonding wires 15 is performed on each memory chip 1.
  • the resin 3 is poured into the surface of the substrate 2 on which the memory bare chip 1 is mounted, as shown in FIG.
  • the memory chip 1 is sealed with the resin 3 (second step).
  • each memory bear chip 1 is sealed with the resin 3 to prevent disconnection and short circuit of the bonding wires 15 connected to the memory bear chip 1.
  • the resin 3 has a predetermined thickness, variations in the height of the manufactured memory module 10 are suppressed.
  • a pass / fail inspection of each memory bare 1 is performed (third step). For example, by pressing an inspection probe against a BGA pad 13 formed on the back surface of the substrate 2 to make electrical contact therewith, Perform some functional tests.
  • the pass / fail inspection of the memory bay chip 1 as a unit of the entire board 2, that is, by conducting pass / fail inspection of a plurality of memory bays 1 mounted on the board 2 at one time, Improving efficiency.
  • FIG. 4 is a diagram showing the results of a pass / fail inspection (third step) of the memory bare chip 1 mounted on the substrate 2, where a mark ⁇ indicates a memory bare chip 1 determined to be non-defective, and a mark X indicates non-defective. Each of the bare chips 1 for memory that have been determined to be non-defective is shown.
  • a plurality of memory bare chips 1 mounted on the substrate 2 are collectively inspected, and a matrix-like inspection result indicating the quality of the inspection is obtained.
  • defective products are removed from the separated memory modules 10 and only non-defective products are taken out.
  • the pass / fail inspection of a plurality of memory bare chips 1 mounted on the board 2 is performed collectively for the entire board 2 as a unit. Inspection efficiency can be increased as compared with the case where quality inspection is performed.
  • memory bare chips can be cut in units of one or more (two or four). -Can be manufactured efficiently.
  • FIG. 5 is a diagram showing a connection state between the bare memory chip 1 and the substrate 2 in the case of flip-chip mounting.
  • the board pads formed on the mounting surface of the memory bare chip 1 and the chip pads formed on the surface of the board 2 on which the memory bare chip 1 is mounted face each other and are connected by bumps 21.
  • flip chip mounting is performed. According to the flip-chip mounting, further high-density mounting is possible, so that the outer dimensions of the manufactured memory module 10 are further reduced. It becomes possible to cut.
  • DRAMs and other semiconductor chips will have shorter wiring lengths because of their higher operating speeds, but shorter wiring lengths will be realized by adopting flip mounting. Can be.
  • each bare chip 1 for memory may be housed in the substrate 2 to have a CIB (Chip In Board) structure in which the bonding wires 15 and the like are not exposed to the outside.
  • FIG. 6 is a diagram showing a cross section of a memory bear chip 1 having a CIB structure and a substrate 2. As shown in the figure, a concave portion is formed in the substrate 2, a memory chip 1 is mounted inside the concave portion, and the substrate pad 11 and the chip pad 14 are substantially flush with each other.
  • FIG. 7 is a view for explaining resin molding by transfer molding.
  • FIG. 7 (a) shows a case where flat resin molding is performed on the entire substrate 2, and
  • FIG. ) Shows a case in which a groove is provided along a dividing line.
  • Transfer molding resin molding is suitable for mass production because the molding time can be shortened.
  • the BGA pad 13 is used as the external connection terminal of the memory module 10.
  • a so-called LCC (Leadless Chip Carrier) type terminal may be used.
  • FIG. 8 is a diagram showing a partial structure of the memory module 10 when an external connection terminal of the LCC system is used. As shown in the figure, a concave portion is formed in one side (or in both directions) of the longitudinal direction or the horizontal direction on the side surface of the memory module or the module 10 after the separation, and the surface of the concave portion is formed. Metal cover to cover As a result, the external connection terminal 31 is formed.
  • FIG. 9 is a view for explaining a process of forming the external connection terminal 31 of the LCC system.
  • the substrate 2a has through holes 3 along one or both of the dividing lines for separating the mounted memory bare chip 1 in the vertical or horizontal direction. 2 are formed.
  • the external connection terminals 31 may be clogged by the poured resin 3 during the resin sealing in the second manufacturing process described above. May occur. Therefore, as shown in FIG. 3B, a protective member such as an insulating tape 33 is formed along the through hole 32 to prevent the resin 3 from flowing into the through hole 32. .
  • solder or the like may be poured into each through hole 32 in advance so that clogging with the resin does not occur later. Thereafter, the above-described through-hole 32 is cut at the center thereof to form the external connection terminal 31 shown in FIG.
  • a flexible substrate or other various substrates may be used as the substrate 2 used in the above-described embodiment.
  • a case where a memory chip is used as a semiconductor chip and a memory module as a semiconductor device is manufactured has been described as an example.
  • various types of semiconductor chips other than the memory chip such as a processor chip and an ASIC, may be used. It can be applied when mounting a chip on a substrate.
  • the memory bare chips 1 to be separated from the substrate 2 may not be separated one by one, but may be separated into two or more predetermined chips.
  • the quality of semiconductor chips is inspected in units of the entire board on which a plurality of semiconductor chips are mounted, so that one or a small number of semiconductor chips are individually inspected. Inspection efficiency can be increased as compared with the above.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor device which can improve the efficiency of quality inspections performed on each semiconductor chip and a method for manufacturing the semiconductor device. A plurality of identical bare chips (1) for memory is COB-mounted on a substrate (2) and the surface of the substrate (2) mounted with the chips (1) is sealed with a resin (3). After the chips (1) mounted on the substrate (2) are inspected at once for quality, each memory module (10) is cut and divided.

Description

明 細 書 半導体装置およびその製造方法 技術分野  Description Semiconductor device and method for manufacturing the same
本発明は、 メモリ基板やマザ一ボード等に実装可能な半導体装置およびその製 造方法に関する。 背景技術  The present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method for manufacturing the same. Background art
従来の半導体チップは、 パッケージングされた状態で組み付けられる。 また、 複数の半導体チップを基板上に実装してマルチチップモジュールを構成する場合 もある。 このようにパヅケ一ジングされた半導体チヅプゃモジユール基板に実装 された半導体チップは、 1あるいは複数個を単位として良否検査が行われるが、 検査する半導体チップの数が多い場合に、 検査する単位となる半導体チップの数 が少ないと、 それだけ検査効率が低下することになるため、 検査効率を上げるこ とができる手法が望まれている。 発明の開示  Conventional semiconductor chips are assembled in a packaged state. In some cases, a multi-chip module is formed by mounting a plurality of semiconductor chips on a substrate. The semiconductor chip mounted on the packaged semiconductor chip module board is subjected to a pass / fail inspection in units of one or a plurality of units. The smaller the number of semiconductor chips, the lower the inspection efficiency. Therefore, a method that can increase the inspection efficiency is desired. Disclosure of the invention
本発明は、 このような点に鑑みて創作されたものであり、 その目的は、 半導体 チップの良否検査の効率を上げることができる半導体装置およびその製造方法を 提供することにある。  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of improving the efficiency of a semiconductor chip quality test and a method of manufacturing the same.
本発明では、 基板上に複数の半導体チップ （好ましくはメモリチップ） を実装 して樹脂封止した状態で各半導体チップの良否検査を行った後に所定個数を単位 として半導体チップを切り分けることにより半導体装置が形成される。 半導体チ ップの良否検査を、 基板を単位として行うため、 1あるいは少数個の半導体チッ プを個別に検査する場合に比べて、 検査の効率を上げることができる。  According to the present invention, a semiconductor device is provided by mounting a plurality of semiconductor chips (preferably memory chips) on a substrate, performing a quality inspection of each semiconductor chip in a resin-sealed state, and then dividing the semiconductor chip into a predetermined number of units. Is formed. Since the quality inspection of semiconductor chips is performed on a substrate basis, the efficiency of inspection can be increased as compared with the case where one or a small number of semiconductor chips are individually inspected.
特に、 基板の一方の面に複数の半導体チップを実装し、 他方の面に形成さ Λた 端子を介して各半導体チップの良否検査を行うことが好ましい。 この場合には、 In particular, it is preferable that a plurality of semiconductor chips are mounted on one surface of the substrate, and the quality of each semiconductor chip is inspected via terminals formed on the other surface. In this case,
1枚の基板の全体を一つの部品として取り扱って、 これに実装される複数の半導 体チップの良否検査を行うことができるため、 個別にパッケージングされた半導 体チップや複数個の半導体チップが実装された半導体基板を単位として良否検査 を行う場合などに比べて、 良否検査に要する手間を低減することができる。 図面の簡単な説明 The entire board is treated as one component, and multiple semiconductors mounted on it are handled. Since the quality of semiconductor chips can be inspected, the quality of the semiconductor chips can be compared with the quality of semiconductor chips individually packaged or the semiconductor substrate on which multiple semiconductor chips are mounted. The required labor can be reduced. BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 本実施形態のメモリモジュールの製造工程を示す図、  FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment,
第 2図は、 メモリ用べァチップが実装される前の基板の部分的な構造を示す図 第 3図は、 第 2図に示す基板上にメモリ用べァチップが実装された状態を示す 図、  FIG. 2 is a view showing a partial structure of the substrate before the memory bay chip is mounted. FIG. 3 is a view showing a state where the memory bay chip is mounted on the board shown in FIG. 2.
第 4図は、 基板に実装されたメモリ用べァチップの良否検査の結果を示す図、 第 5図は、 フリップチップ実装の場合のメモリ用べァチップと基板の接続状態 を示す図、  FIG. 4 is a view showing the results of a pass / fail inspection of the memory bay chip mounted on the board, FIG. 5 is a view showing a connection state between the memory bay chip and the board in the case of flip chip mounting,
第 6図は、 C I B構造を有するメモリ用ベアチップと基板の断面を示す図、 第 7図は、 トランスファーモールドによる樹脂成形の概要を説明する図、 第 8図は、 L C C方式の外部接続端子を用いる場合のメモリモジュールの部分 的な構造を示す図、  FIG. 6 is a diagram showing a cross section of a memory bare chip having a CIB structure and a substrate, FIG. 7 is a diagram illustrating an outline of resin molding by transfer molding, and FIG. 8 is using an LCC type external connection terminal Figure showing the partial structure of the memory module in the case
第 9図は、 L C C方式の外部接続端子を用いる場合の外部接続端子の形成過程 を説明する図である。 発明を実施するための最良の形態  FIG. 9 is a diagram for explaining a process of forming the external connection terminals when using the LCC type external connection terminals. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明を適用した一実施形態のメモリモジュールについて、 図面を参照 しながら具体的に説明する。 第 1図は、 本実施形態のメモリモジュールの製造ェ 程を示す図である。 同図 （d ) に示すように、 半導体装置としてのメモリモジュ —ル 1 0は、 半導体ウェハから切り出されたメモリ用ベアチップ （メモリチヅプ ) 1と、 メモリ用ベアチップ 1が実装される基板 2と、 基板 2のメモリ用べァチ ップ 1が実装された面を封止する樹脂 3とを含んで構成されている。 ― まず、 第 1図 （a ) および （b ) に示すように、 基板 2を導入し、 この基板 2 上に複数のメモリ用ベアチップ 1を一方の面上に縦横それそれ所定間隔に配置し て実装する （第 1の工程） 。 各メモリ用ベアチヅプ 1の実装方法としては、 例え ば C O B (Chip On Board ) 実装が用いられる。 Hereinafter, a memory module according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment. As shown in FIG. 1D, the memory module 10 as a semiconductor device includes a memory bare chip (memory chip) 1 cut out from a semiconductor wafer, a substrate 2 on which the memory bare chip 1 is mounted, and a substrate. And a resin 3 for sealing the surface on which the memory chip 2 is mounted. -First, as shown in Fig. 1 (a) and (b), a substrate 2 is introduced, and a plurality of memory bare chips 1 are arranged on one side of the substrate 2 at predetermined intervals vertically and horizontally. (1st step). As a mounting method of each memory chip 1, for example, COB (Chip On Board) mounting is used.
第 2図は、 メモリ用べァチップ 1が実装される前の基板 2の部分的な構造を示 す図である。 同図 （a ) はメモリ用ベアチヅブ 1が実装される側の面を、 同図 （ b ) は反対側の面 （裏面） を、 同図 （c ) は側面から見た構造をそれぞれ示して いる。 これらの図に示すように、 基板 2は、 メモリ用ベアチヅプ 1が実装される 所定領域ごとに、 メモリ用ベアチップ 1との間で電気的な接続を行うために必要 な基板用パッ ド 1 1が形成されており、 さらにこの基板用パッド 1 1がスルーホ —ル 1 2を介して裏側の B G A (Bal l Grid Array ) 用パヅド 1 3と電気的に接 続されている。  FIG. 2 is a diagram showing a partial structure of the substrate 2 before the memory bay chip 1 is mounted. 1A shows the surface on which the memory carrier 1 is mounted, FIG. 2B shows the opposite surface (back surface), and FIG. 1C shows the structure viewed from the side. . As shown in these figures, the board 2 is provided with a board pad 11 necessary for making an electrical connection with the memory bare chip 1 for each predetermined area where the memory bear chip 1 is mounted. Further, the substrate pad 11 is electrically connected to a BGA (Ball Grid Array) pad 13 on the rear side through a through hole 12.
第 3図は、 第 2図に示す基板 2上に第 1の工程においてメモリ用ベアチップ 1 が実装された状態を示す図である。 第 3図 （a ) はメモリ用ベアチヅプ 1の実装 面を、 同図 （b ) は側面から見た構造をそれぞれ示している。 各メモリ用べァチ ヅプ 1は、 例えば 1 6 M x 4ビヅ トの容量を有する D R A Mであり、 その表面に は長辺に沿って中央に一列にチヅプ用パヅ ド 1 4が形成されている。 このチヅプ 用パッド 1 4は、 基板 2上に形成された基板用パッド 1 1とボンディングワイヤ 1 5を用いて接続される。 各メモリ用ベアチヅプ 1についてこのようなボンディ ングワイヤ 1 5を用いた C O B実装が行われる。  FIG. 3 is a view showing a state in which the memory bare chip 1 is mounted on the substrate 2 shown in FIG. 2 in the first step. FIG. 3 (a) shows the mounting surface of the memory bear chip 1, and FIG. 3 (b) shows the structure viewed from the side. Each memory tape 1 is a DRAM having a capacity of, for example, 16 M × 4 bits, and a chip pad 14 is formed on the surface thereof in a line in the center along the long side. Have been. The chip pads 14 are connected to the substrate pads 11 formed on the substrate 2 by using bonding wires 15. COB mounting using such bonding wires 15 is performed on each memory chip 1.
上述した第 1の工程においてメモリ用ベアチップ 1を基板 2に実装した後、 第 1図 （c ) に示すように、 基板 2のメモリ用ベアチヅプ 1が実装された面に樹脂 3を流し込み、 所定厚の樹脂 3で各メモリ用ベアチヅプ 1を封止する （第 2のェ 程） 。  After the memory bare chip 1 is mounted on the substrate 2 in the first step described above, the resin 3 is poured into the surface of the substrate 2 on which the memory bare chip 1 is mounted, as shown in FIG. The memory chip 1 is sealed with the resin 3 (second step).
第 2の工程において樹脂 3で各メモリ用ベアチヅプ 1を封止することによって 、 メモリ用ベアチヅプ 1に接続されたボンディングワイヤ 1 5の断線や短絡の防 止を図っている。 また、 樹脂 3を所定厚とすることによって、 製造されるメモリ モジュール 1 0の高さのばらつきを抑えている。  In the second step, each memory bear chip 1 is sealed with the resin 3 to prevent disconnection and short circuit of the bonding wires 15 connected to the memory bear chip 1. In addition, by making the resin 3 have a predetermined thickness, variations in the height of the manufactured memory module 10 are suppressed.
次に、 このようにして樹脂 3による封止が行われた状態で各メモリ用ベア ヅ プ 1の良否検査を行う （第 3の工程） 。 例えば、 基板 2の裏面に形成された B G A用パッド 1 3に検査用プローブを押圧して電気的に接触させることにより、 各 種の機能試験を実施する。 メモリ用べァチップ 1の良否検査を基板 2の全体を単 位として行うことにより、 すなわち、 基板 2に実装された複数のメモリ用べァチ ップ 1の良否検査を一度に行うことにより、 検査効率の向上を図っている。 Next, in the state where the sealing with the resin 3 is performed as described above, a pass / fail inspection of each memory bare 1 is performed (third step). For example, by pressing an inspection probe against a BGA pad 13 formed on the back surface of the substrate 2 to make electrical contact therewith, Perform some functional tests. By performing the pass / fail inspection of the memory bay chip 1 as a unit of the entire board 2, that is, by conducting pass / fail inspection of a plurality of memory bays 1 mounted on the board 2 at one time, Improving efficiency.
次に、 第 3の工程における良否検査の結果に基づいて、 第 1図 （d ) に示すよ うに、 良品と判定されたメモリ用ベアチップ 1を 1個 （あるいは所定の複数個） 切り分けることにより、 メモリモジュール 1 0を完成させる （第 4の工程） 。 第 4図は、 基板 2に実装されたメモリ用ベアチップ 1の良否検査 （第 3の工程 ) の結果を示す図であり、 〇印は良品と判定されたメモリ用ベアチップ 1を、 X 印は不良品と判定されたメモリ用ベアチップ 1をそれそれ示している。 基板 2に 実装された複数のメモリ用ベアチップ 1をまとめて検査して、 その良否を示すマ トリクス状の検査結果が得られる。 第 4の工程では、 切り分けたメモリモジユー ル 1 0の中から不良品を取り除き、 良品のみを取り出す。  Next, based on the results of the pass / fail inspection in the third step, as shown in FIG. 1 (d), one (or a predetermined number) of memory bare chips 1 determined to be non-defective are cut out. Complete the memory module 10 (fourth step). FIG. 4 is a diagram showing the results of a pass / fail inspection (third step) of the memory bare chip 1 mounted on the substrate 2, where a mark 〇 indicates a memory bare chip 1 determined to be non-defective, and a mark X indicates non-defective. Each of the bare chips 1 for memory that have been determined to be non-defective is shown. A plurality of memory bare chips 1 mounted on the substrate 2 are collectively inspected, and a matrix-like inspection result indicating the quality of the inspection is obtained. In the fourth step, defective products are removed from the separated memory modules 10 and only non-defective products are taken out.
このように、 基板 2全体を単位としてその基板 2に実装された複数のメモリ用 ベアチップ 1の良否検査をまとめて行っているため、 切り分けた後の 1個 1個の メモリモジュール 1 0に対して良否検査を行う場合に比べて、 検査の効率を上げ ることができる。  In this way, the pass / fail inspection of a plurality of memory bare chips 1 mounted on the board 2 is performed collectively for the entire board 2 as a unit. Inspection efficiency can be increased as compared with the case where quality inspection is performed.
さらに、 メモリ用ベアチップは 1個あるいは複数個 （ 2個または 4個） を単位 として切り分けられるが、 なるべく多くの個数をひとまとまりとして切り分ける 、 すなわちなるべく 4個ずつ切り分けることによって、 4個取りのメモリモジュ —ルを効率よく製造することができる。  Furthermore, memory bare chips can be cut in units of one or more (two or four). -Can be manufactured efficiently.
本発明は、 上記実施形態に限定されるものではなく、 本発明の要旨の範囲内で 種々の変形実施が可能である。 例えば、 上述した実施形態ではワイヤボンディン グによる実装を行ったが、 フリヅプチップ実装によってメモリ用ベアチップ 1を 実装してもよい。 第 5図は、 フリヅプチップ実装の場合のメモリ用ベアチップ 1 と基板 2の接続状態を示す図である。 同図に示すように、 メモリ用ベアチップ 1 の実装面に形成された基板用パッドと基板 2のメモリ用ベアチップ 1を実装する 面に形成されたチップ用パッドとを対向させ、 バンプ 2 1によって接続する iと でフリップチップ実装が行われる。 フリップチップ実装によれば、 さらに高密度 実装が可能となるため、 製造されるメモリモジュール 1 0の外形寸法をさらに小 さくすることが可能となる。 また、 これからの D R A Mをはじめとする各種の半 導体チップは、 動作速度が高速化されるため配線長は短いほど好ましいが、 フリ ップ実装を採用することにより、 より短い配線長を実現することができる。 The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, mounting by wire bonding is performed, but the bare chip for memory 1 may be mounted by flip-chip mounting. FIG. 5 is a diagram showing a connection state between the bare memory chip 1 and the substrate 2 in the case of flip-chip mounting. As shown in the same figure, the board pads formed on the mounting surface of the memory bare chip 1 and the chip pads formed on the surface of the board 2 on which the memory bare chip 1 is mounted face each other and are connected by bumps 21. Then, flip chip mounting is performed. According to the flip-chip mounting, further high-density mounting is possible, so that the outer dimensions of the manufactured memory module 10 are further reduced. It becomes possible to cut. In addition, DRAMs and other semiconductor chips will have shorter wiring lengths because of their higher operating speeds, but shorter wiring lengths will be realized by adopting flip mounting. Can be.
また、 上述した実施形態では、 基板 2上に各メモリ用ベアチヅプ 1を載せてさ らにその上から C O B実装を行ったため、 基板 2上に各メモリ用ベアチップ 1や ボンディングワイヤ 1 5が突出したが、 各メモリ用ベアチップ 1を基板 2内に収 納してボンディングワイヤ 1 5等が外部に露出しない C I B (Chip In Board ) 構造とすることもできる。 第 6図は、 C I B構造を有するメモリ用ベアチヅプ 1 と基板 2の断面を示す図である。 同図に示すように、 基板 2に凹部を形成し、 そ の凹部の内部にメモリ用ベアチヅプ 1を実装して、 基板用パッ ド 1 1とチップ用 パヅ ド 1 4とをほぼ同一面上に配置させることにより、 実装の際のワイヤボンデ ィング装置のキヤビラリの上下方向の移動を小さくすることができ、 作業効率を 上げることが可能となる。 また、 メモリ用ベアチップ 1の端部にボンディングヮ ィャ 1 5が接触することがないため、 この部分での配線の短絡がなくなり、 不良 率の低減が可能になる。  In the above-described embodiment, the memory bare chips 1 are mounted on the substrate 2 and COB mounting is performed from above, so that the memory bare chips 1 and the bonding wires 15 protrude from the substrate 2. Alternatively, each bare chip 1 for memory may be housed in the substrate 2 to have a CIB (Chip In Board) structure in which the bonding wires 15 and the like are not exposed to the outside. FIG. 6 is a diagram showing a cross section of a memory bear chip 1 having a CIB structure and a substrate 2. As shown in the figure, a concave portion is formed in the substrate 2, a memory chip 1 is mounted inside the concave portion, and the substrate pad 11 and the chip pad 14 are substantially flush with each other. By arranging them in the vertical direction, it is possible to reduce the vertical movement of the cavities of the wire bonding apparatus at the time of mounting, and it is possible to increase work efficiency. Further, since the bonding wire 15 does not come into contact with the end of the memory bare chip 1, the wiring is not short-circuited at this portion, and the defect rate can be reduced.
また、 上述した実施形態では、 単に樹脂 3を流し込んで、 基板 2のメモリ用べ ァチップ 1が実装された面を封止したが、 射出成形によるトランスファーモール ドによって樹脂封止してもよい。 第 7図は、 トランスファ一モールドによる樹脂 成形を説明する図であり、 同図 （a ) は、 基板 2全体に平坦な樹脂成形を行う場 合を、 同図 （b ) は、 同図 （a ) の変形例であって切り分け線に沿って溝を設け る場合をそれぞれ示している。 トランスファーモールドによる樹脂成形は成形時 間を短縮できるため、 大量生産に適している。  In the above-described embodiment, the surface of the substrate 2 on which the memory base chip 1 is mounted is simply sealed by pouring the resin 3, but may be sealed by transfer molding by injection molding. FIG. 7 is a view for explaining resin molding by transfer molding. FIG. 7 (a) shows a case where flat resin molding is performed on the entire substrate 2, and FIG. ) Shows a case in which a groove is provided along a dividing line. Transfer molding resin molding is suitable for mass production because the molding time can be shortened.
また、 上述した実施形態では、 メモリモジュール 1 0の外部接続端子として B G A用パッド 1 3を用いたが、 いわゆる L C C (Leadless Chip Carrier ) 方式 の端子を用いるようにしてもよい。  In the above-described embodiment, the BGA pad 13 is used as the external connection terminal of the memory module 10. However, a so-called LCC (Leadless Chip Carrier) type terminal may be used.
第 8図は、 L C C方式の外部接続端子を用いる場合のメモリモジュール 1 0の 部分的な構造を示す図である。 同図に示すように、 切り分けた後のメモリモ、 ュ —ル 1 0の側面のうち、 縦方向あるいは横方向のいずれか一方向 （あるいは両方 でもよい） に凹部が形成されており、 この凹部表面を覆うように金属メツキをす ることによって外部接続端子 3 1が形成されている。 FIG. 8 is a diagram showing a partial structure of the memory module 10 when an external connection terminal of the LCC system is used. As shown in the figure, a concave portion is formed in one side (or in both directions) of the longitudinal direction or the horizontal direction on the side surface of the memory module or the module 10 after the separation, and the surface of the concave portion is formed. Metal cover to cover As a result, the external connection terminal 31 is formed.
第 9図は、 L C C方式の外部接続端子 3 1の形成過程を説明する図である。 同 図 （a ) に示すように、 基板 2 aには、 実装されたメモリ用ベアチップ 1を切り 分ける切り分け線のうち、 縦方向あるいは横方向のいずれか一方 （あるいは両方 ) に沿ってスルーホール 3 2が形成されている。 ただし、 この基板 2 aをそのま まメモリモジュール 1 0の製造に用いると、 上述した第 2の製造工程における樹 脂封止の際、 流し込まれた樹脂 3によって外部接続端子 3 1に目詰まりが生じる 場合がある。 このため、 同図 （b ) に示すように、 スルーホール 3 2に沿って絶 縁テープ 3 3等の保護部材を形成しておいて、 スルーホール 3 2に樹脂 3が流れ 込むのを防止する。 あるいは、 予め各スルーホール 3 2に半田等を流し込んでお いて、 後に樹脂による目詰まりが生じないようにしてもよい。 その後、 上述した スルーホール 3 2をその中央で切断することにより、 第 8図に示した外部接続端 子 3 1が形成される。  FIG. 9 is a view for explaining a process of forming the external connection terminal 31 of the LCC system. As shown in FIG. 1A, the substrate 2a has through holes 3 along one or both of the dividing lines for separating the mounted memory bare chip 1 in the vertical or horizontal direction. 2 are formed. However, if the substrate 2a is used as it is in the manufacture of the memory module 10, the external connection terminals 31 may be clogged by the poured resin 3 during the resin sealing in the second manufacturing process described above. May occur. Therefore, as shown in FIG. 3B, a protective member such as an insulating tape 33 is formed along the through hole 32 to prevent the resin 3 from flowing into the through hole 32. . Alternatively, solder or the like may be poured into each through hole 32 in advance so that clogging with the resin does not occur later. Thereafter, the above-described through-hole 32 is cut at the center thereof to form the external connection terminal 31 shown in FIG.
また、 上述した実施形態で用いた基板 2としてフレキシブル基板やその他の各 種基板を用いるようにしてもよい。 また、 上述した実施形態では、 半導体チップ としてメモリチップを用い、 半導体装置としてのメモリモジュールを製造する場 合を例にとって説明したが、 メモリチップ以外の半導体チップ、 例えばプロセッ サチップや A S I C等の各種のチップを基板上に実装する場合に適用することが できる。 また、 基板 2から切り分けるメモリ用ベアチップ 1を 1個ずつ切り分け るのではなく、 2個以上の所定個を単位に切り分けるようにしてもよい。 産業上の利用可能性  In addition, a flexible substrate or other various substrates may be used as the substrate 2 used in the above-described embodiment. Further, in the above-described embodiment, a case where a memory chip is used as a semiconductor chip and a memory module as a semiconductor device is manufactured has been described as an example. However, various types of semiconductor chips other than the memory chip, such as a processor chip and an ASIC, may be used. It can be applied when mounting a chip on a substrate. Further, the memory bare chips 1 to be separated from the substrate 2 may not be separated one by one, but may be separated into two or more predetermined chips. Industrial applicability
上述したように、 本発明によれば、 複数の半導体チップが実装された基板の全 体を単位として半導体チップの良否検査が行われるため、 1あるいは少数個の半 導体チップを個別に検査する場合に比べて検査の効率を上げることができる。  As described above, according to the present invention, the quality of semiconductor chips is inspected in units of the entire board on which a plurality of semiconductor chips are mounted, so that one or a small number of semiconductor chips are individually inspected. Inspection efficiency can be increased as compared with the above.

Claims

請 求 の 範 囲 The scope of the claims
1 . 基板上に実装された複数の半導体チップを樹脂封止した状態で各半導体チッ プの良否検査を行った後に前記半導体チップを所定個数を単位にして切り分ける ことにより形成することを特徴とする半導体装置。  1. A method in which a plurality of semiconductor chips mounted on a substrate are sealed with a resin, and each semiconductor chip is inspected for quality. Then, the semiconductor chips are formed by cutting a predetermined number of units. Semiconductor device.
2 . 前記半導体チップはメモリチップであることを特徴とする請求の範囲第 1項 記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the semiconductor chip is a memory chip.
3 . 基板上に複数の半導体チップを実装する第 1の工程と、  3. A first step of mounting a plurality of semiconductor chips on a substrate;
この実装された複数の半導体チップを樹脂で封止する第 2の工程と、 前記複数の半導体チップのそれぞれの良否検査を行う第 3の工程と、 前記複数の半導体チップを所定個数を単位にして切り分ける第 4の工程と、 を備えることを特徴とする半導体装置の製造方法。  A second step of sealing the plurality of mounted semiconductor chips with a resin, a third step of performing a pass / fail inspection of each of the plurality of semiconductor chips, and A method for manufacturing a semiconductor device, comprising: a fourth step of separating.
4 . 前記第 1の工程で実装される前記複数の半導体チップは、 前記基板の一方の 面に形成されており、  4. The plurality of semiconductor chips mounted in the first step are formed on one surface of the substrate,
前記第 3の工程における前記良否検査を、 前記基板の他方の面に形成された前 記複数の半導体チップに対応した端子を介して行うことを特徴とする請求の範囲 第 3項記載の半導体装置の製造方法。  4. The semiconductor device according to claim 3, wherein the pass / fail inspection in the third step is performed via terminals corresponding to the plurality of semiconductor chips formed on the other surface of the substrate. Manufacturing method.
5 . 前記半導体チップはメモリチップであることを特徴とする請求の範囲第 3項 記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor chip is a memory chip.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373952A (en) * 2001-06-15 2002-12-26 Seiko Instruments Inc Method for manufacturing hermetically sealed ic package
JP2003007888A (en) * 2001-06-18 2003-01-10 Seiko Instruments Inc Method for manufacturing hermetically-sealed ic package
JP2004138391A (en) * 2002-10-15 2004-05-13 Renesas Technology Corp Method for manufacturing semiconductor device

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