WO1999013578A1

WO1999013578A1 - Non-linear counting device

Info

Publication number: WO1999013578A1
Application number: PCT/DE1998/001855
Authority: WO
Inventors: Harald Luedtke
Original assignee: Siemens Nixdorf Informationssysteme Ag
Priority date: 1997-09-10
Filing date: 1998-07-03
Publication date: 1999-03-18
Also published as: DE19739768A1

Abstract

The invention relates to a counting device for the non-linear counting of events. According to the invention, a code generator generates a series of code numbers in such a way that the code numbers occur with varying frequency. Every code number is compared with the counter reading and the counter is changed over in accordance with the comparison in such a way that if the counter reading is high the counter is changed over only when infrequent code numbers occur.

Description

Non-linear counter

The invention relates to a non-linear counting device and a method for generating a sequence of multi-digit binary codes from a sequence of clock pulses. The invention further relates to a device for performing the method.

In numerous applications, test samples are required for testing and checking digital circuits and computer systems, which have their own characteristics. Such test patterns are used, for example, when the efficiency of CPU boards is to be optimized for a computer system. Such CPU boards require a large number of resources, such as buffers, art queues etc. for efficient operation. The dimensioning of such resources must be balanced so that a particular resource does not constitute a bottleneck in data processing and possibly the overall performance of the computer system impaired. It is therefore desirable to be able to measure the utilization of these resources during the current computer operation in order to initiate appropriate adjustment measures and, if necessary, to obtain statements for diagnostic purposes. With the help of a certain multi-digit binary code as a test pattern, counter modules can be controlled, which can measure occupancy times and the work intensity of such resources.

Both a high temporal resolution and a long measuring time are aimed for, which is achieved according to the prior art, for example by counters with a large number of binary digits. With large meter readings, however, the high temporal resolution is not necessary in order to achieve a relative accuracy that is approximately the same over the entire counting range. It is therefore an object of the invention to provide a method and an arrangement in which a large number of events can be detected with approximately the same relative accuracy over the entire range.

The solution assumes that a logarithmic representation of the counter reading with a relatively small number of bit positions is sufficient for a large counting range.

The basic idea of the solution is that a code generator generates a sequence of code numbers such that the frequency of the larger numbers is relatively less than the frequency of the smaller numbers. If the event counter is now only switched on when the current code number is greater than its current counter reading, then counting with a larger counter reading is less frequent and logarithmic counting is thus effected.

In a preferred development, a known logarithmic representation is used for the counter reading, in which the number is divided into an exponent and a mantissa. In the usual binary representation, the most significant bits represent the exponents and the others the mantissa. Since they are natural numbers, contrary to the floating-point representation that is usual in computers, no signs are provided and, since they are not rational numbers, neither normalized. The number of bits is also considerably smaller; For most applications, a division of 4 bits for the exponent and 4 bits for the mantissa is sufficient.

For this purpose, the entire counter reading is not compared with the code numbers, but only the higher-order bits that act as exponents. As long as they are all zero, each code word is counted. With the first overflow the mantissa in the exponents no longer counts the code numbers with the lowest value; the mantissa is therefore increased at a lower clock frequency until the next overflow from the mantissa into the exponent fades out the next area of the code numbers and the counting frequency is further reduced.

Accordingly, the invention allows a conventional linear binary counter to be operated so that the result of the count appears in floating point representation.

Code numbers are used in which the frequency decreases logarithmically with the size of the code number. It is therefore a further object of the invention to provide a method and a device for generating a sequence of code numbers, in particular in the form of multi-digit binary codes from a sequence of clock pulses, which, with an increasing number of clock pulses, emits higher-digit binary values at increasing intervals. The frequency of the code numbers is preferably used in inverse proportion to the logarithm of their value in order to achieve the equivalent of a logarithm and thus to simplify the evaluation; if a different spread is desired, a different distribution function can also be used.

According to the invention, a method for generating a sequence of multi-digit binary codes from a sequence of clock pulses is specified, in which the number N of the received clock pulses into an n-digit binary number according to the relationship

i = 0

with a _n = 1 and ag ... ^ nl ^e (0 ' ¹ ) / is converted, in which i is a run variable and a; is the position at the i-th position of the binary number, the number N increased by 1 into an m-digit binary number according to the relationship m N + l = ∑b _i -2 ⁱ i = 0 with b _m = 1 and bg .. . b _m _ι e {0,1}, where m> n,

is converted, in which bj is the position at the i-th position of the binary number for the N + l-th clock pulse, then an M-position binary code A according to the relationship

with a-j_ = 0 if i> n and

with b _j _ = 0 if i> m,

is formed and then output as an output signal and further processed.

The M-digit binary code A thus generated has the property that a certain value within the definition range of the binary code, namely {0, 1, ..., 2 ^M -1}, occurs twice as often as the next higher value. For example, a hexadecimal code results in a sequence of binary numbers depending on the number of clock pulses, the value "E" occurring twice as often as the value "F", the value "9" occurring twice as often as the value "A" Value "5" occurs twice as often as value "6" etc.

Because when generating the M-digit binary code A, only the lowest M binary digits of the clock number are taken into account. binary code A is repeated with a period of 2 (2 ^M -1) cycles, for example with a hexadecimal code after 32768 clock pulses. The binary code A specifies for each clock pulse the number of bits reduced by 1, which change in the binary representation of the number N of clock pulses during the transition to the number N + 1. Typically, such a binary code A is used to control counter modules which have a logarithmic counting behavior, ie the higher the number of clock pulses, the slower the counter module counts. In this way, an almost logarithmic counting behavior is achieved. This means that relatively few bit positions are required to represent a large number of clock pulses. With such a form of representation, the relative resolution remains approximately constant over the entire counting period. However, other possible uses are also conceivable in which a test sample with the properties mentioned is required, for example for diagnostic purposes in a computer system.

A single code generator can supply several counters, all of which are conventional binary counters, which only need to be supplemented by an enable input and a comparator.

A 4-digit binary code is preferably used, so that the number of clock pulses need only be represented modulo 2 ^ -5, i.e. the size M is 4.

It should also be noted that the run variables n and m are dependent on the numbers N and N + 1. The highest values a-j_ and bj_ for i = n then have the value 1.

Furthermore, the invention relates to a device for performing the method. With this facility Targetable advantageous effects are essentially the same as those according to the method according to the invention.

An embodiment of the invention is shown below with reference to the figures. 1 shows a device in which a large number of counter modules are controlled by the binary code,

FIG. 2 shows a sequence of binary codes A in hexadecimal representation,

Figure 3 shows the structure of a counter module, and

FIG. 4 shows a code generator which is constructed from digital standard modules, and

Figure 5 shows another code generator, which is constructed from digital standard components.

Figure 1 shows a device according to the invention, which is used in a gate array for a CPU board of a computer system. A large number of counter modules ZO, ZI, ..., Zm-1, Zm, with m as the run variable, should count clock pulses CLOCK depending on an enable signal BUSYO, BUSYl, ..., BUSYm-1, BUSYm, for example by the load on one identify certain resource during computer operation. Depending on the clock pulses CLOCK counted, fine-tuning measures can then be initiated or statements made for diagnostic purposes. In order to minimize the technical effort for the counter modules ZO to Zm, these counter modules ZO to Zm work with an almost logarithmic scaling. In this way, a measuring range from 15 ns to approx. 15 ms can be covered with an 8-digit simple standard counter module at a CLOCK frequency of 66.67 MHz, ie a range in the ratio of 1: 1,000,000, whereby the relative resolution remains approximately constant over the entire measuring range.

The counter modules ZO to Zm are designed as 8-bit binary counters, with the least significant bit positions 0 to 3 being interpreted as the base and the bit positions 4 to 7 being interpreted as the exponent to the base. As long as a resource or execution unit to be monitored by the counter module ZO to Zm is not active, the release signal BUSYO to BUSYm is logic "0". In this state, the assigned counter module ZO to Zm is deleted. If the corresponding BUSY signal BUSYO to BUSYm is active, i.e. has a logic level "1", the assigned counter module ZO to Zm begins to count. The logarithmic counting behavior is achieved in that the counter block ZO to Zm counts the slower the higher the value B of the higher-order bit positions 4 to 7, i.e. the higher the value of the exponent.

In order to be able to control the large number of counter modules ZO to Zm with a single binary signal A via a bus 11, a code generator or a prescaler V is used which generates the binary code A with a width of 4 bits. This binary code A is determined in accordance with the relationship given below, the prescaler V being supplied with the sequence of clock pulses CLOCK. A 16-bit code block is used as the prescaler. The number N of arriving clock pulses CLOCK is converted into a 16-digit binary number according to the relationship

15

N = ∑ a _r 2 'i = 0 with aj_ € {0,1}, converted, ie represented in the form modulo 2 ^ 6, where i is a run variable and aj_ is the position at the i position of the binary number.

The subsequent clock pulse, i.e. the N + lth clock pulse is also converted into a binary number according to the relationship

15

N + l = ∑b _r 2 'i = 0 with b _n e {0,1}

changed, i.e. in the form modulo 2 ^^, where bj_ is the position at the i-position of the binary number for the N + lth clock pulse.

Then the binary code A according to the relationship

determined. The binary code A determined in this way is called the hexadecimal code, i.e. with a width of 4 bits, output on the bus 11.

A sequence of the binary code A is shown in FIG. The value "4" is intended to illustrate how the sequence of binary codes A is structured. Within the interval I, in which the output value 4 would repeat itself at the next higher clock pulse, the value "3" occurs twice, the value "2" four times, the value "1" eight times and the value "0" sixteen times. This means that the binary code A has the property that each value occurs twice as often as the next higher one. With reference to the hexadecimal representation according to FIG. 2, this generally means that the value "E" occurs twice as often as the value "F" and the value "D" twice as often the value "E" etc. up to the value "0", which occurs twice as often as the value "1".

Figure 3 shows the structure of one of the counter modules ZO to Zm, in this case the counter module ZO. This counter block ZO contains a standard binary counter with a width of 8 bits. These 8 bits, which are output on line 12, are divided into a lower counter 14 with the low-order bits 0 to 3 and the count U and an upper counter 16 with bit positions 4 to 7 and the count B. The counter 10 has three inputs, a count enable input CE, a reset input R and a clock input T, to which the clock pulses CLOCK are supplied. The reset input R is preceded by a negation element 18, to which the enable signal BUSY is fed. This enable signal BUSY is also fed to an AND gate 20, the output of which is connected to the input CE. The other input of the AND gate 20 is connected to the output of a comparator 22 which compares the value B of the upper counter 16 with the current value of the binary code A.

The mode of operation when counting the Z0 counter is explained below. As long as the enable signal BUSY has the logic level "0", the counter 10 is cleared, ie its output signal on line 12 is zero. When the enable signal BUSY has the value "1", the counter 10 begins to count the clock signals CLOCK supplied to it. This counting depends on the signal status at the CE input. If the upper counter 16 has a count B = 0, then all incoming clock pulses CLOCK are counted until there is an overflow, ie the fourth bit position of the upper counter 16 is "1" and the count B is different from zero. The count B is compared with the current binary code A by the comparator 22. Only when the condition is A> B the lower counter counts another clock pulse CLOCK and increases its count U by 1. Due to the property of the binary code A that higher-order hexadecimal values occur only half as often as the next lower hexadecimal value, the count-enable input CE is only half as often generates a signal.

The time T _z that has elapsed since the enable signal BUSY became active results from the following relationship:

B- \

T = f / -2 ^{/ i} + ∑ (16-2 ') [(-7 + 16) -2 ^ß -16] -

(= 0

where t _{p is} the clock period of the sequence of clock pulses CLOCK and T _{z is} the measured time.

Due to the properties of the binary code A, the various counter modules ZO to Zm can be activated and deactivated independently of one another at any time via the release signal BUSYO to BUSYm without a time measurement error occurring. An advantage of the invention is that standard counters can be used that have a relatively small number of bit positions, for example 8 bit positions, but still cover a large measuring range. The use of standard counter modules has proven to be extremely advantageous, since they can be incorporated easily and with little effort into ASIC modules or gate arrays.

In order to generate the binary code, the previous binary number N can be temporarily stored and compared bit by bit with the new value by means of an XOR operation. The number of binary "1" bits must be determined from this result. If the number of bits is small, this can be done using a read-only memory. Instead of a fixed value memory, an adder for, for example, sixteen 1-bit words can also be used, in that the two lowest Bits are added with the first adder and the next higher bit is added to the result by a further adder, the word width increasing and the last adder having the word width of the result. A serial evaluation is also possible if time conditions allow it. It is also possible to build a code generator from simple standard components so that the code is generated directly at its output.

Further variants of a code generator are conceivable. Figure 4 shows such a code generator for generating a 3-digit binary code A, i.e. in this case M is 3. This code generator uses simple commercially available digital standard modules, i.e. the code generator can be set up with relatively simple means. The clock pulses CLOCK are fed to a digital register 30 with a width of 8 bits at its clock input. The outputs of this register 30 are fed to the input of an increment block 32 and to an input of 8 XNOR gates 34. The outputs of the increment module 32 are connected on the one hand to the other input of the XNOR gates 34 and on the other hand to the D input of the register 30. The two building blocks 30 and 32 together form a waiting counter, i.e. with each clock pulse CLOCK the number N appears in binary form at the output Q of the register 30 and the value N + 1 increased by 1 by the increment module 32 is present at the D inputs of the register 30. The XNOR gates 34 compare the binary values N and N + 1 and determine in which binary position N and N + 1 differ.

The outputs of the eight XNOR gates 34 are each fed to an input 10 to 17 of an 8: 3 priority encoder module 36, for example the standard module 74LS148 by Texas Instruments. The priority encoder module 36 determines which is the most significant active input 10 to 17, with 10 being the least significant and 17 being the most significant input. In accordance with the standardized code regulation, the module 36 emits signals at its outputs A0, AI, A2, which are converted into the binary code A with the bit positions 0, 1, 2 by the negating elements 38.

An alternative code generator is shown in FIG. 5. Here the counter outputs are swapped, i.e. the least significant bit A0 of the counter 32a is applied to the most significant bit 17 of a priority encoder 36. The least significant bit thus has the highest priority, so that all odd counter readings lead to the same code word. If, in the circuit shown in FIG. 5, the 74LS148 block is used as the priority encoder 36, the inputs of which are inverted, i.e. are active at LOW, the outputs of counter 32a must also be inverted, as indicated in FIG. 5. The negation elements 38 are not necessary in this application, since the outputs are already inverted, so that the code word of the highest priority has all bit positions at zero. It should be noted that a priority encoder forms the integer part of the dual logarithm of a binary code word at its inputs. 5 thus generates the logarithm of a permutation of the bit positions of the counter 32a.

Furthermore, a code generator can also be effected by a counter with a width of 16 bits, for example, the outputs of which form the address inputs of a read-only memory, which are quite commercially available with a storage capacity of 64 kbytes. This represents a table by means of which each odd address the code word zero, each even, but not by four divisible address the code word One, each by four but not by eight divisible addresses, the code word two, etc. is assigned. The code word "fifteen" is then assigned to address 0 and thus only appears once. The code generators mentioned generate code numbers in such a way that the code numbers are equally distributed over a frequency. This embodiment is to be preferred in almost all cases when the events to be counted are statistically to be regarded as random. However, stochastic encoders according to the known methods of stochastic computing technology can also be used if a correlation of the events to be counted with the clock generator of the encoder cannot be ruled out. In principle, it is also possible to use an encoder which first generates all code numbers with the lowest frequency and lastly the code number with the highest frequency, provided that the duration of the events is to be determined and the events all begin at the same time as the code generator also starts.

Claims

Expectations

1. Counter for non-linear counting of events with the features:

- A code generator (V) generates a sequence of code numbers (CODE) such that the code numbers occur with different frequencies;

- Each code number is compared with the status of the counter and the counter is switched depending on the comparison in such a way that when the count is high, only code numbers with low frequency are switched on.

2. Counter according to claim 1, wherein a code generator is used in which the frequency of the code numbers is inversely proportional to the logarithm of their value.

3. Counter according to claim 2, wherein the counter is incremented when the code number is greater than or equal to a number obtained from the status of the counter.

4. Counter according to claim 3, wherein the number obtained from the state of the counter is obtained by dividing the count by a predetermined divisor.

5. The counter of claim 4, wherein the divisor is the basis of the logarithm used by the code generator.

6. Counter according to one of claims 1 to 5, wherein a code generator is used which generates code numbers in which the code numbers of a frequency are evenly distributed over time.

7. Generator for generating a sequence of code numbers of different frequencies from a sequence of clock pulses (CLOCK), wherein a counter (32, 32a), which has as many binary digits as different code numbers are generated, is switched on by the clock pulses,

- The integral part of a logarithm of a permutation of the counter reading is formed.

8. Generator for generating a sequence of code numbers of different frequencies from a sequence of clock pulses (CLOCK), wherein

a counter (32, 32a), which has as many binary digits as different code numbers are generated, is switched on by the clock pulses,

- The code number of the value a is always generated when the bit of the value a of the binary counter is active.

9. Generator according to claim 7 or 8, wherein a priority encoder (36) is used, the highest priority input of which is connected to the least significant bit of the counter (32, 32a).

10. Method for generating a sequence of code numbers of different frequencies in the form of multi-digit binary codes from a sequence of clock pulses (CLOCK),

- in which the number N of clock pulses arrived

(CLOCK) into an n-digit binary number after the relationship

N = ∑ai-2 ¹ i = 0

* with a _n = 1 and ao ... a _n _τ_ e {0,1}

* is converted, where i is a run variable and aj is the position at the i-th position of the binary number, - the number N increased by 1 into an m-digit binary number according to the relationship m

∑ i-2 ¹ i = 0

* with b _m = 1 and brj ... b _m - ± ^e i ^{0 1} } *, where bj is the position at the i-th position of the binary number for the N + l-th clock pulse,

- then an M-digit binary code A according to the relationship

* with aj_ = 0 if i> n and

* bi = 0 if i> m

- Formed and then output as an output signal and processed.

11. The method according to claim 10, characterized in

- That the counter module (ZO) contains a lower counter (14) and an upper counter (16),

- That the lower counter (14) at a counter reading B = 0 of the upper counter (16) counts all incoming clock pulses (CLOCK) until the count B is different from 0 due to an overflow, and

- That the count B is compared with the binary code A and if the condition A≥B the lower counter (14) counts a clock pulse (CLOCK) and increases its count U by 1.

12. The method according to claim 10 or 11, characterized in that the counting time T _z for the counter module is formed according to the relationship

(U + 2 ^K ) - _> B <- »K t. where t _{p is} the clock period of the sequence of clock pulses.