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WO1999003202A2 - Circuit bistable a retard commande en fonction du niveau - Google Patents

Circuit bistable a retard commande en fonction du niveau Download PDF

Info

Publication number
WO1999003202A2
WO1999003202A2 PCT/RU1998/000213 RU9800213W WO9903202A2 WO 1999003202 A2 WO1999003202 A2 WO 1999003202A2 RU 9800213 W RU9800213 W RU 9800213W WO 9903202 A2 WO9903202 A2 WO 9903202A2
Authority
WO
WIPO (PCT)
Prior art keywords
sοοτveτsτvennο
πeρvοgο
τρanzisτοροv
ποdκlyucheny
πaρallelnο
Prior art date
Application number
PCT/RU1998/000213
Other languages
English (en)
Russian (ru)
Other versions
WO1999003202A3 (fr
Inventor
Sergei Kuzmich Luzakov
Original Assignee
Sergei Kuzmich Luzakov
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from RU97111592/09A external-priority patent/RU97111592A/ru
Application filed by Sergei Kuzmich Luzakov filed Critical Sergei Kuzmich Luzakov
Publication of WO1999003202A2 publication Critical patent/WO1999003202A2/fr
Publication of WO1999003202A3 publication Critical patent/WO1999003202A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Definitions

  • the invention is provided with a pulse technique and can be used in computing devices and a system for installing a hardware on the base of the technology.
  • s ⁇ de ⁇ z haschy ⁇ e ⁇ vy, v ⁇ y, ⁇ e ⁇ y and che ⁇ ve ⁇ y, ⁇ ya ⁇ y, shes ⁇ y ⁇ DP- ⁇ anzis ⁇ y s ⁇ ve ⁇ s ⁇ venn ⁇ ⁇ e ⁇ v ⁇ g ⁇ and v ⁇ g ⁇ ⁇ i ⁇ a and ⁇ a ⁇ zhe sedm ⁇ y, and v ⁇ sm ⁇ y devya ⁇ y, desya ⁇ y ⁇ DP- Transports are related to the first and second types.
  • the third and seventh power transmissions are turned on between the first main power bus and the second main power supply, which is inactive
  • the sixth and ninth transports are included between the second bus and the tenth transformer.
  • the fourth and fourth transients are included in parallel between the gates of the fourth and tenth transgressions, and the related costs are excluded. From the first, the fourth, and the fifth, tenth of the incidents, the corresponding to the first and second 2 power supply buses.
  • the damages of the first, fourth and second, and the fifth transaction are connected to the invoice and the direct input of the power.
  • the cost of this product is its own dynamic, lightweight, low reliability.
  • the objective, to solve the problem, is the claimed invention, is to achieve high reliability of the function in combination with small hardware costs.
  • B-thumper adjusted for the first time (.J. 1) first (1), second (2), third (3), seventh (4), eight (5), ninth (6) and fifth (7) - the sixth (8), sixth (9), tenth (10), eleventh (11), twelfth (12) ⁇ DP-transforms of the corresponding first ( ⁇ ) and second ( ⁇ ) type.
  • the first (1) and process (3) processes are turned on in parallel between the first power bus (13) and the inverted output (14) of the power supply.
  • the fifth (7) and sixth (9) power supply is turned on in parallel between the main power bus (15) and the direct output (16) of the power supply.
  • the second (2) and the fourth (8) paths are included in parallel between the direct pathway (16) and the inverse pathway (14) outlets of the pathway.
  • the 8th (5) and ninth (6) processes are included in the sequence between
  • Seventh (4) alternative is included in parallel with the eight (5), or (see JUNE 1) parallel with the included in eight (5) and the ninth (6) istanzum.
  • the tenth (10) alternative is included in parallel with the eleventh (11), or (see JUNE 1) is parallel with the included in the eleventh (11) and twelve (12) alternatives.
  • Eight (5) and one-eleven (11) shutdowns have been connected to the input (18) of the electronic unit.
  • the gates of the third (3) and sixth (9) transports were connected to the inverse exit (17) of the transformer.
  • the waivers of the second (2), fifth (7) and first (1), four (8) of the complaints were made to the parties (19).
  • the conversion rate is a logical level of interest that is valid at the input (18), since the seventh (4) and tenth
  • the level is physically fixed at the inverse exit (17) and at the gate of the road (3) and the sixth (9) roadway. This is achieved by logging the ninth (6), or twelve (12) and the tenth (10), or the seventh (4), depending on the loss (16).
  • ⁇ master ⁇ As a result, in the absence of the active signal ⁇ -signal is in one of the two stable states and does not depend on the signal level for the information (18).
  • the used battery is intended for use in microphones on the basis of the DPS technology in the quality of the memory element. Using it allows you to combine the high reliability of the implementation and the economic efficiency of implementation, provided that the device is used in a manner that is convenient for use.
  • the high reliability of the operation of the power supply unit is stipulated by the fact that the fixation of its operation is ensured by an inadequate, non-volatile signal.
  • the signal is the signal generated by one of the two outputs of the ⁇ -switch, which is controlled by the operation of the pulse.

Landscapes

  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Cette invention se rapporte aux techniques de génération d'impulsions et concerne un circuit bistable à retard commandé en fonction du niveau qui peut être utilisé dans des éléments de mémoire ou dans des générateurs commandés. Ce circuit bistable peut être réalisé d'après les techniques de MIS complémentaires et ne nécessite que six paires de transistors MIS (1 à 12). La fixation de l'état se fait directement à l'aide d'un signal logique qui est émis à l'une ou l'autre de deux sorties synchronisées (14, 16) sous l'action d'impulsions d'horloge (19, 20).
PCT/RU1998/000213 1997-07-07 1998-06-30 Circuit bistable a retard commande en fonction du niveau WO1999003202A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU97111592 1997-07-07
RU97111592/09A RU97111592A (ru) 1997-07-07 D-триггер, управляемый фронтом (варианты) и d-триггер, управляемый уровнем для использования в нем

Publications (2)

Publication Number Publication Date
WO1999003202A2 true WO1999003202A2 (fr) 1999-01-21
WO1999003202A3 WO1999003202A3 (fr) 1999-04-08

Family

ID=20195088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1998/000213 WO1999003202A2 (fr) 1997-07-07 1998-06-30 Circuit bistable a retard commande en fonction du niveau

Country Status (1)

Country Link
WO (1) WO1999003202A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0905892A3 (fr) * 1997-09-30 2000-12-20 Siemens Aktiengesellschaft Bascule RS avec des entrées de validation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE383325B (sv) * 1974-01-31 1976-03-08 Stella Maskiners Forseljnings Anordning vid ett hoj- och senkbart lyftorgan till lastfordon sasom truckar o.d. for fasthallning ovanifran av en av lyftorganet uppburen last
CH629921A5 (fr) * 1977-07-08 1982-05-14 Centre Electron Horloger Structure logique de bascule bistable d.
US4275316A (en) * 1978-11-06 1981-06-23 Rca Corporation Resettable bistable circuit
GB2174856A (en) * 1985-05-08 1986-11-12 Racal Microelect System Hysteresis latch arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0905892A3 (fr) * 1997-09-30 2000-12-20 Siemens Aktiengesellschaft Bascule RS avec des entrées de validation

Also Published As

Publication number Publication date
WO1999003202A3 (fr) 1999-04-08

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