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WO1999000840A1 - Interconnect spacer structures - Google Patents

Interconnect spacer structures Download PDF

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Publication number
WO1999000840A1
WO1999000840A1 PCT/US1998/006887 US9806887W WO9900840A1 WO 1999000840 A1 WO1999000840 A1 WO 1999000840A1 US 9806887 W US9806887 W US 9806887W WO 9900840 A1 WO9900840 A1 WO 9900840A1
Authority
WO
WIPO (PCT)
Prior art keywords
interconnect
contact
sidewall
layer
tunnel
Prior art date
Application number
PCT/US1998/006887
Other languages
French (fr)
Inventor
Basab Bandyopadhyay
Michael J. Gatto
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1999000840A1 publication Critical patent/WO1999000840A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Definitions

  • the invention relates to the field of semiconductor processing and more particularly to an improved method of coupling adjacent interconnect levels in a semiconductor process by forming spacer structures on the sidewalls of an interconnect level to minimize susceptibility to contact overlap.
  • Integrated circuits include a large number of transistors fabricated into a monolithic semiconductor substrate. Isolation structures such as field oxides or shallow trench dielectrics are used to electrically isolate the individual transistors from one another. The transistors are then selectively coupled to other transistors to achieve a desired circuit through the use of patterned layers of conductive interconnect structures. In semiconductor processes employing multiple interconnect levels, each interconnect level is selectively coupled to a subsequentlv formed interconnect level. Multiple level interconnects enable greater functional complexity and can reduce the average interconnect length thereby minimizing the RC delay associated with the interconnects.
  • Each interconnect level typically includes a plurality of patterned interconnect structures comprised of a conductive material such as aluminum.
  • Aluminum interconnects have a desirably high conductivity and adhere well to oxide, which is commonly used as an insulating layer in semiconductor processing.
  • oxide which is commonly used as an insulating layer in semiconductor processing.
  • forming fine line patterns from an aluminum layer using optical photolithographic techniques is difficult because of aluminum's high reflectivity.
  • Optical energy rays reflected off the aluminum upper surface may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile.
  • an anti-reflective coating can be deposited on the aluminum layer prior to the photolithography/etch sequence. The ARC minimizes the energy reflected back to the energy source during exposure.
  • the coupling of adjacent interconnect levels in a multiple interconnect level process is typically accomplished by depositing an insulating material upon the existing interconnect level and forming via or tunnel structures through the insulating material to predetermined locations in the underlying interconnect level using well known photolithography and etch techniques.
  • the aspect ratios i.e., the ratio of the vertical dimension to the lateral dimension
  • these contact tunnels necessitate a dedicated processing sequence to fill or "plug" the contact tunnels with a conductive material before depositing and patterning the subsequent interconnect level.
  • Chemically vapor deposited tungsten is an example of a commonly used material for plugging contact tunnels.
  • tungsten exhibits poor adhesion to typically used insulating materials such as oxide, however, it is not uncommon to precede the tungsten deposition process with an adhesion layer deposition during which a thin adhesion layer, typically comprised of a refractory metal, is deposited on the sidewalls of the contact tunnel.
  • a thin adhesion layer typically comprised of a refractory metal
  • the adhesion layer exhibits good adhesion to both oxide and tungsten and therefore provides an adhesive interface between the tungsten plug and the oxide.
  • the contact tunnel sidewalls terminate entirely upon an upper surface of the underlying interconnect structure.
  • Interconnect 11 is formed on an upper surface of the semiconductor substrate 10.
  • Interconnect 11 includes an aluminum base 12 and an antireflective coating 14 formed on upper surface of the aluminum base 12.
  • Interconnect 11 includes a pair of sidewalls 13a and 13b.
  • Interlevel dielectric 16 includes a contact tunnel 18.
  • Contact tunnel 18 includes a pair of sidewalls 20a and 20b.
  • Contact tunnel 18 overlaps interconnect 11 by a distance x 0 which represents the displacement between the second sidewall 20b and second sidewall 13b of interconnect 11. Because of this overlap, the etch process used to form contact tunnel 18 extends along second sidewall 13b of interconnect 1 1 thereby exposing a portion of the sidewall of the conductive base layer 12.
  • conductive base layer 12 comprises aluminum
  • a subsequent thin film deposition process such as the deposition of an adhesion layer in connection with the fabrication of a tungsten plug, for example, is made more difficult by the narrow and deep geometry of the contact structure along the sidewall of interconnect structure 11.
  • the present invention contemplates a semiconductor process in which an interconnect layer is formed on an upper surface of a semiconductor substrate.
  • the interconnect layer includes an interconnect structure and the interconnect structure includes an interconnect sidewall.
  • a spacer structure is then formed on the sidewall of the interconnect layer and an interlevel dielectric is then deposited on the interconnect layer.
  • a contact tunnel is thereafter formed into the interlevel dielectric.
  • a center of the contact tunnel is preferably aligned over the interconnect structure.
  • a perimeter of the contact tunnel may overlap the underlying interconnect structure. In other words, the perimeter of the contact tunnel may extend beyond a plane defined by the interconnect sidewall.
  • the presence of the spacer structure upon the interconnect sidewall during the contact tunnel formation substantially prevents the interconnect sidewall from exposure during the formation of the contact tunnel.
  • the contact tunnel is plugged with a conductive material.
  • the presence of the spacer structure on the interconnect sidewall during the plugging of the contact tunnel substantially prevents the conductive material from contacting the interconnect sidewall.
  • the formation of the interconnect layer is accomplished by depositing a metal layer on an upper surface of the semiconductor substrate.
  • the metal layer preferably comprises aluminum.
  • an antireflective coating is deposited on an upper surface of the metal layer.
  • the metal layer and the antireflective coating are patterned.
  • the patterning of the metal layer and the antireflective coating is typically accomplished with a single photolithography/etch sequence.
  • the antireflective coating is preferably a refractory metal such as titanium, molybdenum, platinum, palladium, nickel, or an alloy thereof in one presently preferred embodiment in which the conductive base layer comprises aluminum, the refractory metal comprises titanium nitride (TiN).
  • the spacer structures are comprised of either polysilicon or silicon nitride.
  • the formation of the spacer structures includes the steps of chemically vapor depositing a spacer film on a topography defined by the interconnect layer and the semiconductor substrate.
  • the topography includes planar regions that are substantially parallel to an upper surface of the semiconductor substrate.
  • the spacer film is antisotropically etched until portions of the topography are removed.
  • the chemical vapor deposition of the silicon nitride is accomplished by reacting silane and NH 3 in a plasma enhanced C VD reactor chamber maintained at a temperature range of approximately 400 °C and a pressure of less than approximately 2 torrs.
  • the deposition of the interlevel dielectric preferably comprises the process of decomposing TEOS in a C VD reactor chamber maintained at a temperature in the range of approximately 400° C and a pressure of less than approximately 2 torrs.
  • the plugging of the contact tunnel preferably includes the steps of depositing an adhesion layer on sidewalls of the contact tunnel and depositing a plug material until the contact tunnel is filled.
  • the adhesion layer comprises a refractory metal such as titanium, tungsten, molybdenum, palladium, platinum, nickel, and appropriate alloys thereof or other appropriate refractory metal.
  • the adhesion layer is preferably comprised of TiN deposited in a CVD reactor chamber.
  • the present invention further contemplates an integrated circuit including a semiconductor substrate, an interconnect layer, a spacer structure, an interlevel dielectric layer, and a contact plug.
  • the interconnect layer is formed on an upper surface of the semiconductor substrate.
  • the interconnect layer includes an interconnect structure and the interconnect structure includes an interconnect sidewall.
  • the spacer structure is formed in contact with the sidewall of the interconnect structure.
  • the interlevel dielectric layer is formed above the interconnect layer.
  • the interlevel dielectric includes a contact tunnel. A center of the contact tunnel is preferably aligned over the interconnect structure.
  • the contact tunnel may overlap the interconnect structure to some extent. In other words, a perimeter of the contact tunnel may extend beyond a plane defined by the interconnect sidewall.
  • the contact plug fills the contact tunnel.
  • the interconnect layer includes a metal layer formed on an upper surface of the semiconductor substrate and an antireflective coating formed on an upper surface of the metal layer.
  • the metal layer comprises aluminum and the antireflective coating comprises a refractory metal.
  • the refractory metal is preferably comprised of titanium, molybdenum, platinum, palladium, nickel, and appropriate alloys thereof or other appropriate refractory metal.
  • the spacer structure comprises either polysilicon or silicon nitride.
  • the interlevel dielectric is preferably comprised of a CVD oxide such as an oxide formed from a TEOS source.
  • the contact plug includes a refractory metal outer shell in contact with the sidewalls of the contact tunnel and the plug further includes a conductive core.
  • the refractory metal outer shell comprises TiN and the conductive core comprises tungsten.
  • Fig. 1 is a partial cross-sectional view of an interconnect structure and an overlapping contact tunnel:
  • Fig. 2 is a partial cross-sectional view of a metal layer formed on an upper surface of a semiconductor substrate:
  • Fig. 3 is a processing step subsequent to Fig. 2 in which an antireflective coating is formed on an upper surface of the metal layer
  • Fig. 4 is a processing step subsequent to Fig. 3 in which the metal layer and the antireflective coating have been patterned to form and interconnect level on an upper surface of the semiconductor substrate;
  • Fig. 5 is a processing step subsequent to Fig. 4 in which a spacer film has been deposited over the interconnect level and the semiconductor substrate:
  • Fig. 6 is a processing step subsequent to Fig. 5 in which the spacer material has been anisotropically etched to form a spacer structure on a sidewall of the interconnect structure;
  • Fig. 7 is a processing step subsequent to Fig. 6 in which an interlevel dielectric has been deposited over the interconnect level and the semiconductor substrate;
  • Fig. 8 is a processing step subsequent to Fig. 7 in which a contact tunnel has been formed in the interlevel dielectric
  • Fig. 9 is a processing step subsequent to Fig. 8 in which an adhesion layer and a conductive plug material have been deposited onto the existing semiconductor topography;
  • Fig. 10 is a processing step subsequent to Fig. 9 in which the conductive plug material and the adhesion layer have been planarized leaving a contact plug that fills the contact tunnel and provides a conductive path to the interconnect structure.
  • a conductive layer 102 is formed on upper surface 101 of semiconductor substrate 100.
  • Semiconductor substrate 100 preferably includes a monocrystalline silicon substrate into which a plurality of transistors have been fabricated with well known transistor fabrication techniques.
  • Semiconductor substrate 100 may further include one or more interconnect levels and one or more levels of entry level dielectric layers.
  • Upper surface 101 of semiconductor substrate 100 suitably includes an upper portion of an insulating layer that isolates conductive layer 102 from previous interconnect levels and from the transistors within semiconductor substrate 100 and further includes selectively located conductive paths to existing interconnect levels.
  • metal layer 102 is primarily comprised of aluminum possibly in combination with small amounts (i.e., ⁇ 5%) of copper, silicon or other suitable material.
  • Metal layer 102 is typically deposited upon semiconductor substrate 100 with a physical vapor deposition or sputtering process using an aluminum or aluminum alloy target as is well known in the field of semiconductor processing.
  • antireflective coating 104 is deposited upon an upper surface of metal layer 102.
  • Antireflective coating 104 is used in conjunction with aluminum or other metal interconnect levels to improve the resolution obtainable with conventional photoresist masking techniques. If photoresist is deposited directly upon metal layer 102, the optical energy reflected back to the energy source by the conductive metal layer during the exposure of the photoresist results in undesirably ragged photoresist profiles that can negatively effect the critical dimensions and sidewall profile of the subsequently formed interconnect.
  • antireflective coating 104 comprises a refractory metal.
  • a refractory metal refers to a metal or metal alloy comprising titanium, molybdenum, tungsten, palladium, platinum, nickel, appropriate alloys thereof, or other appropriate refractory metal.
  • antireflective coating 104 is preferably comprised of sputter deposited titanium nitride (TiN) It will appreciated to those skilled in the art of sputter deposition processes that antireflective coating 104 is preferably deposited upon metal layer 102 in a single process step without breaking vacuum such that the semiconductor substrate is not exposed to atmosphere between the deposition of the metal and the deposition of the antireflective coating.
  • an interconnect level 1 10 is formed by patterning conductive layer 102 and antireflective coating 104 using well known photolithography masking techniques. As will be appreciated to those skilled in the art of semiconductor processing, the patterning of metal layer 102 and antireflective coating 104 can typically be accomplished using a single photolithography/etch process sequence.
  • Interconnect level 110 includes a first interconnect structure 112a and a second interconnect structure 112b. Each interconnect structure 112 includes a metal section 116 and an antireflective coating section 118. Each interconnect structure 112 further includes an interconnect sidewall 114.
  • Spacer material 130 is deposited upon the topography defined by interconnect level 110 and semiconductor substrate 100.
  • Spacer material 130 includes a plurality of planar regions represented in Fig. 5 by reference numerals 132a and 132b.
  • Planar regions for purposes of this disclosure, refer to regions of the spacer layer substantially parallel to upper surface 101 of semiconductor substrate 100.
  • spacer material 130 is typically formed by a low pressure (i.e.. less than 2 torrs) chemical vapor deposition process.
  • spacer material 130 is intended to be used for the formation of spacer structures upon sidewalls 114 of interconnect structures 112, as described further below.
  • the spacer structures will serve to protect sidewalls 114 from subsequent etch and deposition processes.
  • the preferred embodiment of the present invention contemplates a spacer material 130 comprised of silicon nitride.
  • Silicon nitride is desirable as a spacer material in the present invention because silicon nitride is characteristically an excellent barrier to mobile contaminants. In other words, it is well known that mobile impurities or other contaminants cannot typically penetrate through a silicon nitride barrier layer.
  • the silicon nitride is preferably deposited with a low temperature chemical vapor deposition process during which silane is reacted with NH 3 at a temperature in the range of approximately 400 °C at a pressure of less than approximately 2 torrs.
  • silicon nitride is an excellent barrier layer, the high dielectric constant associated with silicon nitride may undesirably increase parasitic capacity between adjacent interconnect structures 112.
  • An alternative embodiment of the present invention contemplates a spacer material comprised of chemically vapor deposited polysilicon.
  • the polysilicon is typically deposited by thermally decomposing silane in a CVD reactor chamber maintained at a temperature in the range of approximately 400 °C and a pressure of less than approximately two tours.
  • spacer structures 140 are formed on sidewalls 114 of the interconnect structures 112 by anisotropically etching spacer film 130 until planar regions 132 of spacer film 130 are removed. Removing the planar regions of a conformal film deposited over an underlying topography is typically accomplished with an anisotropic etch process using minimum overetch as is well known in the field of semiconductor processing.
  • interlevel dielectric layer 150 is deposited over interconnect level 110 and semiconductor substrate 100.
  • the deposition of interlevel dielectric 150 is accomplished by decomposing TEOS in a PEC VD chamber maintained at a temperature of approximately 400 °C and a pressure of less than approximately 2 torrs and following the deposition with a planarization process.
  • the planarization process is designed to result in the formation of a substantially planar upper surface 151 of interlevel dielectric layer 150. Portions of interlevel dielectric layer 150 removed by the planarization process are shown in phantom in Fig. 7.
  • suitable process sequences for fabricating and planarizing interlevel dielectric 150 may include, by way of example, a
  • TEOS CVD deposition process in combination with a chemical mechanical polish or a deposition and etch back of a spin-on glass.
  • Another embodiment might include a high density plasma (HDP) deposition process in combination with a PECVD TEOS and an etchback.
  • HDP high density plasma
  • a contact tunnel 160 is etched into interlevel dielectric 150.
  • a center of contact tunnel 160 is aligned over a portion of interconnect 114.
  • contact tunnel 160 may include some overlap (represented in Fig. 8 as the displacement x 0 ).
  • the contact overlap results when a sidewall 162b of contact tunnel 160 extends beyond a boundary defined by the imaginary plane extending upward from sidewall 114 of interconnect structure 112.
  • Contact overlap may result from misalignment in the contact masking layer, misalignment in interconnect level 110. or from oversizing of contact tunnel 160 during either the photoresist exposed/develop sequence or during the subsequent etch process.
  • Contact overlap may also occur in situations in which the drawn dimension of contact tunnel 160 is larger than the lateral dimension of the underlying interconnect 112.
  • the presence of the spacer structure 140a upon sidewall 114 of interconnect structure 112 during the formation of contact tunnel 160 substantially prevents sidewall 114 from exposure to the contact tunnel formation process.
  • the presence of spacer structure 140 desirably prevents sidewall 114 of metal section 116a of interconnect structure 112 from being exposed to the fluorine bearing atmosphere.
  • metal section 116a may result in undercutting of the metal section 116a and may result in increased contact resistance thereby potentially reducing the long term reliability of the contact structure. In some cases, it has been observed that large portions of the exposed metal interconnect are missing after the contact etch.
  • adhesion layer 170 is preferably comprised of a refractory metal such as TiN.
  • the blanket deposition of plug material 172 comprises a chemical vapor deposition process during which WF 6 , and silane followed by hydrogen are reacted to produce a tungsten deposition.
  • contact plug 180 is completed by removing portions of adhesion layer 170 and plug material 172 from regions exterior to contact tunnel 160. In the presently preferred embodiment, the removal of excess adhesion layer and plug material is accomplished with a chemical mechanical polish or other suitable planarization process. The completion of the contact plug process results in the formation of an integrated circuit 190 which includes semiconductor substrate 100, interconnect level 110, spacer structure 140, interlevel dielectric 150, and contact plug 180. Interconnect layer 110 is formed on upper surface 101 of semiconductor substrate 100.
  • Interconnect layer 110 includes interconnect structure 112.
  • Interconnect structure 112 includes an interconnect sidewall 114.
  • Spacer structure 140 is formed in contact with sidewall 114 of interconnect structure 112.
  • Interlevel dielectric 150 is formed above interconnect layer 110.
  • Interlevel dielectric 150 includes a contact tunnel 160 (shown in Fig. 8).
  • a center of contact tunnel 160 is aligned over interconnect structure 112.
  • a perimeter or sidewall 162b of contact tunnel 160 may extend beyond a plane defined by interconnect sidewall 114 such that contact tunnel 160 overlaps interconnect structure 114.
  • Contact plug 180 fills contact tunnel 160.
  • the presence of spacer structure 140 upon interconnect sidewall 114 protects interconnect sidewall 114 from contact plug 180.
  • contact plug 180 includes a refractory metal outer shell 182 in contact with sidewalls 162 of contact tunnel 160 and further includes a conductive core 184.
  • refractory metal outer shell 182 comprises TiN and conductive core 184 comprises tungsten.

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Abstract

A semiconductor process in which a spacer structure (140) is fabricated on sidewalls (114) of an interconnect (116A) to protect sidewalls of the interconnect sidewalls from subsequent processing. An interconnect layer (102) is formed on an upper surface of a semiconductor substrate (100). The interconnect layer (102) includes an interconnect structure (116A) and the interconnect structure includes an interconnect sidewall (114). A spacer structure (140) is then formed on the sidewall (114) of the interconnect layer (116A) and an interlevel dielectric (150) is then deposited on the interconnect layer (116A). A contact tunnel (160) is thereafter formed into the interlevel dielectric (150). A center of the contact tunnel (160) is preferably aligned over the interconnect structure (116A). A perimeter of the contact tunnel (160) may overlap the underlying interconnect structure (116A). In other words, the perimeter of the contact tunnel may extend beyond a plane defined by the interconnect sidewall (114). Thereafter, the contact tunnel is plugged with a conductive material (184).

Description

TITLE: INTERCONNECT SPACER STRUCTURES
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to an improved method of coupling adjacent interconnect levels in a semiconductor process by forming spacer structures on the sidewalls of an interconnect level to minimize susceptibility to contact overlap.
2. Description of the Relevant Art
Integrated circuits include a large number of transistors fabricated into a monolithic semiconductor substrate. Isolation structures such as field oxides or shallow trench dielectrics are used to electrically isolate the individual transistors from one another. The transistors are then selectively coupled to other transistors to achieve a desired circuit through the use of patterned layers of conductive interconnect structures. In semiconductor processes employing multiple interconnect levels, each interconnect level is selectively coupled to a subsequentlv formed interconnect level. Multiple level interconnects enable greater functional complexity and can reduce the average interconnect length thereby minimizing the RC delay associated with the interconnects.
Each interconnect level typically includes a plurality of patterned interconnect structures comprised of a conductive material such as aluminum. Aluminum interconnects have a desirably high conductivity and adhere well to oxide, which is commonly used as an insulating layer in semiconductor processing. Unfortunately, forming fine line patterns from an aluminum layer using optical photolithographic techniques is difficult because of aluminum's high reflectivity. Optical energy rays reflected off the aluminum upper surface may produce standing waves within the photoresist during exposure and result in an undesirably ragged post-develop photoresist profile. To address tins problem, an anti-reflective coating (ARC) can be deposited on the aluminum layer prior to the photolithography/etch sequence. The ARC minimizes the energy reflected back to the energy source during exposure.
The coupling of adjacent interconnect levels in a multiple interconnect level process is typically accomplished by depositing an insulating material upon the existing interconnect level and forming via or tunnel structures through the insulating material to predetermined locations in the underlying interconnect level using well known photolithography and etch techniques. In many advanced process, the aspect ratios (i.e., the ratio of the vertical dimension to the lateral dimension) of these contact tunnels necessitate a dedicated processing sequence to fill or "plug" the contact tunnels with a conductive material before depositing and patterning the subsequent interconnect level. Chemically vapor deposited tungsten is an example of a commonly used material for plugging contact tunnels. Because tungsten exhibits poor adhesion to typically used insulating materials such as oxide, however, it is not uncommon to precede the tungsten deposition process with an adhesion layer deposition during which a thin adhesion layer, typically comprised of a refractory metal, is deposited on the sidewalls of the contact tunnel. As its name suggests, the adhesion layer exhibits good adhesion to both oxide and tungsten and therefore provides an adhesive interface between the tungsten plug and the oxide. Ideally, the contact tunnel sidewalls terminate entirely upon an upper surface of the underlying interconnect structure. This ideal condition occurs consistently, however, only if the lateral dimension of the underlying interconnect structure is greater than the contact tunnel lateral dimension by an amount equal to approximately twice the misalignment tolerance associated with the contact masking process (i.e., wmιn > raSct + 2 * δm, where \vmιn is the minimum interconnect width. wcontact is the width or lateral dimension of the contact tunnel, and δm is the misalignment tolerance associated with the contact mask photolithography process). Unfortunately, the width of interconnect structures found in multiple interconnect level, submicron semiconductor technologies is frequently less than wmm. When the width of the interconnect is less than wmm, the contact tunnel will "overlap" the interconnect structure. For purposes of this disclosure, contact overlap refers to the condition wherein the contact tunnel sidewalls do not terminate entirely on an upper surface of the underlying interconnect structure.
Contact overlap can be particularly problematic in semiconductor processes employing aluminum interconnects, antireflective coatings, and tungsten plugs. It will be appreciated to those skilled in the art that, when contact overlap exists, the contact etch process is capable of exposing a portion of the sidewall of the interconnect structure. If the contact etch process involves a carbon-fluorine plasma, the exposure of the interconnect sidewall during contact etch may undesirably expose the aluminum base of the interconnect structure to the carbon-fluorine plasma. The exposure of aluminum to a carbon-fluorine plasma may result in some undesirable undercutting of the aluminum and may introduce fluorine into the aluminum potentially degrading the long-term reliability of the interconnect structure. Referring to Fig. 1, an overlapping contact structure is shown. Interconnect 11 is formed on an upper surface of the semiconductor substrate 10. Interconnect 11 includes an aluminum base 12 and an antireflective coating 14 formed on upper surface of the aluminum base 12.
Interconnect 11 includes a pair of sidewalls 13a and 13b. Interlevel dielectric 16 includes a contact tunnel 18. Contact tunnel 18 includes a pair of sidewalls 20a and 20b. Contact tunnel 18 overlaps interconnect 11 by a distance x0 which represents the displacement between the second sidewall 20b and second sidewall 13b of interconnect 11. Because of this overlap, the etch process used to form contact tunnel 18 extends along second sidewall 13b of interconnect 1 1 thereby exposing a portion of the sidewall of the conductive base layer 12. In process sequences in which conductive base layer 12 comprises aluminum, it is typically undesirable to expose the aluminum during the contact tunnel etch process because the contact tunnel etch process may inadvertently undercut the aluminum and may undesirably introduce fluorine or other undesirable impurities into the aluminum during the etch process. In addition, it will be appreciated to those skilled in the art that a subsequent thin film deposition process, such as the deposition of an adhesion layer in connection with the fabrication of a tungsten plug, for example, is made more difficult by the narrow and deep geometry of the contact structure along the sidewall of interconnect structure 11. If an adhesion layer deposition process is unable to adequately cover the exposed aluminum alone sidewall 13B of interconnect 11 , the subsequent deposition of the plug material, which is typically carried out with a WF6 plasma, will further expose conductive base 12 of interconnect 11 to fluorine and may undesirably increase the contact resistance of the structure. As is well known, increased contact resistance can degrade the reliability of the integrated circuit.
Therefore, it would be highly desirable to implement a processing sequence in which an aluminum based interconnect level was made less susceptible to the processing variations associated with contact overlap.
SUMMARY OF THE INVENTION The problems identified above are in large part addressed by a semiconductor process in which spacer structures are fabricated on the sidewalls of an interconnect structure to minimize or eliminate the exposure of the interconnect sidewalls during a subsequent processing sequence. By eliminating susceptibility to contact overlap, the present invention improves circuit reliability and increases processing margins by adequately protecting the interconnect sidewalls from exposure during subsequent processing.
Broadly speaking, the present invention contemplates a semiconductor process in which an interconnect layer is formed on an upper surface of a semiconductor substrate. The interconnect layer includes an interconnect structure and the interconnect structure includes an interconnect sidewall. A spacer structure is then formed on the sidewall of the interconnect layer and an interlevel dielectric is then deposited on the interconnect layer. A contact tunnel is thereafter formed into the interlevel dielectric. A center of the contact tunnel is preferably aligned over the interconnect structure. A perimeter of the contact tunnel may overlap the underlying interconnect structure. In other words, the perimeter of the contact tunnel may extend beyond a plane defined by the interconnect sidewall. The presence of the spacer structure upon the interconnect sidewall during the contact tunnel formation substantially prevents the interconnect sidewall from exposure during the formation of the contact tunnel. Thereafter, the contact tunnel is plugged with a conductive material. The presence of the spacer structure on the interconnect sidewall during the plugging of the contact tunnel substantially prevents the conductive material from contacting the interconnect sidewall.
Preferably, the formation of the interconnect layer is accomplished by depositing a metal layer on an upper surface of the semiconductor substrate. The metal layer preferably comprises aluminum. Thereafter, an antireflective coating is deposited on an upper surface of the metal layer. Thereafter, the metal layer and the antireflective coating are patterned. The patterning of the metal layer and the antireflective coating is typically accomplished with a single photolithography/etch sequence. The antireflective coating is preferably a refractory metal such as titanium, molybdenum, platinum, palladium, nickel, or an alloy thereof in one presently preferred embodiment in which the conductive base layer comprises aluminum, the refractory metal comprises titanium nitride (TiN). Preferably, the spacer structures are comprised of either polysilicon or silicon nitride. The formation of the spacer structures includes the steps of chemically vapor depositing a spacer film on a topography defined by the interconnect layer and the semiconductor substrate. The topography includes planar regions that are substantially parallel to an upper surface of the semiconductor substrate. Thereafter, the spacer film is antisotropically etched until portions of the topography are removed. In an embodiment of the present invention in which the spacer film comprises silicon nitride, the chemical vapor deposition of the silicon nitride is accomplished by reacting silane and NH3 in a plasma enhanced C VD reactor chamber maintained at a temperature range of approximately 400 °C and a pressure of less than approximately 2 torrs. The deposition of the interlevel dielectric preferably comprises the process of decomposing TEOS in a C VD reactor chamber maintained at a temperature in the range of approximately 400° C and a pressure of less than approximately 2 torrs. The plugging of the contact tunnel preferably includes the steps of depositing an adhesion layer on sidewalls of the contact tunnel and depositing a plug material until the contact tunnel is filled. The adhesion layer comprises a refractory metal such as titanium, tungsten, molybdenum, palladium, platinum, nickel, and appropriate alloys thereof or other appropriate refractory metal. In an embodiment of the present invention in which the plug material comprises tungsten, the adhesion layer is preferably comprised of TiN deposited in a CVD reactor chamber.
The present invention further contemplates an integrated circuit including a semiconductor substrate, an interconnect layer, a spacer structure, an interlevel dielectric layer, and a contact plug. The interconnect layer is formed on an upper surface of the semiconductor substrate. The interconnect layer includes an interconnect structure and the interconnect structure includes an interconnect sidewall. The spacer structure is formed in contact with the sidewall of the interconnect structure. The interlevel dielectric layer is formed above the interconnect layer. The interlevel dielectric includes a contact tunnel. A center of the contact tunnel is preferably aligned over the interconnect structure. The contact tunnel may overlap the interconnect structure to some extent. In other words, a perimeter of the contact tunnel may extend beyond a plane defined by the interconnect sidewall. The contact plug fills the contact tunnel. The presence of the spacer structure upon the interconnect sidewall substantially protects the interconnect sidewall from the contact plug. Preferably the interconnect layer includes a metal layer formed on an upper surface of the semiconductor substrate and an antireflective coating formed on an upper surface of the metal layer. In a presently preferred embodiment, the metal layer comprises aluminum and the antireflective coating comprises a refractory metal. In an embodiment in which the interconnect layer comprises aluminum, the refractory metal is preferably comprised of titanium, molybdenum, platinum, palladium, nickel, and appropriate alloys thereof or other appropriate refractory metal. In one embodiment the spacer structure comprises either polysilicon or silicon nitride. The interlevel dielectric is preferably comprised of a CVD oxide such as an oxide formed from a TEOS source. In the preferred embodiment, the contact plug includes a refractory metal outer shell in contact with the sidewalls of the contact tunnel and the plug further includes a conductive core. In the preferred embodiment, the refractory metal outer shell comprises TiN and the conductive core comprises tungsten.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
Fig. 1 is a partial cross-sectional view of an interconnect structure and an overlapping contact tunnel:
Fig. 2 is a partial cross-sectional view of a metal layer formed on an upper surface of a semiconductor substrate:
Fig. 3 is a processing step subsequent to Fig. 2 in which an antireflective coating is formed on an upper surface of the metal layer,
Fig. 4 is a processing step subsequent to Fig. 3 in which the metal layer and the antireflective coating have been patterned to form and interconnect level on an upper surface of the semiconductor substrate;
Fig. 5 is a processing step subsequent to Fig. 4 in which a spacer film has been deposited over the interconnect level and the semiconductor substrate: Fig. 6 is a processing step subsequent to Fig. 5 in which the spacer material has been anisotropically etched to form a spacer structure on a sidewall of the interconnect structure;
Fig. 7 is a processing step subsequent to Fig. 6 in which an interlevel dielectric has been deposited over the interconnect level and the semiconductor substrate;
Fig. 8 is a processing step subsequent to Fig. 7 in which a contact tunnel has been formed in the interlevel dielectric;
Fig. 9 is a processing step subsequent to Fig. 8 in which an adhesion layer and a conductive plug material have been deposited onto the existing semiconductor topography; and
Fig. 10 is a processing step subsequent to Fig. 9 in which the conductive plug material and the adhesion layer have been planarized leaving a contact plug that fills the contact tunnel and provides a conductive path to the interconnect structure.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
DETAILED DESCRIPTION OF THE DRAWINGS
Turning now to the drawing, Figs. 2 through 10 disclose a preferred processing sequence for fabricating an interconnect level and a subsequent interconnect contact structure according to the present invention. Turning to Fig. 2. a conductive layer 102 is formed on upper surface 101 of semiconductor substrate 100. Semiconductor substrate 100 preferably includes a monocrystalline silicon substrate into which a plurality of transistors have been fabricated with well known transistor fabrication techniques. Semiconductor substrate 100 may further include one or more interconnect levels and one or more levels of entry level dielectric layers. Upper surface 101 of semiconductor substrate 100 suitably includes an upper portion of an insulating layer that isolates conductive layer 102 from previous interconnect levels and from the transistors within semiconductor substrate 100 and further includes selectively located conductive paths to existing interconnect levels. In a presently preferred embodiment, metal layer 102 is primarily comprised of aluminum possibly in combination with small amounts (i.e., < 5%) of copper, silicon or other suitable material. Metal layer 102 is typically deposited upon semiconductor substrate 100 with a physical vapor deposition or sputtering process using an aluminum or aluminum alloy target as is well known in the field of semiconductor processing.
Turning to Fig. 3, antireflective coating 104 is deposited upon an upper surface of metal layer 102. Antireflective coating 104 is used in conjunction with aluminum or other metal interconnect levels to improve the resolution obtainable with conventional photoresist masking techniques. If photoresist is deposited directly upon metal layer 102, the optical energy reflected back to the energy source by the conductive metal layer during the exposure of the photoresist results in undesirably ragged photoresist profiles that can negatively effect the critical dimensions and sidewall profile of the subsequently formed interconnect. In a preferred embodiment, antireflective coating 104 comprises a refractory metal. For purposes of this disclosure, a refractory metal refers to a metal or metal alloy comprising titanium, molybdenum, tungsten, palladium, platinum, nickel, appropriate alloys thereof, or other appropriate refractory metal. In an embodiment of the present invention in which metal layer 102 comprises aluminum, antireflective coating 104 is preferably comprised of sputter deposited titanium nitride (TiN) It will appreciated to those skilled in the art of sputter deposition processes that antireflective coating 104 is preferably deposited upon metal layer 102 in a single process step without breaking vacuum such that the semiconductor substrate is not exposed to atmosphere between the deposition of the metal and the deposition of the antireflective coating.
Turning to Fig. 4, an interconnect level 1 10 is formed by patterning conductive layer 102 and antireflective coating 104 using well known photolithography masking techniques. As will be appreciated to those skilled in the art of semiconductor processing, the patterning of metal layer 102 and antireflective coating 104 can typically be accomplished using a single photolithography/etch process sequence. Interconnect level 110 includes a first interconnect structure 112a and a second interconnect structure 112b. Each interconnect structure 112 includes a metal section 116 and an antireflective coating section 118. Each interconnect structure 112 further includes an interconnect sidewall 114.
Turning now to Fig. 5, a spacer material 130 is deposited upon the topography defined by interconnect level 110 and semiconductor substrate 100. Spacer material 130 includes a plurality of planar regions represented in Fig. 5 by reference numerals 132a and 132b. Planar regions, for purposes of this disclosure, refer to regions of the spacer layer substantially parallel to upper surface 101 of semiconductor substrate 100. To achieve a desirably conformal deposition, spacer material 130 is typically formed by a low pressure (i.e.. less than 2 torrs) chemical vapor deposition process. As its name suggests, spacer material 130 is intended to be used for the formation of spacer structures upon sidewalls 114 of interconnect structures 112, as described further below. The spacer structures will serve to protect sidewalls 114 from subsequent etch and deposition processes. For this reason, the preferred embodiment of the present invention contemplates a spacer material 130 comprised of silicon nitride. Silicon nitride is desirable as a spacer material in the present invention because silicon nitride is characteristically an excellent barrier to mobile contaminants. In other words, it is well known that mobile impurities or other contaminants cannot typically penetrate through a silicon nitride barrier layer. In an embodiment of the present invention in which spacer material 130 comprises silicon nitride, the silicon nitride is preferably deposited with a low temperature chemical vapor deposition process during which silane is reacted with NH3 at a temperature in the range of approximately 400 °C at a pressure of less than approximately 2 torrs. Although silicon nitride is an excellent barrier layer, the high dielectric constant associated with silicon nitride may undesirably increase parasitic capacity between adjacent interconnect structures 112. An alternative embodiment of the present invention contemplates a spacer material comprised of chemically vapor deposited polysilicon. In such an embodiment, the polysilicon is typically deposited by thermally decomposing silane in a CVD reactor chamber maintained at a temperature in the range of approximately 400 °C and a pressure of less than approximately two tours.
Turning now to Fig. 6, spacer structures 140 are formed on sidewalls 114 of the interconnect structures 112 by anisotropically etching spacer film 130 until planar regions 132 of spacer film 130 are removed. Removing the planar regions of a conformal film deposited over an underlying topography is typically accomplished with an anisotropic etch process using minimum overetch as is well known in the field of semiconductor processing.
Turning now to Fig. 7, an interlevel dielectric layer 150 is deposited over interconnect level 110 and semiconductor substrate 100. In a preferred embodiment, the deposition of interlevel dielectric 150 is accomplished by decomposing TEOS in a PEC VD chamber maintained at a temperature of approximately 400 °C and a pressure of less than approximately 2 torrs and following the deposition with a planarization process. The planarization process is designed to result in the formation of a substantially planar upper surface 151 of interlevel dielectric layer 150. Portions of interlevel dielectric layer 150 removed by the planarization process are shown in phantom in Fig. 7. Those skilled in the art of deposition and planarization processes will appreciate that suitable process sequences for fabricating and planarizing interlevel dielectric 150 may include, by way of example, a
TEOS CVD deposition process in combination with a chemical mechanical polish or a deposition and etch back of a spin-on glass. Another embodiment might include a high density plasma (HDP) deposition process in combination with a PECVD TEOS and an etchback.
Turning now to Fig. 8, a contact tunnel 160 is etched into interlevel dielectric 150. Preferably, a center of contact tunnel 160 is aligned over a portion of interconnect 114. Consistent with the present invention, contact tunnel 160 may include some overlap (represented in Fig. 8 as the displacement x0). The contact overlap results when a sidewall 162b of contact tunnel 160 extends beyond a boundary defined by the imaginary plane extending upward from sidewall 114 of interconnect structure 112. Contact overlap may result from misalignment in the contact masking layer, misalignment in interconnect level 110. or from oversizing of contact tunnel 160 during either the photoresist exposed/develop sequence or during the subsequent etch process. Contact overlap may also occur in situations in which the drawn dimension of contact tunnel 160 is larger than the lateral dimension of the underlying interconnect 112. In any event, the presence of the spacer structure 140a upon sidewall 114 of interconnect structure 112 during the formation of contact tunnel 160 substantially prevents sidewall 114 from exposure to the contact tunnel formation process. In embodiments of the present invention in which the formation of contact tunnel 160 is achieved using a carbon-fluorine oxide etch, the presence of spacer structure 140 desirably prevents sidewall 114 of metal section 116a of interconnect structure 112 from being exposed to the fluorine bearing atmosphere. It is believed that exposing metal section 116a to a fluorine bearing contact etch process may result in undercutting of the metal section 116a and may result in increased contact resistance thereby potentially reducing the long term reliability of the contact structure. In some cases, it has been observed that large portions of the exposed metal interconnect are missing after the contact etch.
Turning now to Fig. 9, the process of filling contact tunnel 160 is accomplished in a presently preferred embodiment with the sputter deposition of adhesion layer 170 and a subsequent CVD deposition of a plug material 172. In a presently preferred embodiment in which plug material 172 comprises tungsten, adhesion layer 170 is preferably comprised of a refractory metal such as TiN. In the preferred embodiment, the blanket deposition of plug material 172 comprises a chemical vapor deposition process during which WF6, and silane followed by hydrogen are reacted to produce a tungsten deposition. The presence of spacer structure 140 ensures that adhesion layer 170 will achieve an adequate step coverage and that the WF6 deposition process will not result in any inadvertent introduction of fluorine into the metal section 116a of interconnect 112. Turning now to Fig. 10, contact plug 180 is completed by removing portions of adhesion layer 170 and plug material 172 from regions exterior to contact tunnel 160. In the presently preferred embodiment, the removal of excess adhesion layer and plug material is accomplished with a chemical mechanical polish or other suitable planarization process. The completion of the contact plug process results in the formation of an integrated circuit 190 which includes semiconductor substrate 100, interconnect level 110, spacer structure 140, interlevel dielectric 150, and contact plug 180. Interconnect layer 110 is formed on upper surface 101 of semiconductor substrate 100. Interconnect layer 110 includes interconnect structure 112. Interconnect structure 112 includes an interconnect sidewall 114. Spacer structure 140 is formed in contact with sidewall 114 of interconnect structure 112. Interlevel dielectric 150 is formed above interconnect layer 110. Interlevel dielectric 150 includes a contact tunnel 160 (shown in Fig. 8). A center of contact tunnel 160 is aligned over interconnect structure 112. A perimeter or sidewall 162b of contact tunnel 160 may extend beyond a plane defined by interconnect sidewall 114 such that contact tunnel 160 overlaps interconnect structure 114. Contact plug 180 fills contact tunnel 160. The presence of spacer structure 140 upon interconnect sidewall 114 protects interconnect sidewall 114 from contact plug 180. Preferably, contact plug 180 includes a refractory metal outer shell 182 in contact with sidewalls 162 of contact tunnel 160 and further includes a conductive core 184. In their preferred embodiments, refractory metal outer shell 182 comprises TiN and conductive core 184 comprises tungsten.
It will be appreciated to those skilled in the art that the present invention contemplates reducing the susceptibility of underlying interconnect structures to contact overlap in multiple interconnect level submicron semiconductor processes. Various modifications and changes may be made to each and every processing step as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to regarded in an illustrative rather than a restrictive sense.

Claims

WHAT IS CLAIMED IS:
1. A semiconductor process comprising:
forming an interconnect layer on an upper surface of a semiconductor substrate, wherein said interconnect layer includes an interconnect structure, and wherein said interconnect structure comprises an interconnect sidewall;
forming a spacer structure on said sidewall of said interconnect layer;
depositing an interlevel dielectric on said interconnect layer;
forming a contact tunnel in said interlevel dielectric, wherein a center of said contact tunnel is aligned over said interconnect structure, and wherein a perimeter of said contact tunnel extends beyond a plane defined by said interconnect sidewall. and further wherein the presence of said spacer structure upon said interconnect sidewall during said forming of said contact tunnel substantially protects said interconnect sidewall from being undesirably removed during said forming of said contact tunnel: and
plugging said contact tunnel with a conductive material, wherein the presence of said spacer structure on said interconnect sidewall during said plugging substantially prevents said conductive material from contacting said interconnect sidewall.
2. The process of claim 1. wherein the step of forming said interconnect layer comprises:
depositing a metal layer on an upper surface of said semiconductor substrate, wherein said metal layer comprises aluminum;
depositing an antireflective coating on an upper surface of said metal layer; and
patterning said metal layer and said antireflective coating.
3. The process of claim 2, wherein said antireflective coating comprises a refractory metal.
4. The process of claim 3, wherein said refractory metal comprises titanium nitride.
5. The process of claim 1, wherein said spacer structures comprises a material selected from the group consisting of polysilicon and silicon nitride.
6. The process of claim 5, wherein the step of forming said spacer structures comprises: chemically vapor depositing a spacer film on a topography defined by said interconnect layer and said semiconductor substrate, wherein said topography comprises planar regions substantially parallel to an upper surface of said semiconductor substrate; and
anisotropically etching said spacer film until portions of said spacer film in said planar regions of said topography are removed.
7. The process of claim 7, wherein the step of chemically vapor depositing said silicon nitride comprises reacting silane and NH3 in a reactor chamber maintained at a temperature in the range of approximately 300 to
400 ┬░C and a pressure less than approximately 2 torrs.
8. The process of claim 6. wherein the step of depositing said interlevel dielectric comprises decomposing TEOS in a plasma enhanced chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 400 ┬░C and a pressure less than approximately 2 torrs.
9. The process of claim 1. wherein the step of plugging said contact tunnel comprises:
depositing an adhesion layer on sidewalls of said contact tunnel, wherein said adhesion layer comprises a refractory metal: and
depositing a plug material until said contact tunnel is filled.
10. The process of claim 9, wherein the step of depositing said adhesion layer comprises chemically vapor depositing TiN.
11. An integrated circuit comprising:
a semiconductor substrate;
an interconnect layer formed on an upper surface of said semiconductor substrate, wherein said interconnect layer includes an interconnect structure, and wherein said interconnect structure includes an interconnect sidewall;
a spacer structure in contact with said sidewall of said interconnect structure;
an interlevel dielectric formed above said interconnect layer, wherein said interlevel dielectric includes a contact tunnel, and wherein a center of said contact tunnel is aligned over said interconnect structure and further wherein a perimeter of said contact tunnel may extend beyond a plane defined by said interconnect sidewall;
a contact plug, wherein said contact plug fills said contact tunnel, and wherein the presence of said spacer structure upon said interconnect sidewall protects said interconnect sidewall from said contact plug.
12. The integrated circuit of claim 11. wherein said interconnect layer comprises a metal layer formed on said upper surface of said semiconductor substrate and an antireflective coating formed on an upper surface of said metal layer.
13. The integrated circuit of claim 12 wherein said metal layer comprises aluminum.
14. The integrated circuit of claim 12. wherein said antireflective coating comprises a refractory metal.
15. The integrated circuit of claim 14, wherein said refractory metal comprises titanium nitride.
16. The integrated circuit of claim 1 1, wherein said spacer structure comprises a material selected from the group consisting of polysilicon and silicon nitride.
17. The integrated circuit of claim 1 1, wherein said interlevel dielectric comprises oxide.
18. The integrated circuit of claim 1 1, wherein said contact plug includes a refractory metal outer shell in contact with sidewalls of said contact tunnel and a conductive core.
19. The integrated circuit of claim 18. wherein said refractory metal outer shell comprises TiN.
20. The integrated circuit of claim 18, wherein said conductive core comprises tungsten.
PCT/US1998/006887 1997-06-26 1998-04-07 Interconnect spacer structures WO1999000840A1 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444695A2 (en) * 1990-03-02 1991-09-04 Kabushiki Kaisha Toshiba Semiconductor device having multilayered wiring structure and method of manufacturing the same
EP0478308A2 (en) * 1990-09-25 1992-04-01 Kawasaki Steel Corporation Method of forming interlayer-insulating film
EP0568385A2 (en) * 1992-04-30 1993-11-03 STMicroelectronics, Inc. Method for forming contact vias in integrated circuits
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
EP0720227A2 (en) * 1994-12-29 1996-07-03 STMicroelectronics, Inc. Electrical connection structure on an integrated circuit device comprising a plug with an enlarged head

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444695A2 (en) * 1990-03-02 1991-09-04 Kabushiki Kaisha Toshiba Semiconductor device having multilayered wiring structure and method of manufacturing the same
EP0478308A2 (en) * 1990-09-25 1992-04-01 Kawasaki Steel Corporation Method of forming interlayer-insulating film
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same
EP0568385A2 (en) * 1992-04-30 1993-11-03 STMicroelectronics, Inc. Method for forming contact vias in integrated circuits
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
EP0720227A2 (en) * 1994-12-29 1996-07-03 STMicroelectronics, Inc. Electrical connection structure on an integrated circuit device comprising a plug with an enlarged head

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ARAI H ET AL: "EFFECT OF AMMONIA PLASMA TREATMENT ON PLASMA DEPOSITED SILICON NITRIDE FILMS/SILICON INTERFACE CHARACTERISTICS", 1 May 1988, JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, VOL. 6, NR. 3, PAGE(S) 831 - 834, XP000083872 *

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