WO1995034914A1

WO1995034914A1 - High temperature, high holding current semiconductor thyristor

Info

Publication number: WO1995034914A1
Application number: PCT/US1995/007357
Authority: WO
Inventors: Richard E. Nelson; Samuel A. Johnson
Original assignee: Beacon Light Products, Inc.
Priority date: 1994-06-10
Filing date: 1995-06-09
Publication date: 1995-12-21
Also published as: AU2702195A

Abstract

A semiconductor thyristor structure (10) comprises transistors (18, 20, 22, 24, 28, 30) formed by a plurality of regions of alternating N doped (42, 46, 48, 44) and P doped (38, 40) semiconductive material. At least one interior region (38, 40) is doped with an outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter to obtain an upper operating temperature of at least 200 °C, and a holding current in excess of 30 milliamps with a gate trigger current in excess of 20 milliamps. A more sensitive embodiement has a gate trigger current in the range of 1 to 5 milliamps obtained by dividing the interior regions into two segments (62, 64), doping the first segment (64) with at least 10 to the 17th carriers per cubic centimeter, and doping the second segment (62) with less than 10 to the 17th carriers per cubic centimeter.

Description

HIGH TEMPERATURE, HIGH HOLDING CURRENT SEMICONDUCTOR THYRISTOR

This invention relates to a new and improved semiconductor thyristor, such as a triac or an SCR, which functions at relatively high operating temperatures, for example in excess of 200 degrees Celsius (°C) , compared to the common upper working temperature limit of about 125 °C. This invention also relates to a new and improved semiconductor thyristor which has a relatively high holding current, allowing it to be used advantageously in certain new circuit applications, such as that described in U.S. Patent Application for "Solid State Starter For Fluorescent Lamp", Serial No. 08/258,007, filed concurrently herewith, and assigned to the assignee hereof. This invention also relates to a new and improved high operating temperature semiconductor thyristor which has a relatively high holding current and a relatively low gate trigger current, thereby preserving triggering sensitivity. Background of the Invention

The typical semiconductor thyristor, an SCR or a triac, can be thought of as an amplifier with a gain so high that it in essence behaves as a switch. An input signal applied at a gate terminal of the thyristor turns it on maximally and creates, in essence, a short circuit or switch-like effect between its two power terminals. An SCR conducts current in only one direction between its power terminals, while a triac conducts currents in both directions between its power terminals. A conductive thyristor exhibits a very small resistance between the power terminals until the thyristor turns off or becomes non-conductive, at which time the resistance between the power terminals becomes extremely high.

A typical way to turn off or commutate the thyristor to the non-conductive condition is by momentarily ceasing the flow of current through the power terminals. Because of this commutation characteristic thyristors are frequently used in alternating current (AC) circuits during a portion of each half cycle of applied AC power and allowing the zero crossing between sequential alternating half cycles to naturally commutate the thyristor. At the zero crossing point the current flow through the thyristor momentarily ceases before it reverses, thereby commutating the thyristor to the off condition.

The minimum current flow which will sustain a conductive condition of the thyristor is known as the holding current. So long as the current conducted through the thyristor is greater than the holding current, the thyristor will remain conductive. Once the current through the thyristor power terminals diminishes below the holding current level, the thyristor will inherently commute to the off or nonconductive condition, even through the current is not at a zero level. The fact that each thyristor has holding current characteristics is an indication of the departure of actual performance from the theoretical performance represented by a zero holding current.

Efforts at enhancing the performance of semiconductor thyristors have focused primarily on increasing their sensitivity to smaller and smaller triggering currents or signals. Greater sensitivity associated with smaller triggering currents is desirable in many applications because of the low current drive capabilities of the logic and other circuits which supply the trigger signals and because of the desire to conserve power by consuming no more than is absolutely necessary in any circuit. As an inherent result of the greater sensitivity to reduced level triggering currents, the holding current levels of the thyristor also diminish. The reduced holding current has also been viewed as a positive development, because of the closer resemblance of the actual operation to the theoretical commutation at a zero current conductive level. The conductivity characteristics of semiconductor thyristors, like all semiconductor devices, are related to temperature. At higher temperatures, semiconductive materials become more conductive. The carriers or the ionic elemental constituents located in the lattice of the semiconductive material, typically silicon, become more mobile and active as the temperature increases. When the temperature-induced mobility of these ionic carriers increases to the point where the barriers and boundaries between different regions of the semiconductor device are no longer maintained, the semiconductor device ceases to function on a reliable basis. For this reason, most semiconductor devices have a specified temperature range for effective operation. A typical upper temperature range for a high quality semiconductive device is approximately 125 °C. At temperatures greater than 125 °C the device may not function or function reliably.

One of the popular uses for semiconductor thyristors is to control lighting products. Thyristors are employed to control the current flow through a lamp and thereby change the illumination of the lamp. However, many lighting products which use incandescent lamps generate considerable heat when in use. If the lighting control device is integrated with the lamp or in close proximity with the lamp in a light fixture, the heat generated may adversely affect the performance of the thyristor. For example, one of the products developed by the assignee is a small semiconductor controller which fits within a conventional screw-in incandescent lamp socket between the power contacts and the screw shell of the incandescent lamp. In this environment, the operating temperature may increase to a level greater than 125 °C, thereby adversely limiting the ability to use thyristors to the extent desired.

It is with respect to these considerations and others, that the present invention has evolved.

Summary of the Invention One of the important aspects of the present invention relates to a semiconductor thyristor which has the characteristic capability of operating reliably and consistently at relatively high temperatures, for example in excess of 200 °C. Another important aspect of the present invention relates to a semiconductor thyristor which has a relatively high characteristic holding current that can be advantageously used in certain circuit applications. A further important aspect of the present invention relates to a semiconductor thyristor which has a low-level, high-sensitivity gate triggering characteristic along with characteristics of relatively high holding current and relatively high operating temperatures. In accordance with these and other aspects, the present invention relates to a semiconductor thyristor structure which comprises transistors formed by a plurality of regions of alternating N doped and P doped semiconductive material. At least one interior region is doped with a predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter, and preferably 10 to the 19th carriers per cubic centimeter to obtain a predetermined upper operating temperature of at least 200 °C, and preferably in excess of 205 °C. The semiconductor thyristor structure has a predetermined holding current in excess of 30 milliamps and preferably up to 50 milliamps or greater, and has a predetermined gate trigger current in excess of 20 milliamps and preferably up to about 30 milliamps in one embodiment. A more sensitive embodiment has a gate trigger current in the range of 1 to 5 milliamps which is obtained by dividing an interior region into two segments, and doping the first segment with the predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter and doping the second segment with a predetermined carrier concentration of less than 10 to the 17th carriers per cubic centimeter. This increases the holding current to in excess of 50 milliamps and preferably up to 100 milliamps or greater. In accordance with the above and other aspects, the present invention also relates to a method of constructing a high operating temperature, high holding current semiconductor thyristor structure having a predetermined upper operating temperature is in excess of 200 °C and a predetermined holding current in excess of 30 milliamps. The method involves the steps of alternately N doping and P doping a plurality of regions of semiconductive material to form a plurality of transistors connected in the thyristor structure; and doping at least one interior region to achieve a predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter, and preferably 10 to the 19th carriers per cubic centimeter, to obtain a predetermined upper operating temperature of at least 200 °C. Preferably the doping of the interior region obtains a predetermined holding current in excess of 30 milliamps. One of the interior regions may be divided into a first segment and a second segment, and the first segment may be doped with said predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter, and the second segment may be doped with a predetermined carrier concentration of less than 10 to the 17th carriers per cubic centimeter to obtain gate currents in the range of 1 to 5 milliamps, if greater sensitivity of the thyristor structure is desired, while increasing the holding current to in excess of about 50 milliamps and preferably to 100 milliamps or greater. A more complete appreciation for the present invention and its scope may be obtained from understanding the accompanying drawings, which are briefly summarized below, the following detailed description of presently preferred embodiments of the invention, and the appended claims. Brief Description of the Drawings

Fig. 1 is a schematic diagram of a triac embodying the present invention.

Fig. 2 is a top plan view of a semiconductor structure showing an exemplary construction of the triac shown in Fig. 1. Fig. 3 is a full thickness section view of the semiconductor structure shown in Fig. 2, taken substantially in the plane of line 3-3 of Fig. 2.

Fig. 4 is a full thickness section view of the semiconductor structure shown in Fig. 2, taken substantially in the plane of line 4-4 of Fig. 2.

Fig. 5 is an exploded perspective view of the semiconductor structure shown in Figs. 2, 3 and 4, showing its separate layers or regions and other components. Fig. 6 is a graph showing different diffusion concentrations of carriers within portions of the semiconductor structure shown in Figs. 2, 3, 4 and 5.

Fig. 7 is another perspective view, similar to that shown in Fig. 5, showing an alternative embodiment of another semiconductor structure for a triac embodying the present invention.

Detailed Description The discrete components of a semiconductor triac 10 are shown in Fig. 1. A gate terminal 12 receives a triggering signal, and in response thereto, the triac 10 conducts current between two main power terminals 14 and 16. A PNP transistor 18 and a NPN transistor 20 are electrically connected between the power terminals 14 and 16. The transistors 18 and 20 form an SCR structure which, when triggered, conducts current from a positive terminal 16 to a negative terminal 14. A PNP transistor 22 and a NPN transistor 24 are also connected between the terminals 14 and 16. The transistors 22 and 24 form another SCR structure which conducts current from a positive terminal 14 to a negative terminal 16 when triggered. . Thus, the triac 10 is, and achieves its functionality through, two parallel, reversely-polled SCRs. The triac 10 also includes a gate structure 26 formed in part by a NPN transistor 28 and a PNP transistor 30. In the particular configuration of the triac 10 shown in Fig. 1, a negative trigger signal applied on the gate terminal 12 triggers the triac 10 into conduction. The transistor 28 amplifies the trigger signal and applies it to the SCR structures formed by transistors 18, 20, 22 and 24. The transistor 30 is not used for negative gate triggering, but would be employed to respond to positive triggering signals, by circuit connections not shown.

Four resistors, 32, 34, 36 and 37 are employed in the triac 10. The resistor 32 is connected between the terminal 14 and a node 40 which serves as the collector for transistor 18 and the base of transistor 20. The resistor 34 is connected between the terminal 16 and a node 38 which serves as the base of transistor 24, and the collectors of transistors 22 and 30. A node 42 serves as the emitters of transistors 20 and 22 and is also connected to the terminal 14. A node 44 serves as the emitters of transistors 18 and 24 and is connected to the terminal 16. A node 46 serves as the emitter of transistor 28 and is connected to the gate terminal 12. The resistor 36 is connected between the nodes 46 and a node 47. The node 47 serves as the base of transistor 28 and the emitter of transistor 30. The resistor 37 is connected between the nodes 40 and 47. The resistances 32, 34, 36 and 37 are achieved by doping segments of the semiconductor material between nodes 40 and 42, between nodes 38 and 44, between nodes 46 and 47, and between nodes 40 and 47, respectively. A last node 48 serves as the collector of transistor 28, the bases of transistors 18, 22 and 30 and the collectors of transistors 20 and 24.

The triac 10 becomes conductive in response to a negative trigger signal applied at the gate terminal 12. The negative gate signal forward biases transistor 28 and reduces the voltage at node 48. If the trigger signal is applied at a time when the terminal 14 is positive with respect to terminal 16, transistor 22 is biased slightly on, and it conducts amplified current from terminal 14 and through the resistor 34 to the terminal 16. The current flowing through resistor 34 increases the base drive current on transistor 24, thereby causing it to become conductive. The conductive transistor 24 increases the base drive current to transistor 22 and causes it to become more conductive. These conductive characteristics of the transistors 22 and 24 create positive feedback base drive current which instantly causes both transistors 22 and 24 to reach a fully-conductive, saturated condition. Current is thereby conducted in an essential short circuit from terminal 14 to terminal 16. On the other hand, if the trigger signal is applied at a time when the terminal 16 is positive with respect to terminal 14, the lowered voltage at node 48 biases transistor 18 slightly on, and it conducts amplified current from terminal 16 and through the resistor 32 to the terminal 14. The current flowing through resistor 32 increases the base drive current on transistor 20, thereby causing it to become conductive. The conductive transistor 20 increases the base drive current to transistor 18 and causes it to become more conductive. These conductive characteristics of the transistors 18 and 20 create positive feedback base drive current which instantly causes both transistors 18 and 20 to reach a fully-conductive, saturated condition. Current is thereby conducted in an essential short circuit from terminal 16 to terminal 14. The fully conductive resistance through the transistors 22 and 24 or 18 and 20 is very small, for example about 2 ohms, thus establishing the short circuit condition between the terminals 14 and 16 in response to current flowing in either direction.

An SCR structure is essentially the same as that of the triac 10, except that only the pair of the transistors 18 and 20 or the pair of transistors 22 and 24 is employed. Thus an SCR structure will conduct current in only one direction between its power terminals. The present invention is equally applicable to SCRs as to triacs, but for purposes of convenience in description, only the structure of the triac 10 is described below. One of numerous possible implementations of a semiconductor structure 50 for the triac 10 is shown in Figs. 2, 3, 4 and 5. The triac semiconductor structure 50 is preferably formed of silicon material using conventional and well known semiconductor manufacturing techniques, except in the cases specifically noted below. The elements of the transistors and the resistors shown in Fig. 1 are formed in distinct layers in the structure 50, as shown best in Figs. 3 and 4. The triac structure 50 is a multi-layer or multi- region device. The interface between the node region 44 and the node region 38 forms the base emitter junction of transistor 24. A portion of the region 38 also forms the resistor 34. The interface between the node region 48 and the node region 44 forms the emitter base junction of transistor 18. The interface between the node region 38 and the node region 48 forms the collector base junctions of transistors 22, 24 and 30. The interface between the node regions 40 and 48 forms the collector base junctions of transistors 18 and 20. The interface between the node region 48 and the node region 42 forms the emitter base junction of transistors 22. The interface between the node regions 40 and 42 forms the emitter base junction of transistor 20. A portion of the node region 40 also forms the resistor 32. The interface of the node regions 46 and 47 forms the emitter base junction of transistor 28. A portion of the node region 46 or 47 forms the resistor 36. The interface of the node regions 47 and 48 forms the emitter base junction of transistor 30. A portion of the node regions 40 and 47 form the resistor 37, which is a lateral resistance.

The power terminal 16 is formed as a bottom metal layer, preferably of aluminum, titanium, nickel and gold. The other power terminal 14 is a top metal layer, preferably of aluminum.

These regions of the triac semiconductor structure 50 are referred to by the terms "N+" to designate a highly doped concentration of negative ionic carriers diffused within the silicon lattice, "N-" to designate a lightly doped concentration of negative ionic carriers within the silicon lattice, "P+" to designate a highly doped concentration of positive ionic carriers (holes) in the silicon lattice, or "P-" to indicate a lightly doped concentration of positive ionic carriers in the silicon lattice.

The node region 44 is N+. The node region 38 is P+. The node region 48 is N-. The node region 40 is formed as P+. The node region 42 is N+. The node region 46 is also formed as N+. The node region 47 is formed as a lateral resistance of the node regions 40 to 47. The N- and N+ regions are preferably formed by diffusing or doping lesser and greater amounts of phosphorus, respectively, into the silicon lattice. The P- and P+ regions are preferably formed by diffusing or doping lesser and greater amounts of boron, respectively, into the silicon lattice.

The process for building the semiconductor triac chip 50 begins with doping pure silicon an N- starting material 48 having approximately 10 to the 14th carriers per cubic centimeter. Thereafter, P+ material is diffused from both the top and bottom surfaces isolating the N- starting material 48. This P+ diffusion forms a wraparound diffusion 52 and a high concentration of P+ in the node regions 38 and 40.

The diffusion of the P+ extends to a depth of about 30 microns at the interface between the regions 38 and 48 and between the regions 40 and 48, as shown in Fig. 6. The P+ doping achieves a very high carrier concentration of at least 10 to the 17th and preferably 10 to the 19th carriers per cubic centimeter at the outer surface of the regions 38 and 40, located at a depth of about 10 microns as is also shown in Fig. 6. The diffusion carrier concentration of P+ is shown by a graph segment 54 which extends from the 10 to

30 micron depth as shown in Fig. 6. The concentration of

P+ forming the regions 38 and 40 extends from 10 to the 14th carriers per cubic centimeter at about a 30 micron depth up to at least 10 to the 17th, and preferably about 10 to the 19th, carriers per cubic centimeter at the 10 micron depth. This carrier concentration results in sheet resistances in the neighborhood of 10 ohms per square. This high concentration of P+ carriers in the node regions 38 and 40 achieves the desirable high temperature and high holding current characteristics.

The typical diffusion profile for the regions 38 and 40 in a conventional thyristor is substantially less than that of the present invention, for example about 10 to the 15th carriers per cubic centimeter at the surface of the node materials 38 and 40, with an Err function per micron depth and resulting in sheet resistances of about 300 ohms per square or greater. The typical prior art carrier concentration is shown by the graph segment 56 in Fig. 6. The considerably higher concentration of P+ carriers in the regions 38 and 40, as shown by comparing the graph segments 54 and 56 in Fig. 6, obtains significant improvements in high temperature functionality. With the higher P+ carrier concentrations described, the upper operating temperature limit is raised to over 200 °C, and more specifically to about 205 °C. The typical prior carrier concentrations described result in an upper operating temperature limit of only about 125 °C.

By increasing the P+ carrier concentration to in excess of 10 to the 17th carriers per cubic centimeter at the surface of regions 38 and 40, the resistivity of the region 40 is substantially reduced. The reduced resistivity causes the induced temperature activity of the ionic material to have a lesser effect, thus preserving the intended functionality of the thyristor at high temperatures. In other words, the reduced resistivity of the material by the higher carrier concentrations creates more immunity to high temperature effects.

Next, N+ is diffused in the regions 42, 44 and 46 after the high diffusion of P+ carriers in the regions 38 and 40. Of course, the semiconductor material is etched to define separate geometric regions and photo glass 58 is employed to insolate those geometric regions and to prevent diffusion into undesired regions while completing the triac structure 50. As shown in Fig. 6, the carrier concentration of N+ material in nodes 42, 44 and 46 ranges from 10 to the 17th to 10 to the 20th, from the 10 micron depth to the surface of the structure 50.

The resistors 32, 34, 36 and 37 are also formed at the time the interface is formed between the regions 38 and 40 and the regions 42, 44 and 46. The resistors 32, 34 and 36 are formed by selectively diffusing P+ material into the regions which shunt the base emitter junctions of the transistors 20, 24 and 28, respectively. The resistor 37 is formed by diffusing P+ material as a lateral resistance of the node regions 40 to 47.

The heavy concentration of the P+ material in the resistors 32, 34, 36 and 37 has the effect of increasing the holding current of the triac. The holding current is inherently increased by the higher carrier concentrations of the P+ material in the nodes 38 and 40, but the use of the resistors 32, 34, 36 and 37 further increases this holding current. Since the holding current is proportional to V_t divided by the sheet resistance (V_t is approximately .7 volts for silicon), the lower sheet resistance of the P+ material of the resistors 32, 34, 36 and 37 results in a higher holding current.

The emitter diffusions for the transistors 20, 24 and 28 should also be high in doping concentration. For example, sheet resistances of .6 ohms per square and surface concentration of carriers in the order of 10 to the 20th carriers per cubic centimeter are effective for the emitter diffusions of the transistors 20, 24 and 28. Furthermore, due to the characteristics of the diffusion profile, the holding current is relatively independent of temperature with the present invention. The increased holding current may be used to advantage in some applications such as that described in the aforementioned application Serial No. 08/258,007, assigned to the assignee hereof.

To complete the semiconductor structure 50, the metal terminals 12, 14 and 16 are deposited on the exposed surfaces of the node materials 46 and 47, 40 and 42, and 38 and 44, respectively.

By constructing a triac in accordance with the above description, satisfactory operation has been obtained up to 205 °C. Gate trigger currents in the range of 20 to 30 milliamps and holding currents in the neighborhood of 40 milliamps plus have been obtained, while maintaining blocking voltages of greater than 600 volts and achieving an on conductive resistance (between terminals 14 and 16) of less than 2 ohms. It is not believed that other triacs have obtained such high operating temperatures yet maintained reasonable gate currents and high holding currents.

The described triac has been constructed on a chip 42 mills square. However, selective diffusion profiles of the present invention can be applied to other triac geometries such as center fired thyristors.

The high temperature, high holding current characteristics of the triac structure 50 are accompanied by an increase in the current required to trigger the triac. In some situations, it may be desirable to retain the low gate current triggering characteristics associated with more sensitive operation, while still obtaining high operating temperature and high holding current operational characteristics.

The high temperature, high holding current characteristics can be obtained while not substantially degrading the sensitivity of the gate, by employing the triac structure 60 shown in Fig. 7. This triac structure 60 is essentially the same as that described in

Figs. 2, 3, 4 and 5 except that the P+ region 40 is separated into one segment 62 which underlies the terminal metal 14 and another segment 64 which underlies the N+ of the node region 46. The segment 62 of the P+ region 40 which underlies the metal power terminal 14 may be diffused with a carrier concentration greater than 10 to the 19th, resulting in a sheet resistance of approximately 6 ohms per square. The segment 64 of the P+ region 40 and 47 underlying the N+ node region 46 at the gate should be diffused with carriers at approximately a depth of 11 microns to be less than 10 to the 17th. The carrier concentration under the N+ node region 46 is shown at 66 in Fig. 6, and the carrier concentration under the P+ node region 40 is shown at 68 in Fig. 6. Under these conditions, expected gate sensitivity currents are in the range of 1 to 5 milliamps and holding currents are in the neighborhood of at least 50 milliamps and preferably 100 milliamps or greater.

The high temperature and high holding current characteristics of both thyristor structures 50 and 60 are obtained while maintaining relatively high blocking or withstand voltages of greater than 600 volts and typical on-state resistances of less than 2 ohms. The high blocking voltages are obtained by the timeliness of the regions 38, 40 and 48 which can be maintained while still achieving the other desirable characteristics of high temperature operation, high holding current and high sensitivity, low trigger currents.

A presently preferred embodiment of the invention and its improvements have been described above with a degree of particularity. This description has been made by way of preferred example. It should be understood, however, that the scope of the present invention is defined by the following claims, and is not necessarily limited by the description of the preferred embodiment.

Claims

THE INVENTION CLAIMED IS:

1. A semiconductor thyristor structure comprising transistors formed by a plurality of regions of alternating N doped and P doped semiconductive material, in which at least one interior region is doped with a predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter to obtain a predetermined upper operating temperature of at least 200 °C.

2. A semiconductor thyristor structure as defined in claim 1 wherein the predetermined carrier concentration is in the range of 10 to the 17th to 10 to the 19th carriers per cubic centimeter.

3. A semiconductor thyristor structure as defined in claim 1 wherein the predetermined carrier concentration is approximately 10 to the 19th carriers per cubic centimeter.

4. A semiconductor thyristor structure as defined in claim 1 wherein the predetermined upper operating temperature is in excess of 200 °C.

5. A semiconductor thyristor structure as defined in claim 1 having a predetermined holding current in excess of 30 milliamps.

6. A semiconductor thyristor structure as defined in claim 5 wherein the predetermined holding current is in the range of 30 to 50 milliamps.

7. A semiconductor thyristor structure as defined in claim 1 having a predetermined holding current in excess of 50 milliamps.

8. A semiconductor thyristor structure as defined in claim 1 wherein at least two of the interior regions are each doped with the predetermined carrier concentration.

9. A semiconductor thyristor structure as defined in claim 8 having five regions, in which an innermost region is doped N, said two interior regions are doped P and each of said interior regions interfaces with the innermost region on respectively opposite sides of the inner region, and two outermost regions are doped N and each outermost region interfaces with one said inner region on a side of the inner region which is opposite of the side which interfaces with the innermost region.

10. A semiconductor thyristor structure as defined in claim 9 having a predetermined trigger current in excess of

20 milliamps.

11. A semiconductor thyristor structure as defined in claim 9 having a predetermined trigger current in the range of 10 to 20 milliamps, a predetermined holding current in excess of 50 milliamps.

12. A semiconductor thyristor structure as defined in claim 9 wherein one of the interior regions is divided into two segments, and a first one of the segments is doped with said predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter and a second one of said segments is doped with a predetermined carrier concentration of less than 10 to the 17th carriers per cubic centimeter.

13. A semiconductor thyristor structure as defined in claim 12 wherein the first one of the segments is doped with a carrier concentration of at least 10 to the 19th carriers per cubic centimeter.

14. A semiconductor thyristor structure as defined in claim 13 wherein the thyristor has a gate terminal and first and second power terminals, and a first transistor and a second transistor are connected between the power terminals with an emitter of each of the first and second transistors electrically connected to a different power terminal, with a base of the first transistor connected to a collector of the second transistor, and with a base of the second transistor connected to a collector of the first transistor, and wherein one interior region forms the base of the first transistor and the collector of the second transistor.

15. A semiconductor thyristor structure as defined in claim 14 wherein a first resistor is connected between the first power terminal and the base of the second transistor.

16. A semiconductor thyristor structure as defined in claim 15 wherein a third transistor and a fourth transistor are connected between the power terminals with an emitter of the third transistor connected to the first power terminal and an emitter of the fourth transistor connected to the second power terminal, with a base of the third transistor connected to a collector of the fourth transistor, and with a base of the fourth transistor connected to a collector of the third transistor, and with a second resistor is connected between the base of the fourth transistor and the second power terminal, the other interior region forms the collector of the fourth transistor and the base of the third transistor, and the one interior region also forms the emitter of the fourth transistor and the other interior region also forms the emitter of the first transistor.

17. A semiconductor thyristor structure as defined in claim 16 wherein the innermost region forms the bases of the first and third transistors and the collectors of the second and fourth transistors, the outermost regions forms the emitters of the first, second, third and fourth transistors, and the first and third transistors are PNP transistors and the second and fourth transistors are NPN transistors.

18. A semiconductor thyristor structure as defined in claim 17 wherein a fifth transistor forms a gate structure with an emitter connected to the gate terminal, with a base connected to the collector of the first transistor, to the base of the second transistor and to the emitter of the third transistor, and with a collector connected to the bases of the first and third transistors and the collectors of the second and fourth transistors, and the fifth transistor is a NPN transistor.

19. A method of constructing a relatively high operating temperature, high holding current semiconductor thyristor structure, comprising the steps of: alternately N doping and P doping a plurality of regions of semiconductive material to form a plurality of transistors connected in the thyristor structure; and doping at least one interior region to achieve a predetermined outer surface carrier concentration of at least 10 to the 17th carriers per cubic centimeter to obtain a predetermined upper operating temperature of at least 200 °C.

20. A method as defined in claim 19 further comprising: doping the at least one interior region to obtain the predetermined carrier concentration in the range of 10 to the 17th to 10 to the 19th carriers per cubic centimeter.

21. A method as defined in claim 19 further comprising: doping the at least one interior region to obtain the predetermined carrier concentration of approximately 10 to the 19th carriers per cubic centimeter. having a predetermined holding current in excess of 30 milliamps.

22. A method as defined in claim 19 further comprising: doping the at least one interior region to obtain a predetermined holding current in excess of 50 milliamps.

23. A method as defined in claim 19 further comprising:

P doping two interior regions with the predetermined carrier concentrations; N doping an innermost region between the two interior regions; and

N doping an outermost region to the exterior of each inner region.

24. A method as defined in claim 23 further comprising: dividing one of the interior regions into a first segment and a second segment; doping the first segment with said predetermined outer surface carrier concentration of at least 10 to the 17th carriers per. cubic centimeter; and doping the second segment with a predetermined carrier concentration of less than 10 to the 17th carriers per cubic centimeter.

25. A method as defined in claim 24 further comprising: doping the first segment with a predetermined carrier concentration of at least 10 to the 19th carriers per cubic centimeter.

26. A method as defined in claim 19 wherein the thyristor has a gate terminal and first and second power terminals, said method further comprising: forming first, second, third, and fourth transistors by the innermost, interior and outermost regions, each of the transistors having an emitter, a base and a collector; forming first and second resistors in the regions of the structure; connecting the emitters of the first and fourth transistors to the second terminal; connecting the emitters of the second and third transistor to the first terminal; connecting the bases of the first and third transistors to the collectors of the second and fourth transistors; connecting the base of the second transistor through the first resistor to the first power terminal; connecting the collector of the first transistor to the base of the second transistor in the first interior region; and connecting the collector of the third transistor to the base of the fourth transistor in the second interior region.

27. A method as defined in claim 26 further comprising: forming a fifth transistor which has an emitter, a base and a collector by the innermost, interior and outermost regions; forming a third resistor in the regions of the structure; connecting the emitter of the fifth transistor to the gate terminal; connecting the third resistor between the base of the fifth transistor and the collector of the first transistor; and connecting the collector of the fifth transistor to the bases of the first and third transistors.