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WO1995025352A1 - Eprom flash a masse virtuelle avec des regions d'oxyde a epaisseur diminuee - Google Patents

Eprom flash a masse virtuelle avec des regions d'oxyde a epaisseur diminuee Download PDF

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Publication number
WO1995025352A1
WO1995025352A1 PCT/US1995/000654 US9500654W WO9525352A1 WO 1995025352 A1 WO1995025352 A1 WO 1995025352A1 US 9500654 W US9500654 W US 9500654W WO 9525352 A1 WO9525352 A1 WO 9525352A1
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WO
WIPO (PCT)
Prior art keywords
array
oxide regions
field oxide
layer
regions
Prior art date
Application number
PCT/US1995/000654
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English (en)
Inventor
Graham R. Wolstenholme
Albert M. Bergemont
Etan Shacham
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Publication of WO1995025352A1 publication Critical patent/WO1995025352A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

  • the present invention relates to electrically programmable read-only-memories (EPROMs) and, in particular, to a virtual-ground flash EPROM that utilizes reduced-step-height field oxide regions in the array.
  • EPROMs electrically programmable read-only-memories
  • virtual-ground flash EPROM that utilizes reduced-step-height field oxide regions in the array.
  • EPROM electrically programmable read-only-memory
  • EEPROM electrically-erasable programmable read-only-memories
  • FIG. 1 shows a plan view that illustrates a portion of a "virtual-ground" flash EPROM array 10, such as the array described in U.S. Application Serial No. 07/988,293, filed by Albert Bergemont on December 8, 1992, titled HIGH DENSITY CONTACTLESS FLASH EPROM ARRAY USING CHANNEL ERASE.
  • array 10 includes a series of memory cells 12, a series of access transistors 14, and a series of field oxide regions FOX which separate both the vertically-adjacent memory cells and access transistors of the array.
  • each memory cell 12 and each access transistor 14 in a column of memory cells and access transistors shares a source bit line SOURCE and a drain bit line
  • a series of metal bit line contacts MBLl-MBLn in FIG. 1 are utilized to contact the drain bit lines DRAIN so that each drain bit line DRAIN is contacted by one metal bit line MBL once every n cells where n is typically 32, 64, or 128.
  • the source bit lines SOURCE are not contacted by a metal bit line.
  • FIG. 2 shows a cross-sectional diagram taken along lines 1A-1A of FIG. 1 that illustrates the structure of an individual memory cell 12.
  • each memory cell 12 includes a layer of tunnel oxide 16, a floating gate 18 which is formed over the layer of tunnel oxide 16, and a composite layer of oxide/nitride/oxide (ONO) 20 which is formed over each floating gate 18.
  • each floating gate 18 is isolated from a horizontally-adjacent floating gate 18 by a layer of oxide 22.
  • the memory cells 12 in a row of memory cells 12 share a common word line 24 which is formed over the layers of ONO 20 and the layers of oxide 22.
  • the portion of the word line 24 which is formed over each of the floating gates 18 in a row of memory cells functions as the control gate of the memory cells in that row.
  • the access transistors 14 in a row of access transistors share a common access select line 26.
  • FIG. 3 shows a cross-sectional diagram taken along lines IB-IB of FIG. 1 that also illustrates the structure of an individual memory cell 12.
  • the floating gates 18 are extended to cover a portion of each vertically-adjacent field oxide region FOX to compensate for the low coupling ratio which is induced by the tunnel oxide 16.
  • the memory cells are formed in a P-well.
  • a virtual-ground flash EPROM array is programmed in the same manner that a conventional
  • EPROM array is programmed. That is, programming is accomplished by injecting hot electrons from a selected drain bit line DRAIN into a selected floating gate 18 when the corresponding source bit line
  • SOURCE is held at an intermediate low voltage (approximately 1 volt)
  • the corresponding word line 24 is taken to the programming voltage Vpp (approximately 12-13 volts)
  • the drain bit line is held at an intermediate voltage (approximately 5-7 volts).
  • FIG. 4 shows a plan view that illustrates a portion of the '938 virtual-ground flash EPROM array 100.
  • FIG. 5 shows a cross-sectional diagram taken along lines 4A-4A of FIG. 4. As shown in FIGs. 4 and 5, the principle distinction between the '293 array 10 and the '938 array
  • the '938 array 100 utilizes graded N+/N- source bit lines GRADED SOURCE which are contacted by the metal bit lines MBLl-MBLn. As a result, the drain bit lines DRAIN are not contacted by any metal bit lines.
  • the principle advantage of the '938 array 100 is that the cells of the array can be erased in the same way that a conventional "T-shaped" flash EPROM is erased. That is, erasing is accomplished by the Fowler-Nordheim tunneling of electrons from the floating gate 18 through the tunnel oxide 16 to the graded source bit line GRADED SOURCE when the source bit line GRADED SOURCE is high, the drain bit line DRAIN is floating, and the selected word line 24 is low.
  • the field oxide regions FOX are utilized to adjust die coupling ratio of the cell.
  • the field oxide regions FOX are also used to isolate MOS transistors which are formed in the periphery.
  • the MOS transistors which generally handle a larger current than the memory cells of the array, typically function as, for example, current sense detectors, amplifiers, and address decoders.
  • the field oxide regions FOX in both the '293 and '928 applications are formed both in the array and in the periphery simultaneously utilizing well-known integration circuit fabrication steps. Since the MOS transistors in the periphery typically handle a larger current than the memory cells in the array, the step height of the field oxide regions FOX, which is the distance from the top surface of the substrate to the top surface of the field oxide, is defined by the isolation requirements of the MOS transistors.
  • the step height which is required to compensate for the coupling ratio of the cells in the array is smaller than the step height that is required to isolate the MOS transistors in the periphery. This divergence in requirements can lead to problems in the array.
  • FIG. 6 shows a plan view that illustrates an aligned floating gate 30A and a misaligned floating gate 30B (shown in dashed lines) formed over a pair of "ideal" field oxide regions FOX.
  • FIG. 7 shows a plan view that illustrates an aligned floating gate 32A (shown in dashed lines) and a misaligned floating gate 32B formed over a pair of "realistic" field oxide regions FOX which have a large step height.
  • the channel area which is the area of the substrate which underlies the floating gate, of the aligned floating gate 30A and the misaligned floating gate 30B is the same.
  • the corners of the "realistic" field oxide regions FOX are rounded, the channel area of the aligned floating gate 32A and misaligned floating gate 32B is different.
  • the threshold voltage of the memory cell varies.
  • the floating gates 18, which are formed from a layer of polysilicon (polyl) are defined by utilizing the word lines 24 as part of a stacked etch step to remove the unwanted portions of the layer of polyl.
  • the problem that arises is that, as the step height of the field oxide regions FOX increase, the likelihood that polyl stringers will be formed during the stacked etch step also increases. Polyl stringers are unwanted portions of the layer of polyl which are not removed during the stacked etch step and which, when not removed, can lead to shorts between adjacent cells.
  • the array where the memory cells and access transistors are formed, includes a plurality of field oxide regions, while the periphery, where supporting MOS transistors are formed, also includes a plurality of field oxide regions.
  • the present invention provides a method for reducing the size of the step heights of the field oxide regions in the array in relation to the size of the step heights of the field oxide regions in the periphery. By reducing the size of the step heights of the field oxide regions in the array, variations in the channel threshold voltages of the cells and the probability of forming polyl stringers can be reduced.
  • a method of fabricating the virtual-ground flash EPROM begins by providing a semiconductor substrate which has an N-type conductivity. Next, a first P-well and a second P-well are formed in the semiconductor substrate. The first P-well defines the array of the
  • a layer of first material is formed over at least the array and the periphery of the semiconductor substrate, followed by the formation of an overlying layer of second material.
  • a plurality of oxide regions are defined on the layer of second material in the periphery.
  • the layer of second material defined by the plurality of oxide regions is etched away to expose a plurality of first material regions in the periphery.
  • the plurality of first material regions in the periphery are then oxidized to form a plurality of field oxide regions.
  • a plurality of oxide regions are defined on the layer of second material in the array.
  • the layer of second material defined by the plurality of oxide regions is etched away to expose a plurality of first material regions in the array.
  • the plurality of first material regions in the array and the field oxide regions in the periphery are oxidized to form a plurality of field oxide regions in the array and to increase the size of the step height of the field oxide regions in the periphery.
  • FIG. 1 is a plan view illustrating a portion of a "virtual-ground" flash EPROM array 10.
  • FIG. 2 is a cross-sectional diagram taken along lines 1A-1A of FIG. 1 illustrating the structure of an individual memory cell 12.
  • FIG. 3 is a cross-sectional diagram taken along lines IB- IB of FIG. 1 illustrating the structure of an individual memory cell 12.
  • FIG. 4 is a plan view illustrating a portion of a virtual-ground flash EPROM array 100.
  • FIG. 5 is a cross-sectional diagram taken along lines 4A-4A of FIG. 4.
  • FIG. 6 is a plan view illustrating an floating gate 30A and a misaligned floating gate 30B formed over a pair of "ideal" field oxide regions FOX.
  • FIG. 7 is a plan view illustrating an aligned floating gate 32A and a misaligned floating gate 32B formed over a pair of "realistic" field oxide regions FOX with a large step height.
  • FIGs. 8-16 are cross-sectional diagrams illustrating the steps for forming a "virtual-ground” flash electrically programmable read-only-memory (EPROM) in accordance with the present invention.
  • FIG. 17 is a plan view of a portion of P-well 202 illustrating the structure that results after the formation of the layer of differential oxide 244.
  • FIG. 18 is a cross-sectional diagram taken along lines 17A-17A of FIG. 17.
  • FIG. 19 is a plan view illustrating the structure that results after the self-aligned etch of the ONO/polyl composite.
  • FIG. 20 is a schematic diagram illustrating how a cell is programmed.
  • FIG. 21 is a plan diagram illustrating a portion of the array.
  • FIG. 22 is a cross-sectional diagram taken along lines 21A-21A of FIG. 21.
  • FIG. 23 is a cross-sectional diagram taken along lines 21B-21B of FIG. 21.
  • FIG. 24 is a schematic diagram illustrating the bias conditions for erasing the cells on a selected word line.
  • FIG. 25 is a timing diagram illustrating the waveforms of the selected word line voltage and of the P-well voltage for erasing the cells on the selected word line.
  • Fig. 26 is a cross-sectional diagram illustrating the erase mechanism.
  • FIGs. 8-16 show cross-sectional diagrams that illustrate the steps for forming a "virtual-ground” flash electrically programmable read-only-memory (EPROM) in accordance with the present invention.
  • EPROM electrically programmable read-only-memory
  • the size of the step heights of the field oxide regions which are formed in the array of a conventional virtual-ground flash EPROM is substantially the same as the size of the step heights of the field oxide regions which are formed in the periphery.
  • the present invention reduces the size of the step heights of the field oxide regions which are formed in the array in relation to the size of the step heights of the field oxide regions which are formed in the periphery.
  • the process of the present invention begins by forming a triple-well structure in an N-type semiconductor substrate 200.
  • the triple-well structure is first formed by growing a layer of first oxide (not shown) approximately 500 A thick over the semiconductor substrate 200.
  • a P-type implant mask is then formed over the layer of first oxide and patterned to define two P- type implant regions.
  • the unmasked areas are implanted with a P-type dopant to form a P-well region 202 and a P-well region 204.
  • P-well region 202 defines an array portion of the substrate, while P-well region 204 defines a peripheral portion.
  • the P-type implant mask is stripped and a thermal drive-in step is performed to further define the P-well regions 202 and 204.
  • the layer of first oxide is then removed.
  • a layer of second oxide (not shown) approximately 500 A thick is grown over the semiconductor substrate 200.
  • An N-type implant mask is then formed over the layer of second oxide and patterned to define an N-type implant region within P-well 204.
  • an N-type dopant is implanted into the unmasked areas to define an N-well region 206.
  • the N-type implant mask is stripped and a further drive- in step is performed to further define the N-well region 206 and the P-well regions 202 and 204.
  • the layer of second oxide is removed.
  • the fabrication steps utilized to form the triple-well structure are conventional and well known in the art.
  • P-well 202 can also formed in an N-well 208 which, in turn, is formed in a substrate 210 of P-type conductivity.
  • the important feature of the triple- well structure shown in FIGs. 8 and 9 is the provision of a P-well formed in N-type silicon. As described in greater detail below, by forming a P-well in N-type silicon, the P-well can be maintained at the supply voltage which, in turn, allows selective portions of the array to be erased.
  • a substrate of P-type conductivity instead of forming a triple-well structure as described above, a substrate of P-type conductivity can be used.
  • the field oxide regions FOX are first formed by growing a layer of pad oxide 214 approximately 500 A thick over substrate 200, P-wells 202 and 204, and N-well 206. This is followed by the deposition of an overlying layer of nitride 216 approximately 2,000 A thick.
  • a field oxide mask 218 is formed over the nitride/pad oxide composite and patterned to define the field oxide regions FOX in the periphery and at the boundary between the periphery and the array. As shown in FIG. 10, field oxide mask 218 protects the layer of nitride 216 in the array. Following this, the unmasked areas are etched until the underlying layer of nitride 216 is removed.
  • the field oxide mask 218 is stripped. Following this, a P-field implant mask 220 is formed and patterned to protect the P-well region 202 in the array and the N-well region 206 in the periphery.
  • the exposed regions of pad oxide 214 are then implanted with BF 2 at 50KeV to form implant regions 222 which have an implant concentration of approximately 4 X lO'Vcm 2 .
  • the field implant mask 220 is stripped. As shown in FIG. 12, the resulting device is then oxidized until a plurality of field oxide regions FOX approximately 5,000 A thick have been grown in the periphery.
  • a field oxide mask 224 is formed and patterned to define the field oxide regions FOX in the array. As shown in FIG. 13, field oxide mask 224 protects the periphery. Next, the unmasked areas are etched until the underlying layer of nitride 216 is removed. The exposed regions of pad oxide 214 are then implanted with BF 2 at 50KeV to form implant regions 226 which have an implant concentration of approximately 4 X lO'Vcm 2 . Following this, the field oxide mask 224 is stripped. The resulting device is then oxidized until a plurality of field oxide regions
  • FOX approximately 5,000 A thick have been grown in the array.
  • the field oxide regions FOX in the periphery continue to grow during this oxidation step, although more slowly.
  • the field oxide regions FOX in the periphery reach a thickness of approximately 7,000 A by the time the field oxide regions FOX in the array reach a thickness of approximately 4,000 A.
  • the flash EPROM of the present invention includes an N-type semiconductor substrate 200, a P-type array implant well 202 which is formed in semiconductor substrate
  • peripheral implant well 204 which is also formed in semiconductor substrate 200.
  • a plurality of spaced-apart peripheral field oxide regions are formed in the peripheral implant well 204.
  • a plurality of spaced-apart array field oxide regions are formed in the array implant well 202.
  • peripheral field oxide regions with a step height of approximately 7,000 A and array field oxide regions with a step height of approximately 4,000 A the process of the present invention can be used to adjust the step height of the array field oxide regions to any desired height which is less than the step height of the peripheral field oxide regions.
  • an array step height can be formed which is 95% of the peripheral step height.
  • the size of the step height of the array field oxide regions is determined by the coupling requirements of the cell, whereas the size of the step height of the peripheral field oxide regions is determined by the isolation requirements of the support transistors which are formed in the periphery. Therefore, with the latitude provided by the present invention, the step height of the array field oxide regions can be determined by the coupling requirements of the cell, rather than the isolation requirements of the transistors in the periphery.
  • the next step is to set the channel threshold voltages for the to-be-formed memory cells.
  • the threshold voltages are first set by removing the nitride/pad oxide composite layer.
  • a layer of sacrificial oxide (not shown) is grown on the exposed semiconductor substrate 200, the P-wells 202 and 204, and the N- well 206.
  • a threshold voltage mask is formed over the layer of sacrificial oxide and patterned to protect the periphery.
  • the semiconductor substrate 202 underlying the unmasked areas of sacrificial oxide is then implanted with Bön at 40KeV to form an implant concentration of approximately 5 X 10 l2 /cm 2 .
  • the threshold voltage mask is stripped and the layer of sacrificial oxide is removed.
  • the fabrication steps utilized to set the channel threshold voltages are also conventional and well known in the art. Referring to FIG. 15, after the layer of sacrificial oxide has been removed, a layer of tunnel oxide
  • a layer of polysilicon (polyl) 234 approximately 1,500 A thick is deposited over the layer of tunnel oxide 232 and the field oxide regions FOX.
  • the layer of polyl 234 is then doped in a conventional manner.
  • the floating gates of the array are formed from the layer of polyl 234.
  • a composite dielectric layer of oxide/nitride/oxide (ONO) 236 is formed on the layer of polyl 234.
  • a photoresist mask 238 is formed over the layer of ONO 236 and patterned to define spaced-apart parallel strips on the layer of ONO 236.
  • the unmasked layer of ONO 236 and underlying layer of polyl 234 are then plasma etched to form spaced-apart parallel stacks 240 of ONO/polyl. As a result of this etching step, a portion of the layer of tunnel oxide 232 is exposed between each pair of stacks 240.
  • FIG. 17 shows a plan view of a portion of P-well 202 that illustrates the structure that results after the formation of the layer of differential oxide 244.
  • a second source bit line mask can be formed and patterned to expose every other N+ bit line.
  • phosphorus is implanted into the exposed bit lines to provide alternate graded N+/N- source regions for the cells of the EPROM array.
  • this graded source implant can be followed by a mask step for implanting boron into the drain bit lines.
  • the typical flash EPROM includes a number of MOS transistors that function, for example, as current sense detectors and address decoders.
  • a protect array mask (not shown) is formed over the array portion of the substrate.
  • the layer of ONO 236, the layer of polyl 234, and the layer of tunnel oxide 232 are etched from the periphery.
  • a layer of second gate oxide (not shown) approximately 200 A thick is grown on the P- type semiconductor substrate 204 in the periphery.
  • the next step is to set the channel threshold voltages for each of the to be formed MOS transistors in the periphery.
  • the threshold voltages are set by forming and patterning a threshold mask, and then implanting a
  • FIG. 18 shows a cross-sectional diagram taken along lines 17A-17A of FIG. 17. As shown in FIG. 18
  • poly2 approximately 1,500 A is deposited over the surface of the entire device and doped in a conventional manner. In the preferred embodiment, this is followed by the deposition of an overlying layer of tungsten suicide 248 approximately 2,000 A thick.
  • the control gates of the cells are formed by the portion of the composite layer of tungsten silicide/poly2 that is formed over the floating gates.
  • a word line mask 250 is then formed over the tungsten silicide/poly2 composite and patterned to define a series of word lines 252 and access select lines 254 in the array, and the gate electrodes of the peripheral MOS devices. Following this, the tungsten silicide/poly2 composite is etched until the unmasked layers of tungsten suicide, and poly2 have been removed. It is noted that the access transistors are flash EPROM cells which have a larger width than the array flash EPROM cells. This allows the access transistors to drive larger currents than the array cells.
  • the word line mask is UV-hardened and a self-aligned etch (SAE) mask is formed so that the overlying timgsten silicide/poly2 composite can be used as a mask for a self-aligned etch of the ONO/polyl composite.
  • SAE self-aligned etch
  • the SAE mask is removed.
  • a source/drain mask (not shown) is formed and patterned to define the N+ source and drain regions of the
  • the P-type semiconductor substrate 204 underlying the unmasked areas is implanted with arsenic through the layer of gate oxide to a depth of 0.2 to 0.3 microns.
  • the source/drain mask is then stripped. Following this, the process follows conventional steps.
  • FIG. 19 shows a plan view that illustrates the structure that results after the self-aligned etch of the
  • the EPROM of the present invention further includes a plurality of spaced-apart memory cells 270 and a plurality of spaced-apart access transistors 272.
  • the array field oxide regions separate both the vertically-adjacent memory cells and access transistors of the array.
  • each memory cell 270 and each access transistor 272 in a column of memory cells and access transistors shares a source bit line SOURCE and a drain bit line DRAIN with the remaining memory cells and access transistors in the column, and with the memory cells 270 and access transistors 272 in the horizontally-adjacent columns.
  • the size of the step height of the field oxide regions which have been formed in the array can be reduced beyond that can be obtained when the field oxide regions are simultaneously formed in both the array and the periphery.
  • the size of the step height of the array field oxide regions can be defined by the height which is required to obtain a desired coupling ratio.
  • FIG. 20 shows a schematic diagram that illustrates how a cell is programmed.
  • the above-described array is programmed in the conventional AMG manner. That is, to program cell A, the drain bit line N of cell A is held at an intermediate voltage Vd (approx 5-7V), bit line N+l is held at ground, and bit line N-l is allowed to float. Select line 1 is biased to the supply voltage Vcc (approx. 5V) and select line 2 is held at ground. The word line WC1 associated with cell A is taken to the programming voltage Vpp (approx. 12-13V), while the remaining word lines (WC2 WL3) are grounded. These bias conditions result in current flow as shown by the arrow in FIG. 20, which results in electron injection from the drain of cell A to the floating gate of cell A, thus programming cell A.
  • FIG. 21 shows a plan diagram that illustrates a portion of the array.
  • FIG. 22 shows a cross- sectional diagram taken along lines 21A-21A of FIG. 21.
  • FIG. 23 shows a cross-sectional diagram taken along lines 21B-21B of FIG. 21.
  • FIG. 24 shows a schematic diagram that illustrates the bias conditions for erasing the cells on a selected word line.
  • FIG. 25 shows a timing diagram that illustrates the waveforms of the selected word line voltage and of the P-well voltage for erasing the cells on the selected word line.
  • Fig. 26 shows a cross-sectional diagram that illustrates the erase mechanism.
  • a high negative voltage -Vpp (approx. - 12V to -13V) is applied to the word line of each row in the array selected for erasure.
  • a positive voltage Vcc (approx. 5V) is applied to the channel area, i.e. to the p-well.
  • the source and drain bit lines are kept open, i.e. floating.
  • the remaining rows are "erase inhibited” by applying the supply voltage Vcc to their associated word lines.
  • the select transistors are flash cells with a W> 2 times the W of a cell in the array in order to pull down Vss on the intermediate node.

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Abstract

L'épaisseur des régions d'oxyde formées dans un agencement d'une mémoire morte programmable électriquement (EPROM) flash à masse virtuelle est choisie pour être inférieure à l'épaisseur des régions d'oxyde qui sont formées à la périphérie, en formant d'abord les régions d'oxyde dans la périphérie et ensuite en formant les régions d'oxyde dans le dispositif.
PCT/US1995/000654 1994-03-15 1995-01-20 Eprom flash a masse virtuelle avec des regions d'oxyde a epaisseur diminuee WO1995025352A1 (fr)

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US21391294A 1994-03-15 1994-03-15
US08/213,912 1994-03-15

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
EP0491581A2 (fr) * 1990-12-18 1992-06-24 Sundisk Corporation Structures verticales denses de cellules de mémoire morte programmable et procédés pour leur fabrication
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
EP0573169A1 (fr) * 1992-06-02 1993-12-08 National Semiconductor Corporation Mémoire flash EEPROM effaçable par segments
WO1994001892A1 (fr) * 1992-07-03 1994-01-20 Commissariat A L'energie Atomique Memoire eeprom de type flash a triples grilles et son procede de fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087584A (en) * 1990-04-30 1992-02-11 Intel Corporation Process for fabricating a contactless floating gate memory array utilizing wordline trench vias
EP0491581A2 (fr) * 1990-12-18 1992-06-24 Sundisk Corporation Structures verticales denses de cellules de mémoire morte programmable et procédés pour leur fabrication
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
EP0573169A1 (fr) * 1992-06-02 1993-12-08 National Semiconductor Corporation Mémoire flash EEPROM effaçable par segments
WO1994001892A1 (fr) * 1992-07-03 1994-01-20 Commissariat A L'energie Atomique Memoire eeprom de type flash a triples grilles et son procede de fabrication

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