WO1995020223B1 - Bicmos memory cell with current access - Google Patents
Bicmos memory cell with current accessInfo
- Publication number
- WO1995020223B1 WO1995020223B1 PCT/US1995/000816 US9500816W WO9520223B1 WO 1995020223 B1 WO1995020223 B1 WO 1995020223B1 US 9500816 W US9500816 W US 9500816W WO 9520223 B1 WO9520223 B1 WO 9520223B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- coupled
- memory cell
- voltage potential
- data
- Prior art date
Links
- 230000004044 response Effects 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 1
- 210000004027 cell Anatomy 0.000 abstract 3
- 230000000295 complement effect Effects 0.000 abstract 3
- 210000000352 storage cell Anatomy 0.000 abstract 3
- 238000006243 chemical reaction Methods 0.000 abstract 2
- 230000006870 function Effects 0.000 abstract 1
Abstract
A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell comprises two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltages of the current mode differential signal established across the complementary bit lines are reduced.
Claims
1. A semiconductor memory cell for storing data, said data corresponding to first and second logic levels, said data in said memory cell being sensed by a differential current sensing apparatus, said memory cell comprising: a means for storing first and second voltage potentials, said first and second voltage potentials corresponding to said first and second logic levels; a first means for converting said first voltage potential into a third voltage potential and said second voltage potential into a fourth voltage potential, said first means for converting being coupled between said third and fourth voltage potentials; a second means for converting said third and fourth voltage potentials into a differential current mode signal corresponding to said data, said differential current mode signal having an associated peak-to-peak voltage, said second converting means being coupled to first and second sensing nodes; a current driving means for supplying a current driving signal to said second converting means, said current driving means being responsive to a read signal; wherein, in response to said read signal said current driving signal is coupled to said second converting means, said second converting means in response to said current driving signal converting said third and fourth voltage potentials into said differential current mode signal corresponding to said data; and wherein said differential current sensing apparatus detects said differential current mode signal corresponding to said data on said first and second sensing nodes and outputs a corresponding differential voltage mode signal.
2. The memory cell as described in claim 1 wherein said first and second voltage potentials correspond to a first type of logic voltage potentials and said third and fourth voltage potentials correspond to a second type of logic voltage potentials.
3. The memory cell as described in claim 2 wherein said differential current sensing apparatus clamps the peak-to-peak voltage of said differential current mode signal corresponding to said data such that capacitive loading effects are minimized when said memory cell is being read.
4. The memory cell as described in claim 3 also including a means for writing data into said storage means.
5. The memory cell as described in claim 4 wherein said first voltage potential is approximately equal to 3 volts and said second voltage potential is approximately equal to zero volts.
6. A BiCMOS memory cell for storing data, said data corresponding to first and second logic levels, said data being sensed by a differential current sensing apparatus, said memory cell comprising: a means for storing first and second CMOS voltage potentials corresponding to said data, said first and second CMOS voltage potentials corresponding to said first and second logic levels; a first means for converting said first CMOS voltage potential into a third voltage potential and said second CMOS voltage potential into a fourth voltage potential, said third and fourth voltage potential corresponding to ECL voltage potentials, said first means for converting being coupled between said third and fourth voltage potentials; a second means for converting said third and fourth voltage potentials into a differential current mode signal corresponding to said data, said differential current mode signal having an associated peak-to-peak voltage, said second converting means comprising first and second bipolar transistors, said second converting means being coupled to first and second sensing nodes; a current driving means for supplying a current driving signal to said second converting means, said current driving means being responsive to a read signal; 2 4
wherein, in response to said read signal said current driving signal is coupled to said second converting means, said second converting means in response to said current driving signal converting said third and fourth voltage potentials into said differential current mode signal corresponding to said data; and wherein said differential current sensing apparatus detects said differential current mode signal corresponding to said data on said first and second sensing nodes and outputs a corresponding differential voltage mode signal.
7. The BiCMOS memory cell as described in claim 6 wherein said first converting means comprises first and second PMOS devices coupled in series at a first common node between said third and fourth voltage potentials, said first
PMOS device having its source coupled to said third voltage potential and said second PMOS device having its drain coupled to said fourth voltage potential, said first converting means also including third and fourth PMOS devices coupled in series at a second common node between said third and fourth voltage potentials, said third PMOS device having its source coupled to said third voltage potential and said fourth PMOS device having its drain coupled to said fourth voltage potential, the gates of said first and fourth PMOS devices being coupled together and the gates of said second and third PMOS devices being coupled together, said first common node between said first and second PMOS devices being coupled to the base of one of said first and second bipolar transistors and said second common node between said third and fourth PMOS devices being coupled to the base of the other of said first and second bipolar transistors.
8. . The BiCMOS memory cell as described in claim 7 wherein said storage means includes first and second CMOS inverters each being coupled between said first and second voltage potentials, said first CMOS inverter having an input and output and said second CMOS inverter having an input and an output, said first CMOS inverter having its input coupled to the output of said second CMOS inverter and said second CMOS inverter having its input coupled to the output of said first CMOS inverter. 25
9. The BiCMOS memory cell as described in claim 8 wherein said differential current sensing apparatus clamps the peak-to-peak voltage of said differential current mode signal corresponding to said data such that capacitive loading effects are minimized when said memory cell is being read.
10. The BiCMOS memory cell as described in claim 9 also including a means for writing data into said storage means.
11. The BiCMOS memory cell as described in claim Ϊ0 wherein said first voltage potential is approximately equal to 3 volts and said second voltage potential is approximately equal to zero volts.
12. The BiCMOS memory cell as described in claim 10 wherein said first voltage potential is approximately equal to 5 volts, said second voltage potential is approximately equal to zero volts, said third voltage potential is approximately equal to said first voltage potential minus a VDI0DE DR0P, where a VDI0DE DR0P is equal to the forward bias voltage drop across a diode junction, and said fourth voltage potential is approximately equal to said first voltage potential minus (2 x VDI0DE DR0P).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU16055/95A AU1605595A (en) | 1994-01-21 | 1995-01-20 | Bicmos memory cell with current access |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/184,436 US5432736A (en) | 1994-01-21 | 1994-01-21 | BiCMOS memory cell with current access |
| US08/184,436 | 1994-01-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1995020223A1 WO1995020223A1 (en) | 1995-07-27 |
| WO1995020223B1 true WO1995020223B1 (en) | 1995-09-14 |
Family
ID=22676849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1995/000816 WO1995020223A1 (en) | 1994-01-21 | 1995-01-20 | Bicmos memory cell with current access |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5432736A (en) |
| AU (1) | AU1605595A (en) |
| WO (1) | WO1995020223A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991192A (en) * | 1997-12-08 | 1999-11-23 | National Science Council Of Republic Of China | Current-mode write-circuit of a static ram |
| US7898848B2 (en) * | 2007-04-23 | 2011-03-01 | Intel Corporation | Memory including bipolar junction transistor select devices |
| US9679614B1 (en) * | 2015-11-25 | 2017-06-13 | Micron Technology, Inc. | Semiconductor device with single ended main I/O line |
| US12100440B2 (en) * | 2022-02-08 | 2024-09-24 | Changxin Memory Technologies, Inc. | Sense amplifier circuit, method for operating same, and fabrication method for same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701883A (en) * | 1986-06-19 | 1987-10-20 | Motorola Inc. | ECL/CMOS memory cell with separate read and write bit lines |
| US4933899A (en) * | 1989-02-01 | 1990-06-12 | Cypress Semiconductor | Bi-CMOS semiconductor memory cell |
| JPH0482085A (en) * | 1990-07-25 | 1992-03-16 | Toshiba Corp | Static memory cell |
| US5283757A (en) * | 1992-02-28 | 1994-02-01 | Unisys Corporation | High speed BiCMOS memory having large noise margin and repeatable read port |
-
1994
- 1994-01-21 US US08/184,436 patent/US5432736A/en not_active Expired - Fee Related
-
1995
- 1995-01-20 WO PCT/US1995/000816 patent/WO1995020223A1/en active Application Filing
- 1995-01-20 AU AU16055/95A patent/AU1605595A/en not_active Abandoned
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