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WO1994029959A1 - A method for multiplying the frequency of a digital signal and a frequency multiplier circuit - Google Patents

A method for multiplying the frequency of a digital signal and a frequency multiplier circuit Download PDF

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Publication number
WO1994029959A1
WO1994029959A1 PCT/FI1994/000257 FI9400257W WO9429959A1 WO 1994029959 A1 WO1994029959 A1 WO 1994029959A1 FI 9400257 W FI9400257 W FI 9400257W WO 9429959 A1 WO9429959 A1 WO 9429959A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
signal
generated
pulses
additional
Prior art date
Application number
PCT/FI1994/000257
Other languages
French (fr)
Inventor
Seppo Laine
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to DE4493921T priority Critical patent/DE4493921T1/en
Priority to GB9525839A priority patent/GB2295286B/en
Priority to AU68482/94A priority patent/AU6848294A/en
Publication of WO1994029959A1 publication Critical patent/WO1994029959A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency

Definitions

  • the invention relates to a method for multiply- ing the frequency of a digital signal by a predetermined multiplier, said method comprising generating from an input signal of a first frequency an output signal of a second frequency, the ratio between said frequencies corresponding to said frequency multiplier.
  • the inven- tion also relates to a frequency multiplier circuit for multiplying the frequency of a digital signal by a pre ⁇ determined multiplier.
  • the solution according to the invention is intended for use particularly in the clock ⁇ ing of synchronous telecommunications systems.
  • the frequency multiplier function is usually implemented by a digital or analog phase lock circuit.
  • the problem with a digital phase lock is that its real ⁇ ization often requires extremely high auxiliary clock frequencies.
  • the problem with an analog phase lock is that the phase of the multiplied frequency fades, which causes problems relating to metastability and inter ⁇ ference peaks in clockings.
  • the object of the present invention is to provide a method and a circuit by which a generated signal of a multiplied frequency remains in a phase lock with relation to the original signal and by which the problems described above can be obviated. This is achieved with a method and a circuit according to the invention.
  • the method according to the invention is characterized in that a predetermined number of pulses is generated in the output signal per one transition of the input signal, and that, in addition, additional pulses are added to the output signal thus generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated in response to said transitions.
  • the circuit according to the invention is characterized by comprising first means for generating a predetermined number of pulses, prefer- ably one pulse, per one transition of the signal to be multiplied in a signal to be generated, and second means for adding additional pulses, preferably one additional pulse, to the signal to be generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated by said first means.
  • the idea of the invention is to provide a certain basic multiplier by the use of the edges of the signal to be multiplied, i.e. by generating pulses in response to the detected edges, and to add the lacking clock pulses using accurate timing so as to achieve the desired frequency.
  • the frequency multiplier range achieved with the present solution is typically between 1.5 and 6, but the inaccuracy factors of the whole system have an effect on the greatest frequency multiplier achievable at a given time.
  • Figure 1 shows a frequency multiplier circuit according to the invention
  • Figure 2 shows the signals occurring in the circuit illustrated in Figure 1.
  • Figure 1 shows a frequency multiplier circuit according to the invention, comprising three basic blocks: an edge identification block A, a monitoring block B, and an additional pulse generating block C.
  • the purpose of the circuit is to generate, from an incoming basic clock signal CLKl, a clock signal CLK3 having a frequency multiplied by a factor 9/4.
  • Clock signal CLKl may be e.g. a 2048-kbit/s basic clock signal (typically obtained from the rack of tele ⁇ communications equipment).
  • the edge identification block A comprises an inverting exclusive-OR gate (exclusive-NOR gate) 111, to the first input of which the basic clock is supplied directly, and to the second input of which the basic clock is supplied via a first delay element 108, an exclusive-OR gate 109, to the first input of which the output of the delay element 108 is connected, and a second delay element 110.
  • the output of the additional pulse generating block C is connected to the second input of the exclusive-OR gate 109.
  • the basic clock signal is also supplied to the monitoring block B, comprising a frequency divider 101 at the input and two successively connected type D flip- flops 102 and 103.
  • the output of the frequency divider 101 which in this example is a divider by four, is connected to the clock input CLK of the D flip-flop 102.
  • a voltage Vcc corresponding to a logical one is supplied to the data input D of the flip-flop 102, and the output Q of the flip-flop is connected to the data input D of the second flip-flop 103.
  • the output of the exclusive- NOR gate 111 is connected to the clock input CLK of the flip-flop 103, and the output Q of the flip-flop 103 is connected to the reset input R of the flip-flop 102 and to the input of the additional pulse generating block C.
  • the additional pulse generating block C comprises an AND gate 107, to the first input of which the output Q of the flip-flop 103 is connected directly, and to the second input of which the output of the flip- flop 103 is connected via a delay line comprising three successive delay elements 104-106, of which the last one (delay element 106) inverts the signal.
  • the output of the AND gate 107 which is also the output of the entire block C, is connected to the second input of the exclusive-OR gate 109.
  • FIG. 2 illustrates the signals occurring in the frequency multiplier circuit according to Figure 1. The operation of the circuit will be described in the following.
  • a basic clock signal CLKl is supplied to the edge identification block A, which identifies the edges of the basic clock signal and generates one clock pulse to the output signal CLK3 per each transition (rising or falling edge) of the basic clock signal.
  • the length of the generated pulse depends on the total delay caused by the delay elements 108 and 110. In this way the frequency of the basic clock signal is multiplied by two in the first stage.
  • the basic clock signal is also supplied to the frequency divider 101 of the monitoring block, whereby a signal indicated by FB is supplied to the clock input of the flip-flop 102.
  • a signal indicated by FB is supplied to the clock input of the flip-flop 102.
  • the output signal f of the additional pulse generating block C (the output of the AND gate) there is thus also generated, after every eighth transition, a pulse fp, the leading edge of which is slightly delayed in relation to the corresponding rising edge of the basic clock signal multiplied by two (signal CLK3).
  • This delay which is caused by the flip- flop 103 and the AND gate 107, is indicated in the figure by D2.
  • the length D3 of the pulse is determined by the total delay caused by the delay elements 104-106.
  • the exclusive-NOR gate 111 of the edge identification block adds thus an additional clock pulse to the signal to be generated after every eighth transition.
  • This additional pulse is indicated by E.
  • the aim is to time the additional pulses so that they occur primarily in the middle of the pulses gener ⁇ ated as a response to the transitions of the basic clock signal.
  • the edge identification block A generates thus a pulse per each transition of the basic clock signal and, in addition, an additional pulse after every eighth transition.
  • the monitoring block B indicates when a desired number of pulses have been generated (i.e. when the desired number of transitions have occurred), and the additional pulse generating block C generates the additional pulse accurately at the desired position with respect to time as compared with the pulses generated as a response to the transitions of the basic clock signal.
  • the delay elements of the circuit can be implemented, for example, by the use of an internal macrocell of a (programmable) circuit, which macrocell provides a certain delay (the length of which appears from the data sheet of the circuit) in the signal.
  • a circuit suitable for use for this purpose is EP610, manufactured by Altera Corporation, USA.
  • the multiplied signal CLK3 which is generated is not quite homogeneous but contains jitter due to the superposition of additional pulses at regular intervals between the pulses to be generated. Therefore it is advantageous to use as an incoming signal a signal which has the highest possible clock frequency (e.g. 2.048 MHz) at that par ⁇ ticular moment and to use the information which can be obtained from it (both edges).

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention relates to a method for multiplying the frequency of a digital signal by a predetermined multiplier and a frequency multiplier circuit. The method comprises generating from an input signal (CLK1) of a first frequency an output signal (CLK3) of a second frequency, the ratio between said frequencies corresponding to said frequency multiplier. In order that clock frequencies higher than the basic clock might be avoided and that the phase variation of the signal of the multiplied frequency might be controlled, a predetermined number of pulses is generated in the output signal (CLK3) per one transition of the input signal (CLK1), and additional pulses (E) are added to the output signal thus generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated in response to said transitions.

Description

A method for multiplying the frequency of a digital signal and a frequency multiplier circuit
The invention relates to a method for multiply- ing the frequency of a digital signal by a predetermined multiplier, said method comprising generating from an input signal of a first frequency an output signal of a second frequency, the ratio between said frequencies corresponding to said frequency multiplier. The inven- tion also relates to a frequency multiplier circuit for multiplying the frequency of a digital signal by a pre¬ determined multiplier. The solution according to the invention is intended for use particularly in the clock¬ ing of synchronous telecommunications systems. The frequency multiplier function is usually implemented by a digital or analog phase lock circuit. The problem with a digital phase lock is that its real¬ ization often requires extremely high auxiliary clock frequencies. The problem with an analog phase lock is that the phase of the multiplied frequency fades, which causes problems relating to metastability and inter¬ ference peaks in clockings.
The object of the present invention is to provide a method and a circuit by which a generated signal of a multiplied frequency remains in a phase lock with relation to the original signal and by which the problems described above can be obviated. This is achieved with a method and a circuit according to the invention. The method according to the invention is characterized in that a predetermined number of pulses is generated in the output signal per one transition of the input signal, and that, in addition, additional pulses are added to the output signal thus generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated in response to said transitions. The circuit according to the invention is characterized by comprising first means for generating a predetermined number of pulses, prefer- ably one pulse, per one transition of the signal to be multiplied in a signal to be generated, and second means for adding additional pulses, preferably one additional pulse, to the signal to be generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated by said first means.
The idea of the invention is to provide a certain basic multiplier by the use of the edges of the signal to be multiplied, i.e. by generating pulses in response to the detected edges, and to add the lacking clock pulses using accurate timing so as to achieve the desired frequency.
By means of the solution according to the invention it is possible to avoid clock frequencies higher than the basic clock and to control the phase variation of the signal of the multiplied frequency. Further advantages of the solution according to the invention are the small amount of logic that is needed and its applicability to the clocking of synchronous telecommunications systems, in particular.
The frequency multiplier range achieved with the present solution is typically between 1.5 and 6, but the inaccuracy factors of the whole system have an effect on the greatest frequency multiplier achievable at a given time.
In the following, the invention will be described in greater detail by way of example and with reference to the accompanying drawings, in which
Figure 1 shows a frequency multiplier circuit according to the invention, and Figure 2 shows the signals occurring in the circuit illustrated in Figure 1.
Figure 1 shows a frequency multiplier circuit according to the invention, comprising three basic blocks: an edge identification block A, a monitoring block B, and an additional pulse generating block C. In this example, the purpose of the circuit is to generate, from an incoming basic clock signal CLKl, a clock signal CLK3 having a frequency multiplied by a factor 9/4. Clock signal CLKl may be e.g. a 2048-kbit/s basic clock signal (typically obtained from the rack of tele¬ communications equipment).
The edge identification block A comprises an inverting exclusive-OR gate (exclusive-NOR gate) 111, to the first input of which the basic clock is supplied directly, and to the second input of which the basic clock is supplied via a first delay element 108, an exclusive-OR gate 109, to the first input of which the output of the delay element 108 is connected, and a second delay element 110. The output of the additional pulse generating block C is connected to the second input of the exclusive-OR gate 109.
The basic clock signal is also supplied to the monitoring block B, comprising a frequency divider 101 at the input and two successively connected type D flip- flops 102 and 103. The output of the frequency divider 101, which in this example is a divider by four, is connected to the clock input CLK of the D flip-flop 102. A voltage Vcc corresponding to a logical one is supplied to the data input D of the flip-flop 102, and the output Q of the flip-flop is connected to the data input D of the second flip-flop 103. The output of the exclusive- NOR gate 111 is connected to the clock input CLK of the flip-flop 103, and the output Q of the flip-flop 103 is connected to the reset input R of the flip-flop 102 and to the input of the additional pulse generating block C.
The additional pulse generating block C comprises an AND gate 107, to the first input of which the output Q of the flip-flop 103 is connected directly, and to the second input of which the output of the flip- flop 103 is connected via a delay line comprising three successive delay elements 104-106, of which the last one (delay element 106) inverts the signal. The output of the AND gate 107, which is also the output of the entire block C, is connected to the second input of the exclusive-OR gate 109.
Figure 2 illustrates the signals occurring in the frequency multiplier circuit according to Figure 1. The operation of the circuit will be described in the following.
A basic clock signal CLKl is supplied to the edge identification block A, which identifies the edges of the basic clock signal and generates one clock pulse to the output signal CLK3 per each transition (rising or falling edge) of the basic clock signal. The length of the generated pulse depends on the total delay caused by the delay elements 108 and 110. In this way the frequency of the basic clock signal is multiplied by two in the first stage.
The basic clock signal is also supplied to the frequency divider 101 of the monitoring block, whereby a signal indicated by FB is supplied to the clock input of the flip-flop 102. When the flip-flop 102 is clocked by the rising (0-to-l) edge of the signal FB and the flip-flop 103 correspondingly by the rising edge of the output signal of the inverting exclusive-OR gate 111, and when the output signal of the flip-flop 103, while changing from a logical zero to a logical one, resets the flip-flop 102, the output of the monitoring block gives a signal d, which comprises a pulse dp after every eighth transition of the basic clock signal CLKl, the pulse having the length of one transition interval of the basic clock signal. In the output signal f of the additional pulse generating block C (the output of the AND gate) there is thus also generated, after every eighth transition, a pulse fp, the leading edge of which is slightly delayed in relation to the corresponding rising edge of the basic clock signal multiplied by two (signal CLK3). This delay, which is caused by the flip- flop 103 and the AND gate 107, is indicated in the figure by D2. The length D3 of the pulse is determined by the total delay caused by the delay elements 104-106. When the exclusive-OR gate 109 of the edge identification block receives a logical one at its second input, it becomes an inverter, and a correspond¬ ing change takes place in CLK3 after a time determined by the delay element 110. The exclusive-NOR gate 111 of the edge identification block adds thus an additional clock pulse to the signal to be generated after every eighth transition. This additional pulse is indicated by E. The aim is to time the additional pulses so that they occur primarily in the middle of the pulses gener¬ ated as a response to the transitions of the basic clock signal.
The edge identification block A generates thus a pulse per each transition of the basic clock signal and, in addition, an additional pulse after every eighth transition. The monitoring block B indicates when a desired number of pulses have been generated (i.e. when the desired number of transitions have occurred), and the additional pulse generating block C generates the additional pulse accurately at the desired position with respect to time as compared with the pulses generated as a response to the transitions of the basic clock signal.
The delay elements of the circuit can be implemented, for example, by the use of an internal macrocell of a (programmable) circuit, which macrocell provides a certain delay (the length of which appears from the data sheet of the circuit) in the signal. One circuit suitable for use for this purpose is EP610, manufactured by Altera Corporation, USA. As appears from the above, the multiplied signal CLK3 which is generated is not quite homogeneous but contains jitter due to the superposition of additional pulses at regular intervals between the pulses to be generated. Therefore it is advantageous to use as an incoming signal a signal which has the highest possible clock frequency (e.g. 2.048 MHz) at that par¬ ticular moment and to use the information which can be obtained from it (both edges). When lower clock frequencies are formed from the multiplied clock frequency by dividing, e.g. by a hundred, there is hardly any jitter. The essential feature of the multiplied signal is, however, that the positions of its transitions are known accurately in relation to the signal to be multiplied. Although the invention is described above with reference to the examples illustrated in the accompany¬ ing drawings, it will be obvious that the invention is not restricted to them but can be modified within the scope of the inventive concept disclosed above and in the appended claims. It would be possible, for instance, to add two pulses per each transition of an incoming signal. However, in practice this sets much greater requirements for the internal delays of the circuit. The frequency multiplier can also be changed by changing the division ratio of the frequency divider 101. In principle, it is also possible to add more than one additional pulse at regular intervals, but on account of the resulting distortion, it is advantageous to restrict the number of additional pulses to one.

Claims

Claims
1. A method for multiplying the frequency of a digital signal by a predetermined multiplier, said method comprising generating from an input signal (CLKl) of a first frequency an output signal (CLK3) of a second frequency, the ratio between said frequencies corres¬ ponding to said frequency multiplier, c h a r a c ¬ t e r i z e d in that - a predetermined number of pulses is generated in the output signal (CLK3) per one transition of the input signal (CLKl), and that, in addition,
- additional pulses (E) are added to the output signal thus generated at predetermined intervals in such a manner that the additional pulses are generated at predetermined positions in relation to the pulses generated in response to said transitions.
2. A method according to claim 1, c h a r a c ¬ t e r i z e d by generating one pulse in the output signal (CLK3) per one transition of the input signal (CLKl).
3. A method according to claim 1 or 2, c h a r a c t e r i z e d by adding only one additional pulse at predetermined intervals to the signal (CLK3) to be generated.
4. A method according to claim 3, c h a r a c ¬ t e r i z e d by adding said additional pulse substan¬ tially midway between two pulses generated in response to said transitions.
5. A frequency multiplier circuit for multiply¬ ing the frequency of a digital signal by a predetermined multiplier, c h a r a c t e r i z e d by comprising
- first means (A) for generating a predetermin¬ ed number of pulses, preferably one pulse, per one transition of the signal (CLKl) to be multiplied in a signal to be generated, and
- second means (A, B, C) for adding additional pulses, preferably one additional pulse, to the signal to be generated at predetermined intervals in such a manner that the additional pulses are generated at pre¬ determined positions in relation to the pulses generated by said first means.
6. A circuit according to claim 5, c h a r a c- t e r i z e d in that said first means (A) comprise edge identification elements (111) for identifying the pulse edge of the signal to be multiplied.
PCT/FI1994/000257 1993-06-16 1994-06-15 A method for multiplying the frequency of a digital signal and a frequency multiplier circuit WO1994029959A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE4493921T DE4493921T1 (en) 1993-06-16 1994-06-15 Method for frequency multiplication of a digital signal and frequency multiplier circuit
GB9525839A GB2295286B (en) 1993-06-16 1994-06-15 A method for multiplying the frequency of a digital signal and a frequency multiplier circuit
AU68482/94A AU6848294A (en) 1993-06-16 1994-06-15 A method for multiplying the frequency of a digital signal and a frequency multiplier circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI932775A FI94086C (en) 1993-06-16 1993-06-16 Method for multiplying a digital signal frequency and a frequency multiplier circuit
FI932775 1993-06-16

Publications (1)

Publication Number Publication Date
WO1994029959A1 true WO1994029959A1 (en) 1994-12-22

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PCT/FI1994/000257 WO1994029959A1 (en) 1993-06-16 1994-06-15 A method for multiplying the frequency of a digital signal and a frequency multiplier circuit

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AU (1) AU6848294A (en)
DE (1) DE4493921T1 (en)
FI (1) FI94086C (en)
GB (1) GB2295286B (en)
WO (1) WO1994029959A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2124667A1 (en) * 1996-12-16 1999-02-01 Telefonica Nacional Espana Co Integrated frequency multiplier circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH609201GA3 (en) * 1974-08-19 1979-02-28
GB2257276A (en) * 1991-07-04 1993-01-06 Nokia Mobile Phones Ltd Frequency divider

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10108809A (en) * 1996-10-04 1998-04-28 Mitsubishi Electric Home Appliance Co Ltd Electric vacuum cleaner

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH609201GA3 (en) * 1974-08-19 1979-02-28
GB2257276A (en) * 1991-07-04 1993-01-06 Nokia Mobile Phones Ltd Frequency divider

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, Vol. 13, No. 350, E-800; & JP,A,1 108 809 (TDK CORP), 26 April 1989. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2124667A1 (en) * 1996-12-16 1999-02-01 Telefonica Nacional Espana Co Integrated frequency multiplier circuit

Also Published As

Publication number Publication date
FI94086B (en) 1995-03-31
AU6848294A (en) 1995-01-03
GB2295286B (en) 1997-04-30
DE4493921T1 (en) 1996-06-27
FI932775L (en) 1994-12-17
GB2295286A (en) 1996-05-22
FI932775A0 (en) 1993-06-16
FI94086C (en) 1995-07-10
GB9525839D0 (en) 1996-02-21

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