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WO1994010679A1 - Amelioration de la resolution d'ecrans video par interpolation de lignes multiples - Google Patents

Amelioration de la resolution d'ecrans video par interpolation de lignes multiples Download PDF

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Publication number
WO1994010679A1
WO1994010679A1 PCT/US1992/009342 US9209342W WO9410679A1 WO 1994010679 A1 WO1994010679 A1 WO 1994010679A1 US 9209342 W US9209342 W US 9209342W WO 9410679 A1 WO9410679 A1 WO 9410679A1
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WO
WIPO (PCT)
Prior art keywords
resolution
low
pixel
data
image
Prior art date
Application number
PCT/US1992/009342
Other languages
English (en)
Inventor
Robert Joseph Mical
David Lewis Needle
Teju Jhamatmal Khubchandani
Stephen Harland Landrum
Original Assignee
The 3Do Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The 3Do Company filed Critical The 3Do Company
Priority to AU30585/92A priority Critical patent/AU3058592A/en
Priority to PCT/US1992/009342 priority patent/WO1994010679A1/fr
Publication of WO1994010679A1 publication Critical patent/WO1994010679A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4007—Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Definitions

  • the invention relates generally to digital image processing and the display of digitally generated images.
  • the invention relates more specifically to the problem of creating high-resolution animated images in real time.
  • this application includes listings of
  • code conversion tables named: ITPCON, HVON, HV0ON, HV10N, HV20N, HV30N. These code-conversion tables can be implemented by way of a computer program, microcode, in a ROM, and so forth. These code-conversion tables can also be implemented by way of combinatorial logic. Since
  • Patent Application Serial No. bearing the same title, same inventors and also filed concurrently herewith;
  • PCT Patent Application Serial No. entitled SPRYTE RENDERING SYSTEM WITH IMPROVED CORNER CALCULATING ENGINE AND IMPROVED POLYGON-PAINT ENGINE, by inventors Needle et al., filed concurrently herewith, Attorney Docket No. MDI04232, and also to U.S. Patent Application Serial No. , bearing the same title, same inventors and also filed concurrently herewith;
  • the visual realism of imagery generated by digital video game systems, simulators and the like can be enhanced by providing special effects such as moving sprites, real-time changes in shadowing and/or highlighting, smoothing of contours and so forth.
  • Visual realism is further enhanced by increasing the apparent resolution of a displayed image so that it has a smooth photography-like quality rather than a grainy disjoined-blocks appearance of the type found in low- resolution computer-produced graphics of earlier years.
  • bit-mapped computer images originate as a matrix of discrete lit or unlit pixels
  • the human eye can be fooled into perceiving an image having the desired photography-like continuity if a matrix format comprised of independently-shaded (and/or independently colored) pixels is provided having dimensions of approximately 500-by-500 pixels or better at the point of display.
  • the VGA graphics standard which is used in many present-day low-lost computer systems, approximates this effect with a display matrix having dimensions of 640- by-480 pixels.
  • Standard-definition NTSC broadcast television also approximates this effect with a display technology that relies on interlaced fields with 525 lines per pair of fields and a horizontal scan bandwidth (analog) that is equivalent to approximately 500 RGB colored dots per line.
  • Each doubling of display resolution say from 640-by-480 pixels to l280-by-960 pixels, calls for a four-fold increase in storage capacity. This means an increase from 512K words to 2M words (two Megawords) in the given example.
  • the invention overcomes the above-mentioned problems by using a low-resolution image representation within an image data processing unit and by enhancing apparent image resolution through the use of interpolation prior to production of a displayable version of the image.
  • the invention provides an interpolation mechanism in which a first number, N, of low-resolution pixels determine the shading/coloring of a second larger number, M > N, of high-resolution pixels.
  • a 320-by-240 matrix of low-resolution stored pixels is interpolated in real time to produce a non-stored, dual-field, frame of display data with an apparent higher-resolution of 640- by-480 pixels.
  • the produced higher-resolution frame data is either immediately used or ultimately used to generate a light image that is intended to be transmitted to the eyes of a human being and appreciated by that human being for its opto-physiological and/or psycho-visual, graphic content.
  • high-resolution data signals that are produced in accordance with the invention ultimately manifest themselves as significant parts of a physically real entity; the displayed image.
  • Source image data is placed within independently addressable, parallel banks of a multi-bank video random access memory unit (VRAM) .
  • VRAM video random access memory unit
  • the image data is arranged such that pixels of adjacent rows but a same column will be fetched in parallel when same address signals are applied to each of the independently addressable banks of the multi-bank VRAM.
  • the advantages of such an arrangement include reduced demand for large-capacity video-speed memory, reduced demand for high-bandwidth image processing hardware, a consequential decrease in system cost, and automatic smoothing in the displayed image of pixel-to- adjacent-pixel discontinuities.
  • a structure in accordance with the invention comprises: (a) a memory unit for storing low-resolution pixel data of adjacent, low-resolution scan lines in adjacently addressable memory locations; (b) means for extracting from the memory unit, an interpolation group consisting of N low-resolution pixel words, where N is an integer substantially less than the number of pixels in a low-resolution line; (c) interpolating means for interpolating the N low-resolution pixel words of the interpolation group and producing therefrom one or more high-resolution pixel words; and (d) high-resolution display means for displaying a light image having pixels corresponding to each high-resolution pixel word produced by the interpolating means.
  • a method in accordance with the invention comprises the steps of: (a) storing low-resolution image-data in a memory having independently addressable storage banks such that low-resolution image-data defining a first low- resolution row resides in a first of said storage banks and such that low-resolution image-data defining a second low-resolution row, adjacent to the first low-resolution row, resides in a second of said storage banks; (b) extracting first through Nth low-resolution pixel signals [S,-S 3 ] from the memory, said signals representing values of low-resolution pixels in the adjacent first and second low-resolution rows [LR 0 ,LR 1 ] of the low-resolution image-data and producing a high-resolution pixel signal [Hpx] from said first through Nth low-resolution pixel signals [S,-S 3 ] in accordance with a distance-weighted algorithm.
  • FIGURE 1 is a block diagram of a first resolution enhancing system in accordance with the invention.
  • FIGURE 2 is a schematic diagram illustrating how a group of low-resolution pixel datawords is interpolated to generate high-resolution pixel data in accordance with the invention.
  • Figures 3A through 3E are transform diagrams showing one possible set of contribution weightings which can be used within a resolution enhancing system in accordance with the invention.
  • Figure 3F shows a choice making system in which a subposition coordinates used in any of Fig.s 3B-3E are converted to universal (UV) table identifiers of a commonly shared choice-making table and the choices of the choice-making table are converted back to choice identifiers for corresponding condition of each of Fig.s
  • FIGURES 4A-4B combine as indicated by the key in
  • FIGURE 4C is a timing diagram showing the timing of various signals developed in the embodiment of Fig. 4A.
  • FIGURE 4D is a schematic diagram of a CAPCLKEN generating circuit, a slip-stream capture circuit and a VRAM data capture circuit in accordance with the invention.
  • FIGURE 4E is a conceptual diagram showing data interleaving in the pipelined structure of Fig.s 4A-B, showing the destacking of interleaved data and showing a CLUT-delay matching function performed within an SP carrying pipe of the system.
  • FIGURE 5 is a schematic diagram illustrating details of a 24-bit destacker unit and its operation.
  • FIGURE 6A is a schematic diagram illustrating details of a first addends-choosing unit which may be coupled to the MUXCAP unit of below-described Fig. 7, wherein the addends-choosing unit includes a post-choice horizontal and/or vertical interpolation enabling means which creates an appearance that one or both of horizontal and vertical interpolation functions has been selectively enabled or disabled.
  • FIGURES 6B.1 and 6B.2 are diagrams explaining the functions of post-choice modifying units 640-643 of Fig. 6A.
  • FIGURE 6C is a schematic diagram illustrating details of a second addends-choosing unit which may be coupled to the MUXCAP unit of below-described Fig. 7, wherein the addends-choosing unit includes a pre-choice a horizontal and/or vertical interpolation enabling means which creates an appearance that one or both of horizontal and vertical interpolation functions has been selectively enabled or disabled.
  • FIGURES 6D.1 and 6D.2 are diagrams explaining the functions of subposition modifying units 1640-1643 of Fig. 6C.
  • FIGURE 7 is a schematic diagram of a MUXCAP unit of the invention.
  • FIGURE 8 is a schematic diagram illustrating details of a pipelined average-calculating mechanism in accordance with the invention.
  • FIG. 1 a block diagram of an image processing and display system 100 in accordance with the invention is shown.
  • a key feature of system 100 is that it is relatively low in cost and yet it provides mechanisms for handling complex image scenes in real time and displaying them such that they appear to have relatively high resolution.
  • This feature is made possible by including a resolution-enhancing subsystem 150 on one or a few integrated circuit (IC) chips within the system 100.
  • the operations of subsystem 150 are best understood by first considering the video processing operations of system 100 in an overview sense.
  • Figure 1 provides an overview of the system 100. Except where otherwise stated, all or most parts of system 100 are implemented on a single printed circuit board 99 and the circuit components are defined within one or a plurality of integrated circuit (IC) chips mounted to the board 99. Except where otherwise stated, all or most of the circuitry is implemented in CMOS (complementary metal-oxide-semiconductor) technology using 0.9 micron line widths. An off-board power supply (not shown) delivers electrical power to the board 99.
  • CMOS complementary metal-oxide-semiconductor
  • System 100 includes a video display driver 105A- 105B, a real-time image-data processing unit (IPU) 110, a video random-access memory unit (VRAM) 120 having multiple independently-addressable storage banks, the aforementioned resolution-enhancing subsystem 150 and a high-resolution video display unit 160.
  • a video display driver 105A- 105B a real-time image-data processing unit (IPU) 110, a video random-access memory unit (VRAM) 120 having multiple independently-addressable storage banks, the aforementioned resolution-enhancing subsystem 150 and a high-resolution video display unit 160.
  • IPU real-time image-data processing unit
  • VRAM video random-access memory unit
  • VRAM 120 has two independently-addressable storage banks.
  • a front-end portion 105A of the video display driver incorporates a low-resolution video pixel (LPx) clock generator 108 supplying periodic clock pulses to a dual-output video- address generator (VAG) 115.
  • the VAG 115 outputs two bank-address signals, AB Q and AB, , to the multi-bank VRAM 120 in response to a pulse received from the LPx clock generator 108.
  • VRAM 120 outputs two pixel-defining "halfword" signals, Px(LR 0 ) and Px(LR 1 ), on respective VRAM output buses 122 and 121 to the resolution-enhancing subsystem 150 in response to respective ones of the bank-address signals, AB Q and AB, .
  • the resolution-enhancing subsystem 150 includes a cross-over unit 151 for selectively transposing the Px(LR 0 ) and Px(LR,) signals; first and second delay registers, 156 and 155 (A and B) , coupled to the cross- over unit 151 for generating previous-column signals, Px(LR 0 , laC_ 1 ) and Px LR ⁇ LC ⁇ ) ; and an interpolator 159 for generating high-resolution pixel signals, HPx(HR_i, HC k ) , in response to the previous-column signals, Px(LR 0 , LC_ 1 ) and PxfLR ⁇ LC ,) and in response to current- column signals, Px(LR Q , LC_ 0 ) and P LR ⁇ LC_ 0 ) , supplied from the cross-over unit 151.
  • the bus which connects the output of cross-over unit 151 to the input of A-register 156 is referred to as the A-side bus 154.
  • the bus which connects the opposed output of cross-over unit 151 to the input of B-register 155 is referred to as the B-side bus 153.
  • the high-resolution pixel signals, HPx(HR ⁇ , HC ⁇ ) , produced by interpolator 159 appear on output bus 159o and then pass by way of display-driver portion 105B to the video display unit 160.
  • a high-resolution pixel clock generator (HPx CLK) 158 operating at twice the frequency of the LPx clock generator 108, drives the resolution-enhancing subsystem 150 such that high- resolution pixel signals HPx(HR ⁇ , HC appear on output bus 159o at twice the rate that low-resolution pixels Px(LR 0 ) and Px(LR 1 ) appear on VRAM output buses 122 and 121.
  • the video display unit 160 is located off board 99 and its circuitry can be implemented in technologies other than CMOS.
  • LR is used in the above paragraphs and throughout the remainder of this disclosure to represent “Low-resolution Row”.
  • LC is used throughout this disclosure to represent “Low-resolution Column”.
  • HR and “HC” are used throughout to respectively represent High-resolution Row and High- resolution Column.
  • Fig. 2 shows the relation between low-resolution and high-resolution rows and columns.
  • the subscript "0” is often times (but not always) used in this disclosure to indicate an even-numbered row.
  • the subscript "1” is often times (but not always) used to indicate an odd-numbered row.
  • HPx is used to represent High-resolution Pixel.
  • Px The simple abbreviation "Px” is used to represent a low-resolution pixel.
  • a reference such as Px(LR 0 , LC k ) therefore indicates a low-resolution pixel associated with an even-numbered low-resolution row, LR Q , and low- resolution column numbered as, LC ⁇ .
  • LPx The abbreviation "LPx” is also used occasionally to represent a low- resolution pixel.
  • a reference such as HPx(HR-, HC k ) indicates a high- resolution pixel associated with a high-resolution row numbered as HR• , and a high-resolution column numbered as LC k , where j and k refer to either odd or even integers.
  • a human observer 170 is shown viewing a high-resolution image 165 projected from (or onto) video display unit 160.
  • the perceived performance and image resolution is referenced as 172.
  • Display unit 160 is a VGA color monitor or an NTSC- compatible color television set, or a like display means (e.g., a liquid crystal display panel) or a display means of better resolution which has the capacity to display a pixel matrix of at least, approximately 640-by-480 pixels resolution.
  • the link 169 between board 99 and display unit 160 can be provided through a baseband connection or by way of an RF modulator/demodulator pair.
  • the image data processing unit (IPU) 110 is driven by a processor clock generator 102 (50.097896 MHz divided by one or two) operating in synchronism with, but at a higher frequency than the LPx clock generator 108 (12.2727 MHz).
  • IPU 110 includes a RISC type 25MHz or 50MHz ARM610 microprocessor (not shown) available from Advanced RISC Machines Limited of Cambridge, U.K.
  • a plurality of sprite-rendering engines (not shown) and direct memory access (DMA) hardware (not shown) are also provided within the IPU 110.
  • the IPU 110 accesses binary-coded data (e.g., 125) stored within the VRAM 120 and modifies the stored data at a sufficiently high-rate of speed to create the illusion for observer 170 that real-time animation is occurring in the high-resolution image 165 displayed on video display unit 160.
  • observer 170 will be interactively affecting the animated image 165 by operating buttons or a joystick or other input means on a control panel 175 that feeds back signals 178 representing the observer's real-time responses to the image data processing unit (IPU) 110.
  • IPU 110 is operatively coupled to the video random- access memory (VRAM) 120 such that the IPU 110 has read/write access to various control and image data structures stored within VRAM 120 either on a cycle- steal basis or on an independent access basis.
  • VRAM video random- access memory
  • the internal structure of IPU 110 is immaterial. Any means for loading and modifying the contents of VRAM 120 at sufficient speed to produce an animated low-resolution image data structure 125 of the type described below will do.
  • the VRAM 120 has the capacity to store 1 megabyte of data but it can be expanded to store 2 or 4 or 16 megabytes of data. (A byte is understood to consist of eight bits of data.) One to two megabytes of VRAM storage is preferred but not an absolute minimum or maximum storage requirement. The system will work with a VRAM of larger or smaller capacity also. VRAM access time should be small enough to meet the demands of the low-resolution pixel video clock 108 and processor clock 102. It is to be understood that VRAM 120 can be incorporated within a larger "system" memory that includes DRAM and/or RAMBUSTM storage devices. In such a case, VRAM 120 can serve as a cache area into which there is loaded image data that is to be then displayed or otherwise processed.
  • the IPU 110 reads and writes data from/into the VRAM 120 in the form of 32-bit wide "words". Physically, the VRAM 120 is split into left and right independently addressable banks where each bank has its own 16-bit- wide address port and 16-bit wide data port. This gives hardware devices, such the resolution-enhancing subsystem 150, simultaneous access to two separately addressable 16-bit "halfwords" within VRAM 120. In most instances, such as when the image data processing unit (IPU) 110 is accessing data within VRAM 120, the same address is applied to both banks of the VRAM 120, and accordingly, the VRAM 120 functions as a unitary 32-bit wide word- storing system.
  • IPU image data processing unit
  • the left- bank address word AB Q (a 16-bit-wide signal) can be different from the right-bank address word AB- j ⁇ (also a 16-bit-wide signal) . They can also be the same when desired.
  • VRAM 120 is programmed to contain image-defining data in a variety of VRAM address regions, including a low-resolution, current frame-buffer region (cFB) 125.
  • the VRAM 120 also contains image-rendering control data in other regions (not shown) and instruction code for execution by the IPU 110 in yet other regions (not shown) .
  • the VRAM 120 will often contain one or more alternate frame-buffer regions (aFB's, not shown) storing low-resolution image data of similar structure to that stored in the current frame-buffer region (cFB) 125.
  • a system variable is occasionally switched to designate one of these other regions as the current frame-buffer, thereby providing a quick means for changing the displayed image en masse.
  • VRAM 120 can also store high-resolution image data (not shown) and the stored high-resolution image data can be transmitted as is to video display unit 160.
  • the front end display driver 105A which includes video- address generator (VAG) 115 and low-resolution pixel clock generator 108, periodically fetches low-resolution formatted display data (e.g. at a rate of 60 fields a second when display driver 105A-105B is operating in NTSC mode) from the system's current frame buffer region (cFB) 125.
  • the fetched data appears in 32-bit-wide parallel format on respective left and right data output buses 122 (even) and 121 (odd) of VRAM 120.
  • Each of the fetched left and right halfwords, Px(LR Q , LC k ) and PxfLR ⁇ LC k ) is structured as shown at 126 to consist of 16 bits.
  • 5 of the 16 halfword bits define one out of 32 possible Red gun intensities
  • 5 of the bits define one out of 32 possible Green gun intensities
  • 4 (or 5 depending on a selected interpolation mode) of the bits define one out of 16 (or 32 depending on mode) possible Blue gun intensities. (Aside: it was found that the human eye is less sensitive to intensity variations at the blue end of the visible spectrum than to those at the red end, hence it is acceptable to provide less variance at the blue end when one of the 16 halfword bits is borrowed for other functions.)
  • the remaining 2 of the 16 halfword bits are referred to as the vertical and horizontal supposition bits, SP V and SP H . They are used by a pixel interpolating portion 159 of resolution- enhancing subsystem 150 for resolution expansion.
  • the format of the current frame buffer (cFB) 125 is 320 x 240 pixels, it is possible to expand its image into a 640 x 480 pixels format by judiciously copying the shading value of each original pixel in the 320 x 240 format (hereafter "low-resolution pixel") to a selected one of 4 corresponding pixel spaces in the 640 x 480 format (hereafter "high-resolution pixel" or "HPx”) .
  • the remaining three pixel spaces in the high-resolution space are filled through the use of an interpolation algorithm.
  • the 2 subposition bits, SP V and SP fl , of each 16-bit halfword control the one-out-of-four placement step.
  • the SPJT subposition bit is positioned adjacent to the least significant bit of the 4-bit blue field.
  • the SP ⁇ subposition bit is replaced by the least significant bit of the 5-bit blue field.
  • the remaining one of the 16 halfword bits is still referred to as the vertical subposition bit, SP V , and it is used in a one-out-of-two placement step to control interpolation. The latter interpolation algorithm will be described later, in conjunction with Fig. 2.
  • a RAM (not shown in Fig. 1) , which functions as a color look-up table (CLUT) , may be included in system 100 to convert the 5/5/4-bit-wide formatted RGB data of data structure 126 into 8/8/8-bit-wide formatted RGB data so as to provide a 24 shading-bits-per pixel RGB format.
  • system 100 (Fig. 1) is assumed to not include a CLUT.
  • a second system 400 of a later-discussed Fig. 4A does include such a CLUT (451,452) .
  • the invention is not restricted to RGB formats.
  • Other digital formats such as YCC, or Composite Video Broadcast Standard (CVBS) , can also be used.
  • RGB format is assumed.
  • an output portion 105B of the display driver converts the output of the resolution-enhancing subsystem 150 into NTSC or PAL or Super-VHS or some other analog signal format, and supplies the converted signal to the video display unit (TV monitor) 160.
  • NTSC display each pair of frames (a frame consists of two fields) is divided into four interlaced fields (FIELDS 1, 2, 3 and 0). The four fields are sequentially flashed to the eyes of a viewer 170 over time to create the illusion of animation.
  • the viewer 170 may be wearing stereoscopic eyeglasses (e.g., liquid crystal shutters) which alternatively block light from reaching one or the other of the viewers left and right eyes so as to create a three-dimensional effect.
  • the stereoscopic image is appropriately distributed across FIELDS 0-1 and 2-3 for such instances.
  • the two fields of a frame will be referred to as Fl and F2 throughout this disclosure.
  • VRAM 120 the storage capacity demands placed on VRAM 120 are small in comparison to those that would have been made if the current frame buffer (cFB) 125 and the alternate frame buffers (aFB's, not shown) had to store data representing an image of higher-resolution.
  • the image-processing bandwidth required from image data processing unit (IPU) 110 is small in comparison to what would have been required if the current frame buffer 125 had to store a higher-resolution image.
  • the frequency at which the video pixel clock 108 operates is reduced and the number of cycles it steals per second from the processor clock 102 (in cases where cycle-steal is used) is also reduced. The overall benefit is reduced cost and speed pressures placed on the design of system 100. Observer 170 nonetheless perceives 172 a high-resolution animated image 165 projected from (or onto) video display unit 160.
  • Mapping 200 shows a plurality of low- resolution pixels (LPx's) 201 as large squares arranged in a regular matrix format on a first of two overlapping planes.
  • the LPx's 201 are arranged to define low- resolution rows LR#0, LR#1, LR#2, LR#3, etc. and low- resolution columns LC#0, LC#1, LC#2, LC#3, etc.
  • the top leftmost low-resolution pixel resides at LR#0, LC#0.
  • a low-resolution row will typically have 40 or more low-resolution pixels.
  • the illustrated example assumes 320 low-resolution pixels per low-resolution row, but this number is not necessarily fixed. It is understood that a high-resolution row will have a substantially larger number of high-resolution pixels, for example, two or more times as many as a low-resolution row.
  • a low-resolution column will typically have 40 or more low-resolution pixels.
  • the illustrated example assumes 240 low-resolution pixels per low- resolution column, but this number is not necessarily fixed. It is understood that a high-resolution column will have a substantially larger number of high- resolution pixels, for example, two or more times as many as a low-resolution column.
  • each low-resolution pixel (LPx) 201 is subdivided into four equal-sized subposition regions (quadrants) : QA, QB, QC, and QD, arranged clockwise in the recited order starting from the top left corner.
  • the mapping 200 in Fig. 2 is to be viewed as further showing an array of equally-spaced high-resolution pixels (HPx's) 204 lying on a second plane directly below the plane of the low-resolution pixels (LPx's) .
  • the equal spacing of the high-resolution pixels 204 is somewhat distorted in Fig. 2 to show groups of four HPx's each associated with a corresponding four subposition regions, QA-QD, of each low-resolution pixel.
  • High-resolution pixels 204 are depicted as dashed (hidden) circles in Fig. 2.
  • High-resolution pixels 204 are individually identified by respective high-resolution row and column numbers, HR and HC.
  • HR and HC high-resolution row and column numbers
  • two numbering systems are used to define the placement of each HPx 204.
  • the high-resolution rows are numbered sequentially, starting from the top, as HR#0.0, HR#0.5, HR#1.0, HR#1.5, HR#2.0, HR#2.5, HR#3.0, and so forth.
  • non-decimated numbering system the same high-resolution rows are numbered sequentially, starting from the top, as HR#0, HR#1, HR#2, HR#3, HR#4, HR#5, HR#6, etc.
  • low-resolution row LR#0 overlaps high-resolution rows HR#0.0 and HR#0.5.
  • Low-resolution column LC#0 overlaps high-resolution columns HC#0.0 and HC#0.5.
  • a similar one-to-two mapping exists between the remaining low-resolution row/columns and the high- resolution rows/columns.
  • the left VRAM output bus 122 will produce pixel-defining data Px(LR Q , LC ⁇ ) representing a low-resolution pixel in column LC k and an even-numbered row, LR Q
  • address signal AB Q is advanced to point to the same column but one row ahead of the low-resolution pixel pointed to by address signal AB, the left VRAM output bus 122 will produce pixel- defining data Px(LR 0 , LC j representing a low-resolution pixel in column LC k but the next-adjacent even-numbered row, LRn, relative to the low-resolution pixel pointed to by address signal AB, .
  • Fig. 2 shows an interpolation window 248 surrounding the four low-resolution pixels 201 found at the intersection of rows LR#0, LR#1 and columns LC#1, LC#2.
  • Interpolation window 248 is subdivided into top and bottom halves, 248a and 248b, and also into left and right halves, 248d and 248c, respectively.
  • the bottom half 248b of interpolation window 248 surrounds the eight high-resolution pixels 204 found at the intersection of rows HR#1.0, HR#1.5, and columns HC#1.0, HC#1.5, HC#2.0, HC#2.5.
  • the four low-resolution pixels in interpolation window 248 will later be referred to as LPxO through LPx3.
  • S, S 2 , S 3 , and S 4 are shown located in prespecified subpositions of the low-resolution pixels (LPx's) of window 248.
  • Each small square, S,-S 4 represents the color and/or shading (e.g., a particular mix of the RGB primaries) assigned to its corresponding low-resolution pixel.
  • the color/shading of squares S -S 4 are respectively designated as "source pen" codes PE ⁇ through PEN-.
  • the two center-most high-resolution pixels within the bottom half 248b of window 248 are referenced as targets T ⁇ and T 12 «
  • the color/shading of targets T,, an 12 are each derived by applying a distance-weighted interpolation algorithm (or an approximation thereof) to the source pen codes, PEN 1 through PEN 4 in accordance with one of the following equations (Eq. la-b or Eq. 2) :
  • N is an integer greater than 1 (e.g., 2, 4, 9, 16)
  • dg-m represents the distance from the center of source square S- to the center of the target high-resolution pixel
  • Q represents a power (e.g., 1, 2, etc.) to which the distance is to be raised
  • c represents a zero-offset constant (e.g., -1, 1, 0.5, 0.1, etc.)
  • PENg ⁇ represents the color/shading of source square S-.
  • PEN Target PEN SiT ⁇ E( 3- lb > •
  • interpolation window (248) can be expanded in the horizontal direction (x) or vertical direction (y) or both by respective steps of one or more low-resolution columns and low-resolution rows if so desired.
  • the number of independently-addressable banks in multi-bank VRAM 120 should be increased by one with each expansion of the window size by an LR step in the vertical direction (y) .
  • the number of time delay registers (155 and 156) would also have to be increased for each window expansion in either the horizontal direction (x) or vertical direction (y) .
  • the illustrated two LR's by two LC's size of window 248 is preferred for minimizing the number of VRAM banks and delay registers (155 and 156) .
  • Equation Eq. la a simplified average of N-choices calculation can be performed, as shown by the following equation Eq. 2, to approximate the results of Eq. la-lb.
  • the source- identifier, j(i) can acquire any value in the series 1, 2, ... , N.
  • PENg • fl) through PENg ⁇ N v can therefore each be equal to PEN S3 , in which case p Nm t takes on the value of PENg 3 .
  • PEN g3 contributes 100% to the value of PEN Target .
  • PENg • ,-» through PEN g j fk > can each be set equal to PEN S2
  • PENg • / j , +1 ⁇ through PENg • are each set equal to PEN g4
  • PENm ar ⁇ e+ - takes on the value of (k/N)*PEN s2 + (N-k/N)*PEN g4 .
  • the amount of contribution of each of PEN g2 and PEN g4 to the final value of PEN Ta et depends on the values chosen for integers k and N.
  • window 248 covers 16 high-resolution pixels (HPx's) , shading does not have to be calculated for all possible targets (high- resolution pixels) within the window in one pass.
  • only two target pixels, T,, and T, 2 are calculated while the window stops a first time over the indicated position (during a so-called field Fl pass) . Later, when the window stops over the indicated position for a second time (during a so-called field F2 pass) , the shading/coloring codes of two other centrally- located target pixels, T 21 and T 22 , are calculated and generated.
  • the interpolation window 248 steps to the right by one low- resolution column (1 LC) and interpolation begins for determining the shading/color of one or more additional target pixels (T ⁇ ) in the corresponding intersection of high-resolution rows HR#0.0-HR#l.5 with high-resolution columns HC#2.0-HC#3.5) .
  • At least two high-resolution target pixels should be calculated and generated by interpolator 159 per window stop.
  • This approach allows interpolation to be carried out on the fly as the video-address generator (VAG) 115 of Fig. 1 scans across the pixels of a low-resolution row in source image 125 in synchronism with the LPx clock generator 108 and display driver end-portion 105B outputs the color/shade/illumination-defining signals for two or more corresponding high-resolution pixels in a high-resolution row of target image 165 in synchronism with the HPx clock generator 158.
  • window 248 When window 248 reaches the end of rows LR#0 and LR#1, it steps down by one low-resolution row, returns to the left edge and scans rightward across low- resolution rows LR#1 and LR#2, again writing out target positions T,, and T, 2 within the window as the codes for high-resolution row HR#2.0. This process repeats for high-resolution rows HR#3.0, HR#4.0, etc., until field Fl completes.
  • window 248 returns to the top left of mapping 200 and repeats the process, this time writing out target positions T 2 , and T 22 within the window as the codes for high-resolution rows HR#0.5, HR#1.5, HR#2.5, etc.
  • vertical interpolation can be selectively turned on or off.
  • the codes written out for reject target positions T 2 ,/T 22 and T,,/T, 2 is adjusted in a more complex way to give the appearance that vertical interpolation is not taking place.
  • Cross-over unit 151 (Fig. 1) is operated to place the appropriate even or odd-numbered pixel signal LPx(LR 0 , ...) or LPx(LR 1 , 7) on the respective A-side bus 154 and B-side bus 153 of resolution-enhancing subsystem 150.
  • AB Q AB
  • AB Q AB 1 + L row , where L is an offset for moving one low-resolution row forward in the address space of memory.
  • Video-address generator (VAG) 115 is appropriately switched to generate the necessary stream of equal or nonequal AB Q and AB, bank address signals.
  • Figures 3A through 3E show one possible set of contribution weightings which can be used within interpolator 159 to determine what contribution a source square S ⁇ within an interpolation window is to make to a target pixel in accordance with equation Eq la.
  • the distance between quadrant QD and target pixel T 21 of the same low-resolution pixel is defined as one unit.
  • the distance between quadrant QB and target pixel T 21 of the same low-resolution pixel is therefore also equal to one unit.
  • the distance between quadrant QA and target pixel T 2 , of the same low- resolution pixel then becomes equal to the square root of two units. Source to target pixel T 2 , distances for further parts of the interpolation window are calculated accordingly.
  • Fig. 3B maps the l/ target pi .xel T 21* contribution weights for respective target pixels T 22 ,
  • N is set to four. Division by four, in order to obtain an average after four contributors are selected and added, can be easily implemented for binary-coded values by a shift right of two bit positions.
  • a single combinatorial logic unit (320 of Fig. 3F, 620 of Fig. 6A) provides the transform function of Fig. 3C, as approximated by equation Eq. 2.
  • the single combinatorial logic unit (320, 620) selects four choices from the set, PEN s ⁇ through PEN g4 , and outputs four 2-bit-wide signals, B0-B3, each representing one of the four choices.
  • the 2-bit "choice" signal is to be distinguished from the PEN code it points to.
  • the PEN code typically has many more bits, fifteen for example.) If the target high-resolution pixel is other than the one shaded in Fig.
  • a forward/backward mapping scheme is used to first transform the subposition coordinates of the corresponding one of Fig.s 3B, 3D and 3E into the coordinates of Fig. 3C; and after combinatorial logic unit (320, 620) outputs the four choice signals, B0-B3, to transform those choices into their equivalents for the corresponding one of Fig.s 3B, 3D and 3E.
  • Fig. 3F illustrates a choice-making system 300 comprised of a 4-by-4 forward-mapping table unit (FMT) 310, a 4-of-4 choice-making table unit 320, and a 4-by- 4 backward-mapping table unit (BMT) 330.
  • the choice- making table unit 320 is structured to choose four unique or duplicate items, B0-B3, from the set, PENg, through PENg 4 , approximately in accordance with the weightings suggested by Fig. 3C.
  • code- conversion Table 1 (This same code-conversion table also describes the operations of later mentioned units 620 and 1620, and hence it is provided at the end of the disclosure.) Referring momentarily to Code-conversion Table 1, it is understood that the 2-bit wide input signal, A0, consists of less significant bit A00 and more significant bit A01. Similarly, the 2-bit wide output signal, BO, consists of less significant bit BOO and more significant bit B01.
  • each of quadrants QA through QD is associated with a corresponding 2-bit-wide subposition value (00, 01, 10, 11) .
  • the assignment of values is shown at 301 in Fig. 3F.
  • Fig. 3F four 2-bit wide signals, SP Q through SP 3 are provided, each representing an interpolation weighting coefficient (or "subposition point") that is assigned to a corresponding one of the four low- resolution pixels, LPxO through LPx3, then residing in the interpolation window 248.
  • This provides the choice- making table unit 320 with a total of eight bits of input information (A0 through A3) which it may use to produce a corresponding set of four choices (B0 through B3) , each 2-bits wide.
  • the choices are preferably arranged as set forth in code-conversion Table 1 to cause above equation
  • Fig. 3F accordingly shows the choice-making table unit 320 receiving four input signals: A0, Al, A2, A3, each two-bits wide, and outputting four choice signals: B0, Bl, B2, B3, each two-bits wide.
  • Forward-mapping table unit (FMT) 310 operates the same for each of low-resolution pixels LPxO through LPx3.
  • Multiplexer 305 supplies each of the corresponding four subposition coordinate signals, SP Q through SP 3 , one at a time to forward-mapping table unit (FMT) 310 for each step of interpolation window 248.
  • Multiplexer 325 supplies each of signals B0-B3, one at a time to backward-mapping table unit (BMT) 330 for conversion.
  • Demultiplexer 335 converts the one- choice at-a-time output of backward-mapping table unit (BMT) 330 to the four appropriately-converted output choice signals: CO, Cl, C2, C3, of choice-making table unit 320. If desired, the backward-mapping table unit (BMT) 330 can be duplicated four times and multiplexer 325 and demultiplexer 335 can then be eliminated from Fig. 3F.
  • BMT backward-mapping table unit 330
  • FIG.s 4A and 4B form a block diagram of a second imaging system 400 which includes a pipelined resolution- enhancing subsystem 450 in accordance with the invention.
  • Like reference symbols in the "400" number series are used where possible for elements of Fig.s 4A,4B which correspond to but are not necessarily the same as those in the "100" series within Fig. 1.
  • VRAM Video-speed Random Access Memory
  • left and right memory banks 420L and 42OR Each of left and right banks 420L and 420R stores 2 datawords. A single dataword is 16-bits wide.
  • Left and right memory banks 420L and 420R are collectively referred to as VRAM 420.
  • imaging system 400 can include other, slower forms of data storage such DRAM and/or RAMBUSTM storage devices that are operatively coupled to transfer data to and from VRAM 420.
  • VRAM 420 should be considered as a cache-like area of system memory into which there is loaded image data that is to be then displayed or otherwise processed.
  • a page-mode SRAM device such as the Toshiba TC524256AJ/AZ-12TM is preferred for forming VRAM banks 420L and 42OR.
  • the Toshiba device is a two-port static- random-access memory device in which one of the ports, a so-called "serial input/output" port (SIO) , outputs a sequential stream of datawords beginning with one stored in an address loaded into a serial address counter (S-CNT) .
  • the serial address counter (S-CNT) is clocked by a serial clock (SC) signal applied to the device from clock generator.
  • the NEC UPD482234TM fast-page VRAM and NEC UPD482235TM hyper-page VRAM are examples of other integrated circuit memory chips that support serial-mode data input and output.
  • respective left and right clock generators, 408L and 408R are separately coupled to the serial clock input terminals of VRAM banks 420L and 42OR.
  • Each of clock generators, 408L and 408R operates at 6.13635 MHz, but the signals are provided out of phase to provide a combined frequency of 12.2727 MHz.
  • Left and right clock generators 408L and 408R are synchronized to a shared video reference clock signal, CV25M, which operates at 24.5454 MHz.
  • Fig. 4C shows the corresponding signals, LSC ⁇ (inverted left serial clock) and RSC ⁇ (inverted right serial clock). They are derived from the 24.5454 MHz video reference clock, CV25M.
  • serial input/output port (SIO) of the Toshiba TC524256AJ/AZ-12TM is tri-stateable and goes into a high- impedance state (Hi-Z) when a low serial-output enable (SOE) signal is applied to the device.
  • This feature is used advantageously in system 400 to multiplex the SIO outputs of the left and right VRAM banks, 420L and 42OR, over time onto upper and lower halves of a soon-to-be described S-bus 423.
  • Each Toshiba SRAM device has a second so-called "data input/output" port (DIO) which outputs datawords one at a time in accordance with a D-port address stored in another register (not shown) of the device.
  • DIO data input/output
  • the 16-bit-wide DIO ports of VRAM banks 420L and 420R combine at the data input/output port (D) of CPU 410 to define a unitary 32-bit-wide data word for purposes of image data processing.
  • the right VRAM bank 42OR stores bits 0 through 15 and the left VRAM bank 420L stores bits 16 through 31.
  • Fig. 4A shows a memory address manipulator chip (MAMC) 415 supplying respective left and right address signals, LA and RA (each 9-bits wide) , to the address input ports of left and right VRAM banks 420L and 420R.
  • the MAMC 415 also applies respective left and right control signals, L-CTL and R-CTL, to control input ports of left and right VRAM banks 420L and 42OR.
  • Independent SOE signals are included within the L-CTL and R-CTL control signals supplied to each of VRAM banks 420L and 420R. These are respectively designated as L-SOE and R-SOE.
  • the 16-bit-wide SIO port 422 of left VRAM bank 420L connects to an upper 16-bit-portion, S(31:16) of a 32- bit-wide S-bus 423.
  • the 16-bit-wide SIO port 421 of right VRAM bank 42OR connects to a lower 16-bit-portion, S(15:0) of the same 32-bit-wide S-bus 423.
  • the outputs of left and right SIO ports 422 and 421 are time- multiplexed onto the S-bus 423 in synchronism with the 24.5454 MHz clock, CV25M, as shown in Fig. 4C.
  • FIG. 4C the waveforms of signals, CV25M, LSC ⁇ , RSC ⁇ , S(31:16) and S(15:0) are shown in time alignment at the top of Fig. 4C.
  • Valid data states on S- bus portions, S(31:16) and S(15:0), are denoted as "V” and "D", where "V” represents valid Video datawords and "D” represents valid instances of so-called slip-stream data.
  • Fig. 4A shows a 24-bit wide slipstream data source 424 also coupled to S-bus 423.
  • the slipstream data source 424 has tristatable output lines so that its signals can be time-multiplexed onto the S-bus 423 with the VRAM SIO signals 421 and 422.
  • Fig. 4C there are two instances of valid slip-stream data between each valid video dataword on each of S-bus portions, S(31:16) and S(15:0).
  • the 24- bit wide "D" dataword is subdivided into a first, 16-bit wide, less-significant portion followed by a second, 8-bit wide, more-significant portion.
  • the 8-bit wide, more-significant portion of the slipstream data is output, the remaining 8 lines of the upper or lower S-bus portion carry don't care bits.
  • V datawords of S-bus portions, S(3l:16) and S(15:0) are non-overlapping.
  • V and D datawords are introduced serially into the resolution enhancing subsystem 450 and processed in pipelined fashion thereafter.
  • the left edge of Fig. 4C represents the end of a horizontal blanking interval.
  • the first two active high or low states of a tri-statable ADOUT signal at the bottom of Fig. 4C represent the first 24-bit-wide pixel of a high-resolution video line.
  • both the LSC ⁇ and RSC ⁇ signals are held high. As the horizontal blanking interval comes to an end, one of the LSC ⁇ and RSC ⁇ signals goes active low before the other.
  • Fig. 4C shows LSC ⁇ becoming active low first. It is to be understood, however, that RSC ⁇ could have been the one to become active low first.
  • Control signals (not shown) from the memory address manipulator chip (MAMC) 415 determine which of clock generators 408L and 408R turns on first at the end of each horizontal blanking interval. This determination produces an effect similar to the function of cross-over unit 151 (Fig. 1) , except that signal cross-over switching is now done by way of time-domain multiplexing in pipeline fashion rather than spatially.
  • S-bus 423 crosses an inter-chip boundary demarcated by a dash-dot line at the bottom of Fig. 4A and top of Fig. 4B.
  • Left and right serial clock signals, LSC and RSC also cross the inter-chip boundary.
  • the circuitry of a so-called CLUT/INT/OUT chip 430 begins below the dash-dot line.
  • An S-Bus capture-control unit 431 is provided within CLIO chip 430 for controlling a set of S-Bus capture registers, 432-439, and capture-reordering multiplexers, 441-443.
  • the set of registers 432-439 have inputs coupled to both upper and lower portions of S-bus 423 for picking off the left and right "V" signals that are time- multiplexed onto S-bus 423.
  • a set of "CAPCLK” (capture clock) signals strobe the S-bus capture registers 432- 439, causing them to capture the appropriate time- multiplexed signals from the S-bus 423 at the appropriate points in time.
  • a set of "CAPSW” (capture switching) signals control the capture-reordering multiplexers, 441- 443, causing them to output appropriate time-multiplexed signals from the capture registers 432-439 onto respective multiplexer output busses 441o (15-bits wide) , 442o (2-bits wide) , and 443o (24-bits wide) , at the appropriate points in time.
  • CAPSW capture switching
  • reordering multiplexer 441 has two 15-bit-wide inputs respectively coupled to the outputs of a 15-bit-wide LRGB-capture register 432 and a 15-bit-wide HRGB-capture register 433.
  • LRGB- capture register 432 captures a 15-bit wide RGB video ("V") signal that is presented at various times on a lower portion (bits 15:00) of S-bus 423.
  • HRGB-capture register 433 captures a 15-bit wide RGB video (“V”) signal that is presented at various times on an upper portion (bits 31:16) of S-bus 423.
  • the 15-bit-wide output 441o of multiplexer 441 produces a 15-bit-wide serial stream of RGB signals corresponding to those alternately presented on the upper or lower portions of S-bus 423.
  • RGB video-signals presented on one of the upper and lower portions of S-bus 423 are deemed as those belonging to a "previous” low-resolution row and "RGB” video-signals presented on the other of the S-bus portions are deemed as those belonging to a "current" low-resolution row.
  • the output order on bus 441o is previous first, then current, then previous, then current, and so forth.
  • Reorder multiplexer 442 has two 2-bit-wide inputs respectively coupled to the outputs of a 2-bit-wide LSP- capture register 434 and a 2-bit-wide HSP-capture register 435.
  • LSP-capture register 434 captures a one- or-two bit wide "subposition" ("SP") signal that is presented at various times on the lower portion (bits 15:00) of S-bus 423.
  • HSP-capture register 435 captures a one-or-two bit wide "subposition” (“SP”) signal that is presented at various times on the upper portion (bits 31:16) of S-bus 423.
  • the 2-bit-wide output 442o of multiplexer 442 produces a 2-bit-wide serial stream of SP signals corresponding to those alternately presented on the upper or lower portions of S-bus 423.
  • SP- signals presented on one of the upper and lower portions of S-bus 423 are deemed as those belonging to a "previous" low-resolution row and SP-signals presented on the other of the S-bus portions are deemed as those belonging to a "current" low-resolution row.
  • the output order on bus 442o is previous first, then current, then previous, then current, and so forth.
  • the RGB and SP output signals of reorder multiplexers 441 and 442 are derived from the 16-bit- wide data structure 126 shown in Fig. 1.
  • 4-bit blue mode the least significant bit in the 5- bit-wide Blue gun field is forced to zero by circuitry within multiplexer 441 (not shown) and the remaining 2 of the 16 halfword bits on one of the S-bus upper and lower halves then serve as the vertical and horizontal subposition bits, SP V and P H , that are output by reorder multiplexer 442.
  • Reordering multiplexer 443 has two 24-bit-wide inputs respectively coupled to the outputs of a 24-bit- wide LSS-capture(2) register 438 and a 24-bit-wide HSS- capture(2) register 439.
  • a 16-bit wide LSS-capture register(1) 436 first captures, on a first tick of the video reference clock signal, CV25M (24.5454 MHz), a 16-bit wide, less-significant portion of a "slip-stream" (SS) signal that is presented on the lower portion (bits 15:00) of S-bus 423.
  • the 24-bit-wide LSS-capture(2) register 438 next captures, on a second tick of video reference clock signal, CV25M, an 8-bit wide, more- significant portion of the slip-stream (SS) signal that is then present on the lower portion (bits 15:00) of S-bus 423 plus the previously captured 16-bits now output by register 436.
  • a 16-bit wide HSS-capture register(l) 437 first captures, on a first tick of the video reference clock signal, CV25M, a 16-bit wide, less-significant portion of a "slip-stream" (SS) signal that is presented on the upper portion (bits 31:16) of S-bus 423.
  • the 24- bit-wide HSS-capture(2) register 439 next captures, on a second tick of video reference clock signal, CV25M, an 8-bit wide, more-significant portion of the slip-stream (SS) signal that is then present on the upper portion (bits 31:16) of S-bus 423 plus the previously captured 16-bits now output by register 437.
  • the 24-bit-wide output 443o of multiplexer 443 produces a 24-bit-wide serial stream of SS signals corresponding to those alternately presented on the upper or lower portions of S-bus 423.
  • the S-bus control circuit 431 also produces a previous/current designating signal 446 for designating signals streaming down multiplexer output bus 44lo as belonging either to a previous or current low-resolution row.
  • the previous/current designating signal 446 is formed by clocking a Toggle-type flip flop with the video reference clock signal CV25M (24.5454 MHz) .
  • the Toggle-type flip flop (not shown) is reset before the start of a scan through a current low- resolution row. The delay between the reset time and the time of start of a corresponding stream of data down bus 441o is adjusted such that the first data item is deemed "previous".
  • the output 441o of capture-reordering multiplexer 441 connects to an input of a 15-bit-wide demultiplexer 445.
  • Demultiplexer 445 has two 15-bit-wide output buses, 445a and 445b, respectively coupled to the address inputs of two color look-up table units (memory banks) .
  • Demultiplexer 445 responds to the previous/current line- of-origin designating signal 446 provided to a control terminal thereof from the S-bus control unit 431 and routes the signals at its input (44lo) to one or the other of the two color look-up table units in accordance with the "previous" versus "current" line-of-origin designation provided by the line-of-origin designating signal 446.
  • the two color look-up table units are referred to as the A-CLUT 451 (current low-resolution video line color palette) and the B-CLUT 452 (previous low-resolution video line color palette) .
  • a CLUT bypass bus 447 is also provided for carrying the 15-bit wide output 441o of capture-reordering multiplexer 441 to a CLUT-bypass unit 448.
  • the function of unit 448 is explained later below.
  • the A-CLUT 451 is a multi-port random access memory device (RAM) which has three independent address input ports (AI's, each 5-bits wide) for receiving compressed 15-bit RGB signals.
  • the 15-bit wide RGB signal is composed of 5 bits of R (e.g.. Red intensity) data, 5 bits of G (e.g., Green intensity) data, and 5 bits of B (e.g., Blue intensity) data which are respectively applied to the three Al ports of the A-CLUT 451.
  • the A-CLUT 451 further has three corresponding data output ports (DO's) for outputting 24-bit-wide decompressed RGB datawords 451o associated with addresses supplied at the AI's.
  • the 24-bit wide RGB output signal 451o is composed of 8 bits of R (e.g., Red intensity) data, 8 bits of G (e.g.. Green intensity) data, and 8 bits of B (e.g.. Blue intensity) data which are respectively output from the three DO ports of the A-CLUT 451.
  • the A-CLUT 451 also has a serial data input port (SDI) for receiving data which is downloaded into the A-CLUT 451 during each horizontal blanking interval.
  • SDI serial data input port
  • Color-palette conversion data for converting each 5-bit- wide color/shading code of the RGB domain into an 8-bit- wide color/shading code (in the RGB domain) is down ⁇ loaded from the VRAM (420L and/or 42OR) through the SDI data-input port of the A-side CLUT 451 at the end of each line-display period (during the horizontal blanking period) .
  • Old data within A-CLUT 451 shifts out to load B-CLUT 452 during this process.
  • the "current" video line palette thereby becomes the "previous” video line palette as processing of the current video line completes. This is required for proper interpolation if interpolation is to use CLUT-converted pen values.
  • the horizontal blanking interval is also used for downloading new mode and path-control signals into the CLIO chip 430 such that the chip can switch its operating mode for each new line of video data.
  • Each of the three sections within A-CLUT 451 stores at least 32 datawords, each 8-bits wide.
  • Demultiplexer output bus 445a is divided into three 5-bit-wide parts which respectively connect to the three AI's of the A-CLUT 451.
  • Each 5-bit-wide Al signal converts to an 8- bit-wide as it passes through A-CLUT 451.
  • the combined 24-bit-wide output of A-CLUT 451 connects to a 24-bit- wide input port 453a of a subsequent multiplexer 453.
  • B-CLUT 452 is similarly structured to convert the 15-bit-wide signal on demultiplexer output bus 445b into a 24-bit-wide RGB output signal 452o that is supplied to another 24-bit-wide input port 453b of subsequent multiplexer 453.
  • A-CLUT 451 and B-CLUT 452 are software-defined parts distributed across three SRAM's. Each of these SRAM's (not shown) has its own 7-bit-wide, independent address input port (Al) , and stores 66 bytes. The 66 bytes are divided into a first bank of 33 bytes and a second bank of 33 bytes. Five of the bits in the 7-bit address field receive the 5 R or G or B bits as above and they select one of the first 32 bytes in either the first bank or the second bank. A sixth bit in the 7- bit address field acts as the bank-select bit (previous/current designating bit 446) .
  • the seventh address input bit defines a background-mode bit. It is used to override the selection of the first five address bits and instead output the thirty-third (33rd) byte of the selected bank as a "background" color.
  • RGB is not the only way to implement the invention.
  • the CLUT SRAM could store data in YCC format or any other desired format.
  • CLUT-bypass unit 448 is used if color conversion is to be bypassed. Color conversion can be bypassed on a line-byline basis.
  • the connects to CLUT-bypass unit 448 converts the 15-bit-wide RGB signals of multiplexer output bus 441o into 24-bit-wide RGB signals by padding three zero bits or other data into each of the R, G and B fields, thereby converting the 5-bit-wide original fields into 8-bit-wide fields.
  • the received 5-bits of R or G or B intensity fill the 5 MSB's (most significant bits) of each 8-bit-wide output generated by the CLUT-bypass unit 448 .
  • the 3 LSB's (least significant bits) of each 8-bit-wide output are selectively forced equal to either (a) zero, or (b) the same value as that of the 3 MSB's, or (c) a 3-bit value produced by a pseudo-random number generator (not shown) .
  • the latter option produces an eye soothing color dither when an appropriate pseudo-random function is chosen.
  • the previous/current designating signal 446 controls multiplexer 453 so as to selectively couple either the 24-bit-wide output 451o of the A-CLUT 451 or the 24-bit- wide output 452o of the B-CLUT 452 to a 24-bit wide A-input of a bypass multiplexer 454.
  • a 24-bit wide B-input of the bypass multiplexer 454 receives the output of CLUT-bypass unit 448.
  • a CLUT-bypass control signal 454c is applied to the control terminal of the bypass multiplexer 454 for selecting either the output of previous/current selecting multiplexer 453 or the output of CLUT-bypass unit 448 as the output of the bypass multiplexer 454.
  • Multiplexer control signal 454c is user-programmable (by path-control data downloaded during the horizontal blanking interval) for selecting either the CLUT outputs (451o and 452o) or the output of the CLUT-bypass unit 448 as the output of bypass multiplexer 454 on a line-by-line basis.
  • the AI-to-DO signal propagation delay of CLUT units 451 and 452 is approximately 4 ticks of the video reference clock signal CV25M (24.5454 MHz).
  • the CLUT- bypass unit 448 has a similar delay incorporated into it so that the same delay timing occurs regardless of whether signals flowing from the output 44lo of capture- reordering multiplexer 441 by way of CLUT 451/452 or bypass unit 448 are used. (A below described combination of units 457 and 458 is provided with a similar 4-tick delay to match the signal propagation delay of CLUT units 451 and 452.)
  • bypass multiplexer 454 couples to a 24-bit-wide destacker input bus 455i. Signals on the destacker-input bus 455i change in synchronism with the video reference clock signal CV25M (24.5454 MHz).
  • the sequence of time-multiplexed 24-bit-wide signals on bus 455i is represented in Fig. 4B as an over-time stack of datawords labeled 0,3,1,2 next to line 455i. This sequence will be explained in more detail later, in conjunction with Fig. 5. Note for now, however, that the sequence of signals is also labelled P/C/P/C/... to represent a preferred sequence of data alternatingly belonging to a previous and current row of the low- resolution source image 125 (see Fig. 1) .
  • a 24-bit destacker 455 is provided for converting the format of signals output by bypass multiplexer 454 (or alternatively signals output by slipstream multiplexer 443) from an over-time serial format to a pipelined time-parallel format. This will also be explained in more detail when Fig. 5 is discussed.
  • Destacker 455 produces four destacked signals, LPxO, LPxl, LPx2, LPx3, in parallel pipelined fashion, where each signal is 24-bits-wide.
  • Destacked signals, LPxO, LPxl, LPx2, LPx3, are then supplied to interpolator 459 for interpolation.
  • interpolator 459 A preferred embodiment of interpolator 459 will be explained in more detail later, in conjunction with later described Fig.s 6A-6D, 7 and 8.
  • interpolator 459 produces an interpolated output signal 460 (RGB-OUT) in accordance with the values of destacked signals, LPxO, LPxl, LPx2, LPx3 , and in accordance with four subposition signals SPO, SP1, SP2, SP3, supplied to it from a 2-bit destacker 456 by way of a choice-making unit 457 and a choice-capturing multiplexer unit 458.
  • Interpolator unit 459 should be viewed as being capable of combining its received destacked signals, LPxO, LPxl, LPx2, and LPx3, in accordance with any one of a plurality of predefined interpolation algorithms.
  • the applied subposition signals, SPO, SP1, SP2, and SP3, select one of those predefined interpolation algorithms as the algorithm that is to be followed by interpolator unit 459.
  • the 2-bit destacker 456 operates in similar fashion as does the 24-bit destacker 455. It (the 2-bit destacker 456) converts serially-arranged subposition data delivered to it over a 2-bit-wide destacker-input bus 456i from the SP-reordering multiplexer 442 into a set of four time-parallel subposition signals, SPO, SP1, SP2, SP3 (each 2-bits-wide) . These four signals (SP0-SP4) then pass into choice- making unit 457. Choice-making unit 457 generates four choice signals CO, Cl, C2, and C3.
  • Choice-capturing multiplexer unit 458 captures the choice signals CO, Cl, C2, C3, (or modified choice signals MO, Ml, M2, and M3) generated by choice-making unit 457. Two of the four choice signals (C0-C3) are selected by the choice-capturing multiplexer unit 458, delayed to compensate for the delay of the 24-bit path (the path between multiplexer output 44lo and the 24-bit destacker input 455i) , and then forwarded in a first clock cycle to the interpolator 459 as delayed/multiplexed signals, MxO and Mxl (each of which is 2 ⁇ bits wide) .
  • the two non-selected ones of choice signals, CO, Cl, C2, C3, are pipelined in the choice- capturing multiplexer unit 458 and forwarded to the interpolator 459 as delayed/multiplexed signals, MxO and Mxl, in the next clock cycle.
  • the timing of the delayed/multiplexed signals, MxO and Mxl, over repeated first and second cycles, is represented by strobe signals, 2PL1 and 2PL2.
  • the combined signal propagation delay of choice- making unit 457 and choice-capturing multiplexer unit 458 is set to 4-ticks of the video reference clock signal CV25M (24.5454 MHz) to match the signal propagation delay of CLUT units 451 and 452 (or CLUT-bypass unit 448) so that delayed/multiplexed signals, MxO and Mxl, arrive at interpolator 459 in synchronism with corresponding signals LPx0-LPx3.
  • Interpolator 459 generates a 24-bit-wide interpolated output signal 460 by adding the sum of two, nonexhaustively chosen LPx's to the sum of two nonexhaustively, further chosen LPx's, thereby creating a sum of four, nonexhaustively chosen LPx's.
  • Interpolated output signal 460 passes through a 24- to-12 bit multiplexer 465 where it is converted from a 24-bit-wide per two-cycles format to two a format of two 12-bit-wide signals alternated over the two cycles.
  • the 12-bit-wide signal 469 output by the 24-to-12 bit multiplexer 465 is shown in Fig. 4C as an ADOUT signal.
  • This ADOUT signal is transmitted out of the CLIO chip 430 at the video rate of 24.5454 MHz and thereafter it is displayed on a high-resolution monitor (e.g., a color CRT or color LCD panel, not shown) .
  • a high-resolution monitor e.g., a color CRT or color LCD panel, not shown.
  • the parallel-to-serial-to-parallel conversions help to reduce the die-size and pin count of the CLIO chip 430 and help to take full advantage of the limited throughput bandwidth available on the S-bus 423. Note for example, that only 12 output pins are used for outputting the 12-bit-wide ADOUT output signal 469 from the CLIO chip 430.
  • the output of capture-reordering multiplexer 441 is only 15-bits-wide rather than 30- bits-wide because of the use of demultiplexer 445.
  • previous/current selecting multiplexer 453 merges into the CLUT address-processing circuitry and DO busses 451o and 452o are implemented within the CLIO chip 430 as one 24-bit-wide bus, thereby consuming less space within the CLIO chip 430.
  • the 24-bit destacker 455 demultiplexes the signals of de ⁇ tacker-input bus 455i in groups of four to produce a time parallel set of four pixel color/shade/illumination value defining signals, LPxO, LPxl, LPx2, and LP 3, each being 24-bits-wide. These signals correspond to the four source pixels of
  • Flipflops 1404 and 1405 are similarly clocked by CV25M and they respectively produce delayed versions, RSCAP and LSCAP, of serial clock signals, RSC ⁇ and LSC ⁇ .
  • the Q- bar output (QN) of flipflop 1403 passes through inverter 1406 to produce capture-enabling signal CAPCLKENB.
  • OR gate 1410 applies the logic OR of signals LSCAP and CAPCLKENB to the inhibit (INH) terminal of 16-bit wide HV-CAP register 1433 for capturing RGB data and SP data into that register 1433 from the upper portion (bits 31:16) of the S-bus 423.
  • HV-CAP register 1433 is clocked by the CV25M video reference clock.
  • OR gate 1412 supplies the logic OR of signals RSCAP and CAPCLKENB to the INH terminal of 16-bit wide LV-CAP register 1432.
  • LV-CAP register 1432 captures RGB and SP data off the lower portion (bits 15:0) of S-bus 423.
  • the LV-CAP register 1432 is clocked by the CV25M signal.
  • HS-CAP1 register 1437 and LS-CAPl register 1436 are each clocked by an inverted version of the video reference clock signal CV25M.
  • OR gate 1414 applies a signal CAPL, which is the logic or of RSCAP and CAPCLKENB, to the INH terminal of register 1437.
  • OR gate 1416 supplies a signal CAPR which is the logic or of signals LSCAP and CAPCLKENB to the INH terminal of register LS-CAPl 1436.
  • the 16-bit wide input of HS-CAP1 register 1437 connects to the upper portion of S-bus 423.
  • the 16-bit wide input of LS-CAPl register 1436 connects to the lower portion of S-bus 423.
  • the 16-bit wide output of register 1437 is referenced as LDATA(15:0).
  • the 16-bit wide output of register 1436 is referenced as RDATA(15:0).
  • Register HS-CAP2 1438 has a 24-bit wide input which receives the LDATA(15:0) signal from register 1437 and additionally, bits 23 through 16 of S-bus 423.
  • LS-CAP2 register 1439 also has a 24-bit wide input which receives signal RDATA(15:0) from register 1436 plus bits 7 through 0 of S-bus 423.
  • the 24-bit wide outputs of registers 1438 and 1439 represent upper and lower captured portions of the slipstream data. These signals are applied to opposed inputs of multiplexer 1443. The output of multiplexer 1443 becomes the 24-bit wide slipstream output signal 443o.
  • V-CAP registers 1432 and 1433 are applied to opposed inputs of multiplexer 1441.
  • the signal select terminal of multiplexer 1441 is driven by set/reset flipflop 1440.
  • a logic one ("1") on the Q-bar output of flipflop 1405 sets flipflop 1440.
  • a logic one ("1") on the Q-bar of flipflop 1404 resets flipflop 1440.
  • Flipflop 1440 is clocked by the CV25M video reference signal.
  • the 16-bit wide output 144lo of multiplexer 1441 represents the combination of buses 44lo and 442o of Fig. 4B.
  • a conceptual view of system 400 is shown.
  • Data words from left memory bank 1420L and right memory bank 142OR are interleaved as shown and sequenced into pipelined system 1450.
  • the data word which is applied earliest in time represents the color/shading of a low-resolution pixel in the current low-resolution row (cLR) and current low resolution- column (cLC) .
  • the next data word represents low resolution pixel in the previous low resolution row (pLR) and the current low resolution column (cLC) .
  • the third applied data word represents a low resolution pixel in the current low resolution row (cLR) and previous low resolution column (pLC) .
  • the fourth supplied data word represents the color/shading of a low resolution pixel in the previous low resolution row (pLR) and previous low resolution column (pLC) .
  • Fifteen-bit wide portions of these interleaved data words pass through CLUT unit 1451 where they are expanded into a corresponding interleaved stream of 24-bit wide data words (referred to as PEN signals) .
  • PEN destacker 1455 outputs these data words in time parallel form as shown.
  • the "p” represents previous in the destacked formation.
  • the "c” represents current.
  • "LR” represents a low resolution row.
  • LC represents a low resolution column.
  • corresponding 2-bit wide subposition data words move through delay matching unit 1458 and into SP destacker unit 1456 for destacking by the SP destacker unit 1456.
  • the signal-propagation delay of delay matching unit 1458 is set substantially equal to the signal-propagation delay of CLUT unit 1451 so that corresponding supposition data and PEN data are applied in synchronism to interpolator unit 1459.
  • the 24-bit-wide signals appearing on destacker- input bus 455i are identified in order as SO, S3, SI, S2, SA and SB according to their time of appearance, SO being the first in time. These signals pass through multiplexer 500 onto bus 500o when slipstream mode is inactive.
  • slipstream mode If slipstream mode is active, one or more of the corresponding slipstream signals, SS0, SS3, SSI, SS2, SSA and SSB, moving downstream along slipstream input bus 443o.l can be substituted, by appropriate actuation of multiplexer 500, for a corresponding one or more of signals SO, S3, SI, S2, SA and SB on bus 455i.
  • slip stream pixels are interpolated by pretending that a "previous” line exists and the pixels of the previous slipstream line are the same as those of the current slipstream line. Substitution of slipstream pixels in place of some of the VRAM produced pixels creates a picture-in-picture effect. Interpolation can be used to smooth the seam between a slipstream image region and an immediately adjacent VRAM image region. Note that the VRAM data originates in a 15 bits per pixel RGB format, the slipstream data originates in a 24 bits per pixel RGB format, and yet the two can be merged into a single image.
  • Destacker unit 455 includes five 24-bit-wide latches respectively labeled as 501, 502, 511, 512 and 522.
  • the REGCLKl pulse signal is applied to the latch-enable (E) terminal of latch 501.
  • the REGCLK2 pulse signal is applied to the latch-enable (E) terminals of the remaining latches, 502, 511, 512 and 522.
  • Destacker- input bus 500 connects to the inputs of latches 501 and 502.
  • the output of latch 511 defines signal node LPxl (named after the signal generated there) and also connects by way of multiplexer 531 to the input of latch 512.
  • one or more of delayed slipstream signals, SS0', SS3', SSI', SS2', SSA' and SSB', moving downstream along slipstream input bus 443o.2 can be substituted, by appropriate actuation of multiplexer 531, for a corresponding one or more of the normal video ("V") signals passing from latch 511 to latch 512.
  • the output of latch 512 defines signal node LPxO.
  • the output of latch 502 defines signal node LPx2 and also connects by way of multiplexer 532 to the input of latch 522.
  • one or more of delayed slipstream signals, SS0', SS3', SSI', SS2', SSA' and SSB', moving downstream along slipstream input bus 443o.2 can be substituted, by appropriate actuation of multiplexer 532, for a corresponding one or more of the normal video ("V") signals passing from latch 502 to latch 522.
  • V normal video
  • the signals present at respective nodes LPxl, LPxO, LPx2 and LPx3 are still SI, SO, S2 and S3.
  • the signals present at respective nodes LPxl, LPxO, LPx2 and LPx3 are replicas of SA, SI, SB and S2, where SI and S2 represent pixel values of a previous column in the low-resolution image matrix and SA and SB represent pixel values of a current column in the low-resolution image matrix (see Fig.s 1 and 2).
  • the 2-bit destacker 456 (Fig. 4B) operates in the same way except it consists of 2-bit-wide latches rather than 24-bit-wide latches and it does not process slipstream data.
  • Fig. 6A shows one such process in more detail.
  • the destacked subposition signals, SPO, SP1, SP2, SP3, are delivered in parallel to a forward-mapping unit (FMU) 610 together with target configuration signals X and Y.
  • FMU forward-mapping unit
  • Target configuration signal Y is generated by Y-generating circuit 600.
  • Video clock signal CV25M 24.5454 MHz drives the clock inputs of D-type flip flops 601 and 602.
  • a READENB signal resets flip flop 601 at the end of each horizontal blanking interval.
  • Flip flop 601 has its Q ⁇ (read this as Q-bar or Q-not) output coupled to its D input so that it toggles its state each time it is enabled by the CAPCLKENB signal (developed in Fig. 4D as the delayed logical AND of LSC ⁇ and RSC ⁇ (In Fig. 6A, SPN is the negative sampling node of flip flop 601.)
  • Flip flop 602 provides a one tick delay and forwards both the noninverted (Q) and inverted (Q ⁇ ) versions of the toggling signal to multiplexer 603.
  • Forward-mapping unit (FMU) 610 converts the four destacked subposition signals, SPO, SP1, SP2, SP3, into universal subposition signals A0, Al, A2, A3, in accordance with earlier-described Fig. 3F. Internally, FMU 610 comprises four combinatorial logic circuits each providing the function of forward-mapping table unit 310.
  • CMU 620 converts the four universal subposition signals A0, Al, A2, A3, into four universal choice signals, B0, Bl, B2, B3, in accordance with earlier-described Fig. 3F.
  • CMU 620 comprises a plurality of combinatorial logic circuits which provide the function of below code- conversion TABLE 1 (ITPCON.FDS) .
  • Backward-mapping unit (BMU) 630 converts the four universal choice signals, B0, Bl, B2, B3, into target- configuration specific choice signals CO, Cl, C2, C3, in accordance with earlier-described Fig. 3F.
  • BMU 630 comprises four combinatorial logic circuits each providing the function of forward-mapping table unit 330.
  • Choice signals CO, Cl, C2, and C3 pass on to corresponding ones of choice-revising units, 640, 641, 642, and 643.
  • the choice-revising units 640 through 643 convert choice signals CO, Cl, C2, and C3 to respective, modified choice-signals M0, Ml, M2, and M3 in accordance with a horizontal-interpolation activating signal, HION, and a vertical-interpolation activating signal, VION, supplied to units 640-643.
  • choice-revising units 640-643 convert choice signals CO, Cl, C2, and C3 to respective, modified signals MO, Ml, M2, and M3 so as to give the impression that the respective horizontal or vertical interpolation operation has been turned off.
  • the code-conversion processes of each of choice- revising units 640-643 is the same and is given by the below code-conversion TABLE 2 (HVON.FDS).
  • Table input terms Cxi and CxO represent respective more and less- significant bits of a corresponding one, Cx, of 2-bit wide signals C0-C3.
  • Table output terms Mzl and MzO represent respective more and less-significant bits of a corresponding one, Mz, of 2-bit wide signals M0-M3.
  • Fig.s 6B.1 and 6B.2 are provided to explain the operations of units 640-643 by way of example.
  • the high-resolution target pixel (T) is shown located within interpolation window 248 in quadrant QC of low-resolution pixel LPxO.
  • subposition points SP0-S3 are positioned such that SPl is placed very close to the target (T) while SPO, SP3 and SP2 are positioned as far away as possible from the target position (T) .
  • choice-revising units 640-643 will replace each choice of LPxl with a substitute choice of LPxO. If LPx2 is selected as one of the C0-C3 choices, that selection will be replaced by a choice of
  • the result of executing both algorithms is that the same choice value will be output four times to the interpolator 459, where the same choice value is the color/shading code of the low resolution pixel under which the target high resolution pixel (T) resides.
  • Figs. 6A, 6B.1 and 6B.2 The approach taken in Figs. 6A, 6B.1 and 6B.2 is simple and effective. However, it suffers from a slight drawback. Looking momentarily back to Fig. 6B.1, note that subposition point SPl contributes most heavily to the choice-making process of units 610-630 because SPl is positioned closest to the target point (T) . Ideally, if horizontal interpolation is supposed to be turned off, subposition point SPl should not in any way bias the choices made by units 610-630. But in the post-choice revising scheme of Fig. 6A, it does.
  • a second approach in accordance with the invention modifies the subposition values (SP0-SP3) before they are applied to choice-making units 610-630.
  • This pre-choice modifying scheme reduces the problem of bias from supposedly not- present subposition signals.
  • original subposition point SPl is shifted to a new, modified subposition point, MSPl, thereby moving further away from the target position (T) .
  • Original subposition SP2 is shifted to new, modified subposition MSP2 to again increase its distance away from the target position (T) .
  • original subposition point SPO is shifted right to create the new, modified subposition point MSPO which is closer to target position T.
  • SP3 is shifted right to new position MSP3 which is closer to target position T.
  • Fig. 6D.2 shows the counterpart algorithm for the case where vertical interpolation is turned off but horizontal interpolation in left on.
  • the top or bottom half of window 248 in which the target resides is defined as "interesting”.
  • the half in which the target does not reside is deemed as "uninteresting”.
  • the subposition- modifying algorithm is then defined as follows:
  • Fig. 6C shows the circuit for performing the above functions. Note that subposition-modifying units 1640- 1643 are now placed ahead of choice-making units 610- 630. A different code-conversion table is used to define each of subposition-modifying units 1640-1643.
  • the below code-conversion tables 3.0 through 3.3 respectively define the input and output bits of respective modifying units 1640 through 1643.
  • Input parameter SPxl represents the more significant bit
  • input parameter SPxO represents the less significant bit of a respective subposition signal SPx selected from a respective one of SP0-SP3.
  • output parameters MSPxl and MSPxO represent respective more and less significant portions of each output signal MSPx selected from the set MSPO- MSP3.
  • the respective outputs of units 640-643 in Fig. 6A are referenced respectively as M0-M3.
  • the outputs of unit 630 in Fig. 6C is similarly referenced as M0'-M3'.
  • the modified choices M0-M3 (or M0'-M3' if the embodiment of Fig. 6C is used) are next applied to the illustrated MUXCAP unit 458.
  • Eight-bit wide register 705 captures the modified choice signals M0-M3.
  • a CAPEND7B signal connects to the inhibit (INH) terminal of register 705 to define the choice capture time.
  • the CAPEND7B signal represents the capture enable signal CAPCLKEN (see Fig. 4C) where the delay is seven ticks of the CV25M video reference clock.
  • Register 701 develops the CAPEND7B signal from a supplied CAPEND6B signal.
  • Register 702 develops a further delayed signal CAPEND8B from the CAPEND7B signal.
  • the 8-bit wide output of register 705 is subdivided into one-tick delayed signals M0", Ml", M2", and M3". These delayed signals correspond to the modified choice signals M0-M3 (or M0'-M3') applied to the input side of register 705. Delayed signals M0" and M2" are delivered to opposed inputs of multiplexer 706. Delayed signals Ml" and M3" are delivered to opposed inputs of multiplexer 707. The select terminals of multiplexers 706 and 707 are both driven by the CAPEND8B signal.
  • multiplexers 706 and 707 deliver respective signals M0" and Ml" to the 4-bit wide input of register 708.
  • multiplexers 706 and 707 deliver respective signals M2" and M3" to the 4- bit wide input of register 708.
  • Register 708 is clocked by the video reference clock signal CV25M, as are registers 701, 702 and 705.
  • the 4-bit wide output of register 708 couples to the input of 4-bit wide register 709.
  • Register 709 is also clocked by the CV25M signal.
  • the output of register 709 defines a first multiplexed, modified choice signal MxO (2 bits wide) and a second multiplexed, modified choice signal Mxl (2 bits wide) .
  • the delay from the input of choice making unit 457 (Fig. 4B) to the output of register 705 is approximately two ticks of the video reference clock CV25M.
  • the delay from the output of register 705 to the output of register 709 is two more ticks of the video reference clock CV25M.
  • the total delay of choice making unit 457 and MUXCAP unit 458 is four ticks of the video reference clock CV25M. This matches the four-tick signal- propagation delay time of the CLUT units 451 and 452 (Fig. 4B) .
  • Fig. 8 shows the internal structure of interpolator 459.
  • Interpolation 459 is divided into respective R, G and B units, 800R, 800G and 800B (e.g., red, green, blue color handling units) . Only unit 800R is shown in detail. Units 800G and 800B are understood to have internal similar structures.
  • Unit 800R receives the 8-bit wide "R" components of each of the 24-bit wide, destacked signals, LPxO, LPxl, LPx2, LPx3, and produces a corresponding 8-bit wide ROUT signal.
  • Unit 800G receives the 8-bit wide "G” components of each of the 24-bit wide, destacked signals, LPxO, LPxl, LPx2, LPx3, and produces a corresponding 8-bit wide GOUT signal.
  • Unit 800G receives the 8-bit wide "G” components of each of the 24-bit wide, destacked signals, LPxO, LPxl, LPx2, LPx3, and produces a corresponding 8-bit wide GOUT signal.
  • Unit 800B receives the 8-bit wide "B" components of each of the 24-bit wide, destacked signals, LPxO, LPxl, LPx2, LPx3, and produces a corresponding 8-bit wide BOUT signal.
  • Output signals ROUT, BOUT and GOUT combine to form a 24-bit wide output signal RGBOUT.
  • multiplexer 710 picks one of the R values of destacked signals, LPxO, LPxl, LPx2, LPx3, in accordance with the MxO choice signal supplied to a control terminal of multiplexer 710.
  • Multiplexer 710 supplies the picked LPx value to the A-input of first adding unit 712.
  • multiplexer 711 picks one of the R values of destacked signals, LPxO, LPxl, LPx2, LPx3, in accordance with the Mxl choice signal supplied to its select control terminal.
  • Multiplexer 711 supplies the picked LPx value to the B-input of first adding unit 712.
  • First adding unit 712 generates first-sum signal 714 during each tick.
  • This first-sum signal 714 represents the sum of two nonexhaustively chosen ones of destacked R signals, LPxO, LPxl, LPx2, LP 3.
  • the first-sum signal 714 is stored into a respective one or the other of registers 721 and 722.
  • registers 721 and 722 respectively store, in pipelined fashion, the sums of a first chosen pair (current pair) and a second chosen pair of values (previous pair) selected from the set of destacked R signals, LPxO, LPxl, LPx2, LPx3.
  • Carry-out signals (addition overflows) 715 produced by each pipelined addition step of adder 712 are simultaneously stored on alternating ticks in one or the other of registers 723 and 724. Signals designated as "current” become “previous” data in the next successive tick. Computation therefore proceeds through the circuit in pipeline fashion.
  • Second adding unit 730 generates a second-sum signal 734 during each tick.
  • This second-sum signal 734 represents the sum of the four destacked R signals, LPxO, LPxl, LPx2, LPx3 chosen by modified choice signals MO ⁇ S.
  • a carry-out signal (addition overflow) 738 produced by adder 730 is supplied to a C input of a carries- adding unit 740 by way of inverter 739.
  • Carries-adding unit 740 is two-bit plus carry adder with an inverted, 2-bit wide output, 740oB.
  • Inverted versions of the carry-out signals previously generated by adder 712 in successive ticks and stored in registers 723 and 724 are applied to A and B inputs of carries-adding unit 740. It turns out that the process of inverting three 1-bit values, adding them, and inverting the 2-bit result is logically equivalent to a noninverted addition of the three values. Circuit size is minimized and use of two additional inverters is saved in the circuitry of Fig.
  • the 2-bit wide output 740oB of unit 740 represents the sum of the three carry bits generated respectively by a first tick addition in adder 712, a second tick addition in adder 712, and the subsequent addition in adder unit 730.
  • the second-sum signal 734 passes through a divide- by-four unit 735 where it is shifted right by two bit positions (e.g., a hard-wired shift right of two).
  • the result signal 736 output by divide-by-four unit 735 then represents the less-significant 6 bits (ROUT bits 5:0) of the sum of four chosen ones of destacked R signals, LPxO, LPxl, LPx2, LPx3, divided by four.
  • ROUT bits 5:0 the less-significant 6 bits
  • Result signal 736 is synchronized to the video clock signal CV25M by storing it in register 737.
  • the signal output by synchronizing register 737 represents bits 5:0 of the earlier-mentioned ROUT signal.
  • Carries-sum signal 740oB represents the more-significant 2 bits (bits 7:6 of ROUT) of the sum of four chosen ones of destacked R portions of signals, LPxO, LPxl, LPx2, LPx3, divided by four.
  • Result signal 740oB is synchronized to the video clock signal CV25M by storing it in register 747.
  • the combined outputs of registers 737 and 747 form the 8-bit wide ROUT signal.
  • the produced RGBOUT signal of units 800R, 800G and 800B is ultimately transmitted out of the CLIO chip 430 and used to produce a corresponding light image on an appropriate display means (e.g. a color CRT or color LCD) .
  • an appropriate display means e.g. a color CRT or color LCD
  • the machine-internal 320-by-240 pixels low-resolution image (element 125 in Fig. 1) is transformed into a light image (element 165 in Fig. 1) that has an apparent high- resolution of 640-by-480 pixels.
  • the machine-internal 320-by-240 pixels low- resolution image (element 125 in Fig. 1) is transformed into a light image (element 165 in Fig. 1) that has an apparent high-resolution of 640-by-240 pixels.
  • the machine-internal 320-by-240 pixels low-resolution image (element 125 in Fig. 1) is transformed into a light image (element 165 in Fig. 1) that has an apparent high-resolution of 320-by-480 pixels.
  • the machine-internal 320-by-240 pixels low- resolution image (element 125 in Fig. 1) is transformed into a light image (element 165 in Fig. 1) that has a same apparent resolution of 320-by-240 pixels.
  • the invention provides for a number of different transformations from stored data (125) to physical light image (165) .
  • the transformation process need not be viewed as merely an interpolation process.
  • the user-supplied subposition signals (SP0-SP3) can be seen as means for changing the colors of produced pixels.
  • the user-supplied interpolation activating signals (HION, VION) can be seen as means for changing the apparent fuzziness or sharpness of the produced light image.
  • HION, VION interpolation activating signals
  • the appearance of the boundary can be highlighted by increasing or decreasing color intensity in the region of the boundary to create perception of a sharp edge.
  • the boundary can be blurred by smoothing the transition of colors and/or intensity as one moves from one image object to the next to thereby create a perception of a soft or rounded edge.
  • an appearance of different surface textures can be created by patterning subposition bits differently in areas that are to appear as different surfaces.
  • anti ⁇ aliasing effects can be created to remove the jagged edges appearance of angled lines by appropriate manipulation scattering of subposition values within a display image. The various effects are developed empirically by trying different distribution patterns of subposition values and observing the resultant effect on a CRT or other display means (e.g., LCD).
  • Each input/output "1" represents a logic true electrical or other signal
  • each input/output "0” represents a logic false electrical or other signal
  • each input/output "x” bit represents a logic don't-care electrical or other signal.
  • the code-conversion functions can be alternatively implemented in the form of a ROM (read only memory) circuit or a computer program or the like. (Copyright Notice: In so far that the subject matter of the code-conversion tables is coverable by copyrights, the copyright owner reserves all such rights except those expressly waived above.)
  • INPUTS A01,A00,A11,A10,A21,A20,A31,A30; OUTPUTS : B01,B00,Bll,B10,B21,B20,B31,B30; ⁇ TT> 00000000 01011010
  • CKTNAME HVOON
  • TYPE COMB
  • control word structure is as follows:
  • the Spryte-rendering engine is also controlled by certain "Preamble" words that accompany a so-called Spryte-control Block (SCoB).
  • One of the preamble words (the second one) contains controls that affect the subposition bits that are to be stored in VRAM.
  • the source data is totally literal.
  • the source data is totally literal.
  • For totally literal Sprytes there is a second preamble word. It contains the horizontal pixel count for each line of the source data and the word offset from one line of source data to the next. It also contains the other special bits needed for totally literal Sprytes. Note that these bits are only valid while the totally literal Spryte is being rendered. These bits are not used ...GATED AWAY... when the current Spryte is not totally literal.
  • B31->B24 WOFFSET(8). Word offset from one line of data to the next (-2) (8 bits). bits 23- > 16 of offset are set to 0.
  • B25->B16 WOFFSET(IO). Word offset from one line of data to the next (-2) (10 bits). bits 31->26 of offset are set to 0.
  • B10- > B0 TLHPCNT Horizontal pixel count (-1) (11 bits).
  • the TLLSB bits perform the same function that the IPNLSB bits perform in normal Sprytes.
  • the unpacker will disable the 'B' FIFO data requests and alternately place pixels from the source into both FIFOs. Left 16 bits go to 'A' FIFO, right 16 bits go to 'B' FIFO.
  • the data requests for 'A' FIFO will be made in a request 'pair' to insure the reduction of page breaks and '6 tick latencies'.
  • the hardware will lock the corner engines (regardless of the LCE bit).
  • TLHPCNT is the number of pixels in the horizontal dimension (-1). This is the number of pixels that will be attempted to be rendered for each horizontal line of the Spryte. This value is used by the data unpacker. A '0' in the value will attempt 1 pixel. A '-1' in the value will attempt many pixels. There is no 'zero pixel count' value.
  • WOFFSET is the offset in words of memory from the start of one line of data to the start of the next line (-2). If the BPP for this Spryte is 8 or 16, use WOFFSET(IO), else use WOFFSET(8). This number is a zero for the minimum sized Spryte (2 words).
  • WOFFSET and TLHPCNT By arranging WOFFSET and TLHPCNT correctly, you can extract a rectangular area of data our of a larger sized rectangular area of data.
  • the DMA engine will also use WOFFSET as the length value in the normal data fetch process. If WOFFSET and TLHPCNT are set badly, WOFFSET may expire first and the DMA engine will not cope properly.
  • image data is advantageously placed within independently addressable, parallel banks of a multi-bank video random access memory unit (VRAM) in order to perform multi-row interpolation without need for a row buffer for separately storing the image data of one or more entire rows during the multi- row interpolation.
  • VRAM video random access memory unit
  • a distance-weighted interpolation scheme can be approximated by averaging N low resolution values and that such an approximation can be carried out in a pipelined system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Image Processing (AREA)

Abstract

Un procédé et un appareil permettent d'améliorer la résolution apparente de l'image par interpolation de lignes multiples. Un procédé d'amélioration de la résolution de données d'image de faible résolution comprend les étapes suivantes: la mise à disposition d'une mémoire (420) à zones de mémorisation indépendamment adressables (420L, 420R); la mise en mémoire (420) des données d'image de faible résolution (125), de sorte que les données d'image de faible résolution qui définissent une première rangée de faible résolution (LR0) résident dans une première zone de mémorisation (420R) et que les données d'image de faible résolution qui définissent une deuxième rangée de faible résolution (LR1) adjacente à la première rangée de faible résolution (LR0) résident dans une deuxième zone de mémorisation (420L); l'extraction de premier à n signaux de pixels de faible résolution (S1-S3) de la mémoire (420), ces signaux représentant des valeurs de pixels de faible résolution dans les première et deuxième rangées adjacentes de faible résoltuion (LR0, LR1) des données d'image de faible résolution (125); et la génération d'un signal de pixel de haute résolution (Hpx) à partir desdits premier à n signaux de pixels de faible résolution (S1-S3) selon un algorithme à distance pondérée.
PCT/US1992/009342 1992-11-02 1992-11-02 Amelioration de la resolution d'ecrans video par interpolation de lignes multiples WO1994010679A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU30585/92A AU3058592A (en) 1992-11-02 1992-11-02 Resolution enhancement for video display using multi-line interpolation
PCT/US1992/009342 WO1994010679A1 (fr) 1992-11-02 1992-11-02 Amelioration de la resolution d'ecrans video par interpolation de lignes multiples

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Application Number Priority Date Filing Date Title
PCT/US1992/009342 WO1994010679A1 (fr) 1992-11-02 1992-11-02 Amelioration de la resolution d'ecrans video par interpolation de lignes multiples

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EP1816600A3 (fr) * 2006-02-06 2008-08-20 Olympus Corporation Appareil de conversion de résolution de l'image
CN108109570A (zh) * 2016-11-14 2018-06-01 谷歌有限责任公司 用于有效传输的低分辨率rgb渲染
CN114245201A (zh) * 2021-11-25 2022-03-25 湖南翰博薇微电子科技有限公司 视频扩屏显示方法、装置、系统、计算机设备及存储介质
CN114760401A (zh) * 2022-04-14 2022-07-15 上海富瀚微电子股份有限公司 直接扩展图像处理芯片并行接口的输出视频分辨率的方法

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US4719509A (en) * 1985-01-10 1988-01-12 Yokogawa Medical Systems, Limited Video data interpolation apparatus
US4752826A (en) * 1986-10-20 1988-06-21 The Grass Valley Group, Inc. Intra-field recursive interpolator
US4866520A (en) * 1987-03-04 1989-09-12 Hitachi, Ltd. Video system for displaying lower resolution video signals on higher resolution video monitors
US5019903A (en) * 1989-05-04 1991-05-28 Sony Corporation Spatial interpolation between lines of a supersampled digital video signal in accordance with a gradient vector selected for maximum matching of blocks of samples which are offset in opposite directions
US5119082A (en) * 1989-09-29 1992-06-02 International Business Machines Corporation Color television window expansion and overscan correction for high-resolution raster graphics displays

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Publication number Priority date Publication date Assignee Title
US4656467A (en) * 1981-01-26 1987-04-07 Rca Corporation TV graphic displays without quantizing errors from compact image memory
US4719509A (en) * 1985-01-10 1988-01-12 Yokogawa Medical Systems, Limited Video data interpolation apparatus
US4752826A (en) * 1986-10-20 1988-06-21 The Grass Valley Group, Inc. Intra-field recursive interpolator
US4866520A (en) * 1987-03-04 1989-09-12 Hitachi, Ltd. Video system for displaying lower resolution video signals on higher resolution video monitors
US5019903A (en) * 1989-05-04 1991-05-28 Sony Corporation Spatial interpolation between lines of a supersampled digital video signal in accordance with a gradient vector selected for maximum matching of blocks of samples which are offset in opposite directions
US5119082A (en) * 1989-09-29 1992-06-02 International Business Machines Corporation Color television window expansion and overscan correction for high-resolution raster graphics displays

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1816600A3 (fr) * 2006-02-06 2008-08-20 Olympus Corporation Appareil de conversion de résolution de l'image
US7567733B2 (en) 2006-02-06 2009-07-28 Olympus Corporation Image resolution conversion apparatus
CN108109570A (zh) * 2016-11-14 2018-06-01 谷歌有限责任公司 用于有效传输的低分辨率rgb渲染
CN114245201A (zh) * 2021-11-25 2022-03-25 湖南翰博薇微电子科技有限公司 视频扩屏显示方法、装置、系统、计算机设备及存储介质
CN114760401A (zh) * 2022-04-14 2022-07-15 上海富瀚微电子股份有限公司 直接扩展图像处理芯片并行接口的输出视频分辨率的方法

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