WO1991018338A1

WO1991018338A1 - Switchable current source

Info

Publication number: WO1991018338A1
Application number: PCT/US1990/005896
Authority: WO
Inventors: James William Dawson; William Vincent Huott; Panagiotis Andrew Phillips
Original assignee: International Business Machines Corporation
Priority date: 1990-05-17
Filing date: 1990-10-15
Publication date: 1991-11-28

Abstract

A switchable current source is disclosed which permits switching of both the load current and the reference current of a current mirror simultaneously by means of a separate switching device. The switching device need not carry the entire load or reference current. The circuit saves all of the current during switch-off.

Description

SWITCHABLE CURRENT SOURCE

Cross-Reference to Related U.S. Patent Application

Reference is made to U.S. Patent Application

Serial No. 525,286 , filed contemporaneously herewith, by F. Montegari, entitled "Read/Write/Restore Circuit for Memory Arrays," and assigned to the assignee of the present invention.

Background of the Invention

1. Field of the Invention The present invention relates to current source and current mirror circuits, and more particularly to a switchable current source circuit.

2. Description of the Related Art

Current source and current sink circuits often are configured in the form of a current mirror, where a current for driving a load tracks a fixed or predetermined reference current. If it is further desired to switch the load current on or off in response to a select, enable, clock or other input signal, it is possible to include a switching device in the mirror circuit. The type and location of the switching device chosen may, however, have a materially adverse impact on the magnitude or stability of the load current, circuit switching speed, power dissipation, circuit size, degree of control or other characteristics, which could be critical in a semiconductor integrated circuit environment where high density and small size are desired. Switchable current sources and current mirrors have been proposed in the prior art, e.g., U.S. Pat.

Nos. 4,544,878; 4,677,323; and 4,274,014, but these proposals have a number of disadvantages. For example, in U.S. Pat. No. 4,677,323, a field-effect transistor (FET) is introduced in series within the branch of the current mirror that carries the load current, in order to provide a switching function.

This arrangement, however, requires the switching FET to carry the entire load current, thus requiring the switching FET to be a large device. In U.S. Pat. No. 4,544,878, switches 24 and 26 (FIG. 1) do not carry the load current, but other problems are present. For example, two switches are required, and switch 24 will introduce some impedance between the gates of FETs 16 and 20 , resulting in unequal currents in the two branches of the current mirror, a significant disadvantage when precision control is desired with respect to a fixed reference current.

Summary of the Invention

The present invention is intended to remedy the above-mentioned disadvantages and provide a current source circuit having a switching device capable of switching both the load current and the reference current on and off simultaneously, without affecting the relationship between the two currents, and without the need to pass the load or reference current through the switching device. Several alternative embodiments are disclosed, including BICMOS circuits (having both bipolar and FET devices on the same semiconductor chip) , and all-FET circuits. In one embodiment, the present invention comprises first and second controllable current sources or sinks directly coupled to each other through a common control line; a fixed current sink or source directly coupled to the first controllable current source or sink; and a switching device directly coupled to the common control line. in another embodiment, the present invention comprises: a first current source transistor having its conduction path coupled between a first node and ground, and having its control terminal coupled to a second node; a second current source transistor having its conduction path coupled between an external circuit and ground, and having its control terminal coupled to the second node; a switching transistor having its conduction path coupled between the first node and the second node, and having its control terminal arranged to receive a select signal; a first impedance coupled between a voltage source and the first node; and a second impedance coupled between the second node and ground.

Other variations and embodiments of the invention are also disclosed, and are discussed more fully in the detailed description below. Brief Description of the Drawings

To facilitate further description of the invention, the following drawings are provided in which: FIG. 1 is a functional block diagram of one embodiment of the present invention.

FIG. 2 is a partial schematic circuit diagram of one embodiment of FIG. 1.

FIG. 3 is a schematic circuit diagram of a specific embodiment of FIG. 2.

FIG. 4 is a partial schematic circuit diagram of an alternative embodiment of FIG. 1.

FIG. 5 is a schematic circuit diagram of the invention configured for use in a sense amplifier circuit.

FIG. 6 is a schematic circuit diagram of the invention configured for use in a bit line driver circuit.

FIG. 7 is a schematic circuit diagram of the invention configured for use in a word address receiver and true/complement generator circuit.

FIG. 8 is a schematic circuit diagram of the invention configured for use in a read/write control circuit. FIG. 9 is a schematic circuit diagram of the invention configured for use in an OR/NOR logic circuit.

Description of the Preferred Embodiments

Referring first to FIG. 1, the present invention includes a first controllable current source or sink

10 directly coupled to a second controllable current source or sink 12 via a common control line 11. Elements 10 and 12 may be either current sources or current sinks. Coupled to element 10 is a fixed current sink or source 16. If element 10 is a source, then element 16 should be a sink, and vice versa. In either case, element 16 is arranged to produce a fixed or predetermined reference current

(Iref) .

Coupled to source or sink 12 is an external circuit providing a load for which a load current is required to be supplied or removed. This load current (Iload) , which constitutes the "output" of the circuit, is preferably equal to or directly proportional to the reference current and is switchable in accordance with the invention, as will be described below. Completing the arrangement of

FIG. 1 is a switching element 18 having an input terminal arranged to receive a switching or enabling signal as its input, the switching element output being directly coupled to the common control line 11. A noteworthy feature of the invention is that switching element 18 is isolated from both the reference current and the load current, yet is able to control both simultaneously. Another feature is that although the output of element 18 taps onto the control line 11 between the two controllable sources or sinks 10 and 12, the switching element itself does not separate the control terminals of elements 10 and

12. Other features are that only one switching device is needed for the entire circuit, and that all of the power in the circuit is saved during switch-off. Additional switching elements may,. however, be added in series or in parallel with switching element 18, if desired.

Referring now to FIG. 2, there is shown a specific circuit embodiment of the arrangement of FIG. 1. In this embodiment, transistors Tl and T2 form first and second controllable current sinks 10 and 12, respectively, and are coupled together at their base terminals by common control line 11. Coupled to one end of the conductive path of Tl is a fixed current source Cl (16) , which sets a reference current flowing into node 1 (the collector of Tl) .

The source Cl is also coupled to a voltage source

VCC, and the other end of the conductive path of Tl is coupled to ground to complete the reference branch of the circuit. The load branch of the circuit is formed by the series connection of the conductive path of T2 with ground, a load 14 and a source VCC. In this manner, the current Iload in the load branch will mirror the current Iref in the reference branch.

A third transistor, Nl, comprises a switching element 18 and is coupled between node 1 and common control line 11. In this configuration, an impedance

Z is also included between line 11 and ground, in order to discharge the bases of Tl and 2 to ground for best operation.

Transistors Tl and T2 may be NPN bipolar transistors, transistor Nl may be an N-channel FET, impedance Z may be a resistor, and current source Cl may also be a resistor coupled to VCC, but the invention is not limited to the use of these particular device types. For example, Tl and T2 could be PNP bipolar transistors or FETs (either N-channel or P-channel) , Nl could be a P-channel FET, impedance Z could be an FET (N-channel or P-channel) , and current source Cl could be a temperature or voltage compensation circuit, it being understood that transistor types should be properly matched. It is preferred that impedance Z be substantially larger than any impedance inherently present in current source Cl , and that a BICMOS implementation be utilized.

The load 14 will typically be a current mode circuit, but the invention will also operate with other types of load circuits, with appropriate modifications as described below. Switching device

Nl permits the load current (Iload) to be turned on and off by way of a select or enable signal applied to the control terminal of Nl (here, the gate of FET Nl) . This provides several advantages over the constant current sources of the prior art, including the saving of power and the capability of performing additional logic with the loads of other current sources, if desired. A further advantage of the invention of FIG. 2 is that by switching only the bases of Tl and T2 with device Nl, there is no appreciable difference between the current levels Iload and Iref set by Cl or by any other scheme. Since the base currents of Tl and T2 are typically more than an order of magnitude smaller than the collector currents of each, the current flowing through Nl is very small and device Nl can be a very small device. Among other advantages, this will present a very small load to the circuit driving the select/enable signal.

In operation, when the select/enable signal goes high, Nl is turned on and the circuit behaves as a normal current mirror. When the select/enable signal goes low, Nl is turned off, and the current through the conduction paths (collector-emitter paths of bipolar transistors Tl and T2 , if FIG. 2 is being used) goes to zero since impedance Z pulls both bases low. Zero current also means zero power, which is a significant advantage in semiconductor applications and is a significant improvement over certain prior -8- art circuits which only shut off current to the load, meaning that only half the power is saved. In the present invention, also, both Iref and Iload both go to zero simultaneously during switch-off (assuming that Tl and T2 have the same characteristics) , and Nl does not carry the full load current Iload.

FIG. 4 shows an alternative embodiment of the invention using all FET devices for the current sources or sinks and the switching element. Here, PI is analogous to Tl in FIG. 2, P2 is analogous to T2 and P3 is analogous to Nl. The circuit of FIG. 4 has also been reoriented to form a switchable current source instead of the switchable current sink of FIG. 2. The circuits of FIGS. 1 , 2 or 4 can be used to drive virtually any current-mode load circuit or any voltage-mode load circuit with an impedance low enough to prevent the transistor sourcing or sinking the load current (such as T2 in FIG. 2) from saturating. Even this, however, is not a limitation with the FET-only version shown in FIG. 4 (although current matching between Iref and Iload may be slightly less accurate) . Even a high impedance voltage-mode circuit can be driven if a clamp is added to prevent saturation (such as a diode between control line 11 and the collector of T2) , although some loss in current mirroring accuracy may be experienced.

Typical applications of the present invention are shown in FIGS. 3 and 5-9. In FIG. 3, the invention, which comprises devices Tl, T2, Nl, Rl and R2 in this embodiment, controls a differential current switch formed by T3 , T4, R3 and R4. Resistor Rl, coupled to voltage source VCC, operates as the current source Cl of FIG. 1, and the impedance Z is provided by resistor R2. In this embodiment, the invention operates as a switchable current sink.

FIG. 5 shows an application of the invention in a sense amplifier circuit for use in a semiconductor random access memory. Here, a bit selection function is performed via devices Nl, N3 , N5, etc. The sense amplifiers for the number of desired bit columns can all be dotted together as shown, with each sense amplifier having its own switchable current source (or sink) with a unique bit select input signal. In a typical application, only one bit select signal will be on (high) at any given time, selecting the corresponding sense amplifier/bit column. Also shown in this embodiment is the use of two switching devices in series for each column (such as Nl and

N2) , one of which performs a read enable function and the other of which performs a bit select function.

Other possible applications of the present invention are: a bit line driver circuit for use in a memory array (FIG. 6) ; a word address receiver and true/complement generator circuit (FIG. 7) ; a read/write control circuit (FIG. 8) ; and a logic circuit, sii h as a switchable OR/NOR circuit (FIG.

9). In Fit, 6, device N2 operates as an impedance and, hence, is analogous to the impedance Z of FIG.

2. In FIG. 9, a parallel, configuration of two switching devices (Nl and N2) is shown, which provides an overall "OR" function for the entire circuit. In addition, both outputs go high when the circuit is not selected.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

We claim:

Claims

1. A circuit comprising: first and second controllable current sources or sinks directly coupled to each other through a common control line; a fixed current sink or source directly coupled to the first controllable current source or sink; and a switching device directly coupled to the common control line.

2. The circuit of claim 1 in which the controllable current sources or sinks and the switching device each comprise a transistor, each transistor having a control terminal, the control terminals of the controllable current sources or sinks being directly coupled to the common control line and the control terminal of the switching device being arranged to receive a select or enable signal.

3. The circuit of claim 1 further including an impedance coupled to the common control line.

4. The circuit of claim 1 in which the fixed current sink or source comprises an impedance coupled to a voltage source.

5. The circuit of claim 1 in which the controllable current sources or sinks each comprise a bipolar transistor and the switching device comprises a field-effect transistor.

6. The circuit of claim 2 in which each transistor comprises a field-effect transistor.

7. A switchable current source or sink circuit comprising: first and second controllable current sources or sinks directly coupled to each other through a common control line and forming a current mirror; a fixed current sink or source directly coupled to the first controllable current source or sink; and a switching device directly coupled to the common control line for switching on or off currents flowing out of the first and second controllable current sources or sinks, such currents being equal at all times and being switched simultaneously, in response to an external select signal.

8. The circuit of claim 7 in which the controllable current sources or sinks and the switching device each comprise a transistor, each transistor having a control terminal, the control terminals of the controllable current sources or sinks being directly coupled to the common control line and the control terminal of the switching device being arranged to receive the external select signals.

9. The circuit of claim 7 further including an impedance coupled to the control line.

10. The circuit of claim 7 in which the fixed current sink or source comprises a resistor coupled to a voltage source.

11. The circuit of claim 7 in which the controllable current sources or sinks each comprise a bipolar transistor and the switching device comprises a field-effect transistor.

12. The circuit of claim 8 in which each transistor comprises a field-effect transistor.

13. A switchable current source or sink circuit comprising: a first current source or sink transistor having its conduction path coupled between a first node and ground, and having its control terminal coupled to a common control line; a second current source or sink transistor having its conduction path coupled between an external load circuit and ground, and having its control terminal coupled to the common control line; a switching transistor having its conduction path coupled between the first node and the common control line, and having its control terminal arranged to receive a select signal; a first impedance coupled between a voltage source and the first node; and a second impedance coupled between the common control line and ground.

14. The circuit of claim 13 in which currents in the conduction paths of the first and second transistor are equal and are controllable by, but do not flow through, the switching transistor in response to the select signal.

15. The circuit of claim 13 in which the first and second transistors are of the bipolar type and the switching transistor is of the field-effect type.

16. The circuit of claim 15 in which the first and second transistors are of the NPN bipolar type and the switching transistor is of the N-channel FET type.

17. The circuit of claim 13 in which each transistor is of the field-effect type.

18. The circuit of claim 13 in which the first impedance has a value greater than that of the second impedance.

19. The circuit of claim 13 in which the first and second impedances are resistors.

20. The circuit of claim 1 in which either the first or the second impedance comprises a field-effect transistor.

21. The circuit of claim 1 configured for use in a sense amplifier circuit, for reading the bit lines of a memory cell array in response to one or more select signals.

22. The circuit of claim 1 configured for use in a bit line driver circuit for selecting the bit lines of a memory cell array during a read or write operation.

23. The circuit of claim 1 configured for use in a word address receiver and true/complement generator circuit for enabling an address function in response to a clock signal.

24. The circuit of claim 1 configured for use in a read/write control circuit for enabling a read/write control function in response to a clock signal.

25. The circuit of claim 1 configured for use in a logic circuit for enabling a logic function in response to one or more select signals.